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Hi, We have been using ProAsic+ (150) devices for about 9 months in production. I have two concerns with the part. 1) We have had a high drop out in programming with the Flashpro. I don't know exactly what the problem is here. We have had the Actel FAE in and the factory involve but can not determine the problem. However, we are using a special test jig to program the devices because there is not enough room on the board for a programming connector. This may contribute to the probelm. We eventually plan to get the parts programmed out of house so we are not real concerned about the high fallout. 2) We have produced about 1000 boards with the ProAsic+ and have had 20 boards that fail to "startup" properly. I actually had one device start to go into thermal run away. This probelm seems to be somewhat dependent on the power supply, but not positive about that. However, a "good" device will startup under all conditions it seems. I am still investigating this one. All in all they appear to do the job and we are pleased with them. As far as ProAsic3 ... they will be available RSN Dave Colson "SG" <gupt@hotmail.com.NOSPAM> wrote in message news:m3vff8yxjs.fsf@agni.ics.uci.edu... > > Hi all > > I am evaluating the Actel ProAsic Flash-based FPGAs and am wondering > if anyone has experience using them. The claim from Actel is that > they have new products in 0.13u that are smaller in area than > comparative Xilinx/Altera products (Spartan/Cyclone) and offer better > performance. They claim this is because instead of using 6 SRAM > transistors for the configuration memory, the Actel Pro-Asic 3s use 1 > Flash transistor. This reduces die are for the same number of logic > elements/gates and increases performance due to shorter wires in the > die. > > Any experiences with the Pro-Asic line ? Even better, has anyone used > the new 0.13u FPGAs (engineering samples or something or maybe just > using tools) ? > > Thanks > SumitArticle: 72576
I just upgraded Xilinx ISE and Chipscope from version 6.1.03 to 6.2.03=20 with the result that my design doesn't work anymore. Well, it=20 synthesises etc, but the result doesn't work as good as it did before.=20 That is, the system doesn't work very good apart from the heart beat LED = on my board. Also, Chipscope can't connect through my Parallel Cable IV anymore,=20 which is quite mysterious. Are there any reasons for me to spend/waste time to trying make it work, = or should I just swap back to 6.1? --=20 ----------------------------------------------- Johan Bernsp=E5ng, xjohbex@xfoix.se Embedded systems designer Swedish Defence Research Agency Please remove the x's in the email address if replying to me personally.Article: 72577
If I try to start my Quartus-Project by double-click on the QPF-File an error-window pops up. I found the mistake: in the path to start quartus there are / instead of \ (I'm using Windows not Linux!). If I change the Link, the double-click will work one time, thereafter Quartus seems to changes the Link again to the wrong one :-( Can someone help? Thanks, ManfredArticle: 72578
soar2morrow@yahoo.com (Tom Seim) wrote in message news:<6c71b322.0408241439.30dde21e@posting.google.com>... > "Georgi Beloev" <gbH8SPAM@beloev.net> wrote in message news:<SYydnTMglL5u-7fcRVn-gw@megapath.net>... > > Hi, > > > > I'm looking for an inexpensive (up to $1000) development board with the > > following features: > > > > - Relatively fast DSP, e.g., Blackfin. > > - Mid-range Cyclone II or Spartan-3 FPGA. > > - At least 4 MB SDRAM. > > - Video in (CVBS and Y/C), digital video decoder. > > - Video out (CVBS and Y/C), digital video encoder. > > - The video decoder and encoder should be able to work simultaneously. > > > > A combination of boards, e.g., a DSP kit and a plug-in FPGA board can also > > work. Other DSPs and FPGAs than the ones mentioned above can also be > > considered. This is for doing research on video processing and video > > compression; I don't have more precise requirements yet. > > You could combine a Spartan-3 board from Digilent ($89) with ADI > ADSP-2199XX EZ-KITE Lite ($595). I think a better (and maybe more powerful) approach is to use the spartan-3 board from Xilinx (I think is the same as by Digilent) with the BF-561 EzLite. Regards, JaaCArticle: 72579
"SG" <gupt@hotmail.com.NOSPAM> wrote in message news:m3vff8yxjs.fsf@agni.ics.uci.edu... > > Hi all > > I am evaluating the Actel ProAsic Flash-based FPGAs and am wondering > if anyone has experience using them. The claim from Actel is that > they have new products in 0.13u that are smaller in area than Hi Sumit, the rumor about ProAsic G3 and G4 has been around for a long time, so long I already started to think its all waporware. But there seems to be at least some announcement of availability in Q4 2004, still that almost all the info. You mentioned "3" does it mean the products to be unveiled are that of Generation 3 not 4? To my knowledge G4 should have embedded Flash user block memories not available in G3, so what is to be announced? As so long time has passed since the initial G3/G4 info leak I would assume the ProAsic3 as you named it would actually gen4? As of the info you asked I guess its still all under NDA or available only for EAP partners :( I do have ProAsic+ starterkit and have played around a little but the +11,5 and -16.5 voltage programming and requirement to have special electrolytic capacitors on those pins doesnt make it very lucrative. That all may change with ProAsic3 - I hope it changes the FPGA landscape! Antti PS as you do seem to have more recent info could you enlighten all the info that you can share?Article: 72580
Håkon - I faced a similar problem recently (in a Verilog design). I ended up writing a Perl script that puts the current time stamp in an include file. The next time the design synthesizes, it gets the new date. Note that it requires a re-synthesis, it will not increment on just a new routing. If you're interested in this, look back through this news group for the article I posted. The thread was around July 21. John P. "Håkon L" <agurk.haklis@hotmail.com> wrote in message news:<cghcv9$r1v$1@newstree.wise.edt.ericsson.se>... > Hi, > I have usually included a version register in my FPGA designs, but I have to > change/increment it manually in the VHDL code. > > Does anybody have an idea for how one can make an auto-incrementing version > ROM which increments with each new routing? > What is the most easy way to manipulate the ROM? Can I manipulate the .bit > file? Run CoreGen automatically? > > Regards > Håkon LislebøArticle: 72581
In as far as I heard from their distributors/FAEs, the 0.13u ProASICs will be available Q4 this year. They seem to claim they are on track to delivering, but that is what they are going to say. I have seen presentations by John East (CEO, Actel) that seem to point to them aggressively pushing the ProASIC Flash-FPGAs. By the way, I don't know much about which generation they are on (I always get confused about 3/4 etc), so don't go by what I said. On their website, they just call it the ProASIC+ family. I was hoping that someone who has the "engineering samples" would shed some more light ... Thanks SumitArticle: 72582
SG <gupt@hotmail.com.nospam> wrote: ... : I was hoping that someone who has the "engineering samples" would shed : some more light ... Probably he also has a NDA... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 72583
I'm trying to frequency match a number of ring oscillators placed over a Xilinx FPGA. The intention is to use the oscillators as thermometers. Each ring oscillator is a chain of 7 LUTs configured as NOT gates. The problem is that the frequency output varies by as much as 10% (e.g 150 - 165Mhz). While it is not absolutely essential to match the frequencies, I would like to know the source of this difference. Could any of you throw some light on this? Thanks. The LUTs have been placed using RLOCs, so the oscillators have the same logic structure. Is it possible that the routing method is different? If so, is it possible to constrain them to be the same? Thanks, Siva --------------------------- "In the end, everything is a gag." - Charlie ChaplinArticle: 72584
Johan Bernspång wrote : > Also, Chipscope can't connect through my Parallel Cable IV anymore, > which is quite mysterious. > Are there any reasons for me to spend/waste time to trying make it work, > or should I just swap back to 6.1? Consider using simulation and synchronous design as an alternative to logic analysis. -- Mike TreselerArticle: 72585
Siva, you are getting a 7 ns delay from 7 concatenated inverters, about 1 ns per LUT. A 10% difference means about 100 ps. I am not so surprised.You might look at the routing details. Another approach is using the carry chain. It has less "undesirable freedom" of routing, and much finer granularity. So you need more stages, but they involve no discretionary routing, and are automatically floorplanned to be vertical. The only "trouble" could come from the return path. Let me know if this is any better. Peter Alfke, Xilinx > From: Siva Velusamy <sv7d@adder.cs.Virginia.EDU> > Organization: University of Virginia > Newsgroups: comp.arch.fpga > Date: Wed, 25 Aug 2004 14:27:02 -0400 > Subject: ring oscillator calibration > > > I'm trying to frequency match a number of ring oscillators placed over a > Xilinx FPGA. The intention is to use the oscillators as thermometers. > > Each ring oscillator is a chain of 7 LUTs configured as NOT gates. The > problem is that the frequency output varies by as much as 10% (e.g 150 - > 165Mhz). While it is not absolutely essential to match the frequencies, I > would like to know the source of this difference. Could any of you throw > some light on this? Thanks. > > The LUTs have been placed using RLOCs, so the oscillators have the same > logic structure. Is it possible that the routing method is different? If > so, is it possible to constrain them to be the same? > > Thanks, > Siva > --------------------------- > "In the end, everything is a gag." > - Charlie ChaplinArticle: 72586
"Manfred Balik" <e8825130@stud4.tuwien.ac.at> wrote in message news:<412c8a07$0$11094$3b214f66@tunews.univie.ac.at>... > If I try to start my Quartus-Project by double-click on the QPF-File an > error-window pops up. > I found the mistake: in the path to start quartus there are / instead of \ > (I'm using Windows not Linux!). > If I change the Link, the double-click will work one time, thereafter > Quartus seems to changes the Link again to the wrong one :-( > > Can someone help? > > Thanks, Manfred Hi Manfred, Can you elaborate some more. When you say there is a Link, where is the link and how did your create it? I have the following entries for my environment variables PATH %QUARTUS_ROOTDIR%\bin; QUARTUS_ROOTDIR D:\quartus41 I have been double clicking on qpf's and launching Quartus II 4.1 without any problems. Also the Quartus II shortcut on my desktop points to D:\quartus41\bin\quartus.exe. You can send me email to pursue this further. Subroto Datta Altera Corp.Article: 72587
On Wed, 25 Aug 2004 14:27:02 -0400, Siva Velusamy <sv7d@adder.cs.Virginia.EDU> wrote: >I'm trying to frequency match a number of ring oscillators placed over a >Xilinx FPGA. The intention is to use the oscillators as thermometers. These will also be sensitive to Vcc, which may change over the chip depending on what else is going on in that area. You could see the effect of this by varying VCC externally, to get some sense of how much this effects frequency. >Each ring oscillator is a chain of 7 LUTs configured as NOT gates. The >problem is that the frequency output varies by as much as 10% (e.g 150 - >165Mhz). While it is not absolutely essential to match the frequencies, I >would like to know the source of this difference. Could any of you throw >some light on this? Thanks. There could be differences in the speed of the LUTs, but routing is also a major contributor, including the path that leaves the ring oscillator, and goes to whatever you are using to measure frequency, as this must load one of the nodes in the oscillator. >The LUTs have been placed using RLOCs, so the oscillators have the same >logic structure. Is it possible that the routing method is different? If >so, is it possible to constrain them to be the same? If you are just relying on the normal tool flow for routing, this prpbably is a major part of the variability. You can hand route the design in the FPGA Editor, where you can make detailed routing decissions, and when you make multiple oscillators, you can manually route them identically. Once you have done this, there is a facility in the FPGA editor to save the routing details as a constraint. This is called a Directed Routing Constraint. This can be placed into your UCF file and providing you dont change the logic of the oscillators, and their final placement (RLOCs + RLOC_ORIGIN), these constraints will give consistent results. You will find it under the Tools menu list, I believe. Read and enjoy. Also a search of the FPGA-FAQ archive http://www.fpga-faq.com/archives/index.html with "directed" turns up lots of articles. >Thanks, >Siva Philip =================== Philip Freidin philip.freidin@fpga-faq.com Host for WWW.FPGA-FAQ.COMArticle: 72588
Peter Alfke wrote: > Siva, > you are getting a 7 ns delay from 7 concatenated inverters, about 1 ns per > LUT. A 10% difference means about 100 ps. I am not so surprised.You might > look at the routing details. > Another approach is using the carry chain. It has less "undesirable freedom" > of routing, and much finer granularity. So you need more stages, but they > involve no discretionary routing, and are automatically floorplanned to be > vertical. The only "trouble" could come from the return path. > Let me know if this is any better. > Peter Alfke, Xilinx Peter's suggestion is probably the best, but since you are this far under the bonnet, I did see some interesting numbers in an Altera white paper: http://www.altera.com/literature/wp/wpstxvrtxII.pdf Here, Altera identify and specify different delays for the various paths into the LUT (Fig 2), whilst Xilinx use a nominal, fixed time. From this, not all LUT paths are equal, and there seems a large variance in delays ( appx 5:1 ). It is not clear if Xilinx have 'no skews', or if their software does not yet support this, so there is no point in them specfying any differences. You should also start your Ring Osc's from a forced/reset state ( ie use NAND/NOR chain, rather than NOT ) -jgArticle: 72589
"Siva Velusamy" <sv7d@adder.cs.Virginia.EDU> wrote in message news:Pine.GSO.4.58.0408251416240.26669@adder.cs.Virginia.EDU... > > I'm trying to frequency match a number of ring oscillators placed over a > Xilinx FPGA. The intention is to use the oscillators as thermometers. > Why do you have multiple oscillators? Are you trying to take the temperature over several different parts of the die? I would think that the entire die would have the same temperature. I like Peter's carry chain idea a lot. -KevinArticle: 72590
AFAIR, FPGA express license was locked to the Hard disk volume serial number (8-digits). If you still have the same PC and the license file, you should be able to setup the FPGA express license. Also, if you search in the archives of this newsgroup, there has been some discussions on this topic and some even suggested a tool which could change the hard-disk serial number to what you want. However this will work only if you still have the original fpga express license file. If this option does not work, Mentor's Leonardo Spec still supports Spartan/XL (Precision does not). Maybe you should contact Mentor to see if they can help. Synplify also supports these devices. --Neeraj "Guenter Dannoritzer" <dannoritzer@web.de> wrote in message news:cgbvti$pph$00$1@news.t-online.com... > Hi, > > rickman wrote: > > Guenter is asking about the synthesis tools. The "classic" Xilinx tools > > do not include synthesis. They did back when they were current, but > > they no longer do. > > > > > > Vanheesbeke Stefaan wrote: > > > >>hi, > >> > >>I think for the newer generation chips you need fpga express 3.6. > >> > >>Or using the free tools downloaded from Xilinx website. The last is probably > >>the best thing to do, since Xinlinx doesn't sell fpga express anymore, and I > >>believe that FPGA express is not on the market anymore. > >> > >>"Guenter Dannoritzer" <dannoritzer@web.de> wrote in message > >>news:cg56f3$r5l$05$1@news.t-online.com... > >> > >>>Hello, > >>> > >>>I need to change some logic for a board with Spartan XL chip. I got ISE > >>>3.3 Foundation installed and when I want to synthesize, it tells me that > >>>it cannot check out a license. Doing some diagnostics with the licenses > >>>utility it tells me that the FPGA Express licenses expired in 2002. > >>> > >>>Does that mean I have to buy another FPGA Express licenses to do the > >>>synthesis? > >>> > >>>Seems like synthesis is not for free for those old chips? I guess I > >>>could try using a newer version, like 4.1, but I am not sure when the > >>>FPGA Express licenses for this one will expire. > >>> > >>>I searched in the archives for similar postings. I found some older > >>>postings from last year. I read from people keeping older versions of > >>>the software. Do they buy an update of the FPGA Express license? > >>> > >>>Did I do something wrong with the FPGA Express licenses and I can > >>>actually still use it? > >>> > >>>Thanks for the help. > >>> > >>>Guenter > > > > > > What option do I have? I seems like the newest versions of synthesis > tools like Precision do not include the Spartan XL chip either? > > Can I buy a license for an old version? > > So FPGA Express does not work either because Xilinx does not sell it > anymore? > > Thanks. > > Guenter >Article: 72591
"John Providenza" <johnp3+nospam@probo.com> wrote in message > I faced a similar problem recently (in a Verilog design). > I ended up writing a Perl script that puts the current > time stamp in an include file. The next time the design > synthesizes, it gets the new date. Note that it requires > a re-synthesis, it will not increment on just a new routing. > > If you're interested in this, look back through this news group > for the article I posted. The thread was around July 21. > > John P. Thank you, I'll look into that. BR HåkonArticle: 72592
Thanks everyone for the suggestions. The problem was clearly due to difference in routing. Using FPGA Editor's directed routing, I obtained the routing information for one particular placement, and simply copied them over for all other instances only substituting the correct net names. Now all the frequencies are in a 2% range, far better than the 10% earlier. Peter - Could you explain a bit more about how to use the carry chain? From the docs I could see that the carry chain goes up vertically through the slices, so I understand the part about automatic floorplanning - but how exactly should I configure them? There is no local connection between Cin and the CI/DI inputs. So I cannot directly send the carry signal as the select for the subsequent mux. Also, for this application I don't have any target frequency - I only need a predictable response with variation in temperature. So I probably don't need more stages. Kevin - Yes, I am trying to measure the temperature over different parts of the die. Specifically I am interested in the temperature gradient. There have already been papers (in FPGA 04 for instance) that have shown that a gradient exists. Siva --------------------------- "In the end, everything is a gag." - Charlie Chaplin On Thu, 26 Aug 2004, Kevin Neilson wrote: > > "Siva Velusamy" <sv7d@adder.cs.Virginia.EDU> wrote in message > news:Pine.GSO.4.58.0408251416240.26669@adder.cs.Virginia.EDU... > > > > I'm trying to frequency match a number of ring oscillators placed over a > > Xilinx FPGA. The intention is to use the oscillators as thermometers. > > > Why do you have multiple oscillators? Are you trying to take the > temperature over several different parts of the die? I would think that the > entire die would have the same temperature. > > I like Peter's carry chain idea a lot. > -Kevin > > >Article: 72593
Well, Xilinx' new device driver for the parallel cable is obviously more = concervative than the previous. I have to manually disconnect impact=20 from the cable before connecting the ChipScope Analyzer and vice versa. After restarting the design from scratch, and adding all cores one by=20 one ISE 6.2 seem to understand what I want it to do. Though the system=20 doesn't work as good as the one synthesized by ISE 6.1 yet. Mike, in my application it is quite hard to generate a proper test=20 vector (FM-modulated radio signal), whereas doing logic analysis using a = real radio or a signal generator as input is straight forward and gives=20 good insight on what's happening in the system. As far as I'm aware, the design is fully synchronous. How would=20 synchronous design be an alternative to logic analysis? Does the=20 insertion of ChipScope cores make the design asynchronous? /Johan Mike Treseler wrote: > Johan Bernsp=E5ng wrote : >=20 >=20 >>Also, Chipscope can't connect through my Parallel Cable IV anymore,=20 >>which is quite mysterious. >>Are there any reasons for me to spend/waste time to trying make it work= ,=20 >>or should I just swap back to 6.1? >=20 >=20 > Consider using simulation and synchronous design > as an alternative to logic analysis. >=20 > -- Mike Treseler --=20 ----------------------------------------------- Johan Bernsp=E5ng, xjohbex@xfoix.se Embedded systems designer Swedish Defence Research Agency Please remove the x's in the email address if replying to me personally.Article: 72594
Siva Velusamy <sv7d@adder.cs.virginia.edu> wrote: : Thanks everyone for the suggestions. : The problem was clearly due to difference in routing. Using FPGA Editor's : directed routing, I obtained the routing information for one particular : placement, and simply copied them over for all other instances only : substituting the correct net names. Now all the frequencies are in a 2% : range, far better than the 10% earlier. : Peter - Could you explain a bit more about how to use the carry chain? : From the docs I could see that the carry chain goes up vertically through : the slices, so I understand the part about automatic floorplanning - but : how exactly should I configure them? There is no local connection between : Cin and the CI/DI inputs. So I cannot directly send the carry signal as : the select for the subsequent mux. Also, for this application I don't have : any target frequency - I only need a predictable response with variation : in temperature. So I probably don't need more stages. : Kevin - Yes, I am trying to measure the temperature over different parts : of the die. Specifically I am interested in the temperature gradient. : There have already been papers (in FPGA 04 for instance) that have shown : that a gradient exists. Well, if you are interested into the thermal behaviour, you probably don't want to run the stages of the ring oscillator at nearly full gate speed, as this will contribute to (local) heating... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 72595
I'm having trouble with a Nios processor that stops responding after an unpredictable time. It appears to be the result of liberally using interrupt enable/disable statements. These statements are in place to protect shared variables. However, I have some concerns: 1. The register window (CWP) manager can generate an exception that won't be serviced if interrupts are disabled. It seems unlikely because there aren't many different interrupts to service - so not much save/restore. 2. The Nios documentation doesn't provide guidelines for acceptable use of interrupt code (ISR written in C). For instance, can I make subroutine calls (stack is available)? Compiled debug code is too large for my system memory so I am kind of stuck for debugging information. I'd be glad to hear from anyone who has had similar problems or knows about the low-level behavior of Nios. Thanks MattArticle: 72596
From where can i get a JTAG software . I have a FPGA chip and configuration bit file. So how shall i load the bits to FPGA chipArticle: 72597
Hi, In a timing simulation, Setup / Hold violation of Flip-Flop will result in value of 'x' at the output. Is that Right? If so, how double synchronisation circuits work in timing simulation ? Won't it propagate x. ? Regards, Muthu SArticle: 72598
> PS Also missing from this spin, is the fact that the cheapest > previous-generation MAX devices, are actually cheaper than the > cheapest MAX II devices. > ie the price per resource unit has declined, but the > minimum unit-cost step has actually increased, because they > pruned the two smallest offerings. Jim, Do you mean the 32 and 64 macrocells MAX1 devices are dead? And the 128 macrocells MAX1 is cheaper than the "198 macrocell" MAX2? Luiz Carlos.Article: 72599
On 26 Aug 2004 03:30:22 -0700, muthusnv@yahoo.co.in (Muthu) wrote: >In a timing simulation, Setup / Hold violation of Flip-Flop will >result in value of 'x' at the output. Is that Right? Usually so. It depends on how the model was written. Most FF models (in Verilog at least) put X on the output if there's a violation. This X will presumably be corrected on the next clock edge, unless there's another timing violation there. >If so, how double synchronisation circuits work in timing simulation ? >Won't it propagate x. ? Yes - at least for one clock cycle. Tedious stuff. Most people fake their way around this by replacing the first FF model in the resynchroniser with a FF model that doesn't propagate X. In most cases there are very few FFs that need to be modified in this way, so it's not very hard to do. And we hope that you have analysed your resynchroniser very carefully, so you are happy to accept the poor modelling because you already know (from the analysis) exactly how the resynchroniser behaves in all cases. It would be better if the FF model should do rather more accurate modelling of metastability: the output should go to X, then after some settling time it should go to a random choice of 0 or 1. Once you have decided to do this, it's easy to make the model even more accurate: use the precise time of the setup violation to determine how long the settling time should be, and to bias the random choice of 0/1. However, if you do this, the FF model will probably become very inefficient and slow to simulate; so, once again, you should apply this model only to the resynch FFs. There's another possible approach, which I have not tried. You could write some Verilog in your test fixture to sense the FF model's internal notifier register, and take control of the FF's output whenever the notifier toggles, using "assign" or "force". In this way there would be no need to modify the simulation netlist, but you would need to know the exact structure of the models. And it assumes that the test fixture and the models are all written in Verilog - although that's probably a fairly safe guess, for timing simulation. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
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