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Christian E. Boehme wrote: > However, apart from the fuzzy 5V compliance and tolerance > verbiage in the data sheet, that seems to answer my initial > question. I definately agree the description is fuzzy ;-) Lots of good info in the datasheet, but it sort of dances around that particular issue. -- Paul Fulghum paulkf@microgate.comArticle: 72776
Hi Wilhelm, Please contact the Altera Applications group. Also can you check if the dongle can be seen when the programming hardware is not connected to the dongle port? If the dongle can be seen without programming hardware, ask for a license tied to your NICID. Hope this helps. Subroto Datta Altera Corp. "Wilhelm Klink" <kommandantklink@hotmail.com> wrote in message news:6011e208.0408312252.3b0ef36@posting.google.com... > I'm running Quartus (versions 4.0 and 4.1) on a Dell Inspiron 8600, > with a dongle connected to the parallel port. The other day the > dongle stopped being detected in Quartus. A printer still works off > the port so it is fine, and port is set to ecp as required. The > dongle works with other machines I am using. Has anyone got a program > to determine the problem between the dongle and the parallel port? > Maybe I will have to resort to using a debug tool to locate the > problem.Article: 72777
Michal <NOmhusm@SPAMyahoo.com> wrote in message news:<ch2mig$ce6$1@nemesis.news.tpi.pl>... > Hi friends > > >>Paul N. wrote: > >>>I am currently in a FPGA Desgin course that required us to design a 64 > >>>bit floating point multiplier. I am very new to FPGA but have > >>>experience in VHDL and computer architecture design. Can anyone > >>>recommend a good book or a technical document on this subject matter? > >>>Any personal knowledge on how to start this project is much > >>>appreciated. > > You can try "Digital Signal Processing with FPGA" Second Edition by Uwe > Meyer-Baese (Springer 2004), there is subchapter about floating-point > arithmetic implementation. Very nice book for person with VHDL and com > arch experience. > > > john jakson wrote: > > And on the opposite side I was almost tempted to buy a text on FPU > > design with all the schematics given, I forget the title, pretty much > > all gate level, pity its not been brought up to date in HDL. IIRC it > > was a German -> English book to supplement a DLX design tought in > > schools. I figure the math books would be more usefull so the above > > ref, I'll look into also. The HW books though could be usefull in > > covering some of the thorny details. > > I think that the name of this book is "Computer Architecture-Complexity > and Correctness" by S.Mueller and W.J.Paul, also from Springer, with > chapters about fp arithmetics and data paths. > > Both of them discuss fp multipliers. These two books should be enought > for your design. > > Michal Indeed it was, thanks. If I see it again I may buy it this time. regards johnjakson_usa_comArticle: 72778
Vincent, Thanks for this, but I do have a MIF file that looks correct, and I regenerated the core after I associated the COE file with the core - but it still has the same error. Any help much appreciated! ThanksArticle: 72779
Paulo Dutra wrote: > You need SWIFT support which is available with EE version I believe. > http://support.xilinx.com/techdocs/14019.htm Modelsim SE has the swift support. > > shalini wrote: > >>what is the procedure to be followed to run MGT of Virtex2 Pro on >>modelsim5.8b (for windows XP operating system). Is there any packages >>to be included or model sim SE 5.8b version and project navigator 6.2i >>supports it. -- My real email is akamail.com@dclark (or something like that).Article: 72780
Hello, I have programmed EPLD only once using MAX+PLUS II, with necessary hardware already connected with PC. Now, I am in the situation that I need to figure out what is needed and how to set-up system to program MAX 3032ALC. I have an MPU, but it is 68 pins. I have seen some sort of adapters of different pins, could they be used somehow on 68 pin MPU? Could anybody point me to documents describing all these (programming with .pof file)? I also need to set-up for In-System Programming, so at later stage that would become helpful. I have never done that. I need guideline for that too. Thanks, DrewArticle: 72781
does anyone know of a simple PCI board that has a Virtex II connected directly to the PCI bus. Im looking for a very simple interface, no embedded pci bus controller (between the v2 and the bus itself) if possible -- Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science (will be updated soon) http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 72782
Geoffrey Wall wrote: > does anyone know of a simple PCI board that has a Virtex II connected > directly to the PCI bus. Im looking for a very simple interface, no embedded > pci bus controller (between the v2 and the bus itself) if possible > ... and what about a pci board with spartan-ii ? Do you really need the power of a v2? ... will be more easy to find a dev. board ;-) Laurent Gauch www.amontec.comArticle: 72783
Hi Vadim, Detailed information on LVDS usage for Stratix devices can be found in Volume 2, Chapter 5 of the Stratix Handbook. This is available online at http://www.altera.com/literature/hb/stx/ch_5_vol_2.pdf This Chapter has 76 pages and covers all aspects of High Speed Differential I/O Interfaces for Stratix. There is a section from Pg 60 onwards for Software Support. Information for LVDS usage in Cyclone devices can be found at http://www.altera.com/literature/hb/cyc/cyc_c5v1_04.pdf Hope this helps. Subroto Datta Altera CorpArticle: 72784
> Just to be clear, I have a layout akin to: > > top.v > |-top.ucf > +-middle.v > |-middle.ucf <-- contains floorplanner RPM > +-lower.v > +-lower.ucf <-- contains floorplanner RPM > > in my Webpack 'Sources in project' box. > > I have previously run Synthesize/Implement on 'middle.v' and 'lower.v' > and then edited the routed floorplan then saved as an RPM. When I then > run Synthesize/Implement on the 'top.v' module, the RPM's don't appear > to be being picked up (eg: the carry chains are in different relative > positions). > > Is there something I have to do, so that Webpack will pick up the > submodule UCF's ? I thought having them in the tree (and hence in the > project) would be sufficient. I tried a test case and here is how it works: Move middle.v to a separate directory. Synthesize it with xst to generate a ngc file (turn off I/O buffer insertion if needed). This ngc file does NOT have RPM info. Run floorplanner to floorplan the middle module and write out RPM constraints to middle.ucf. Now run ngcbuild (not ngdbuild) on the ngc file that xst generated. ngcbuild will read in middle.ucf and middle.ngc to create a new ngc file. This ngc file will have RPM info. You need to delete the old middle.ngc and rename the new ngc to middle.ngc. Move lower.v to another directory and do the same thing as above. Create two black box module files middle_bb.v and lower_bb.v with the same module name as middle.v and lower.v respectively and only the port definitions. In top.v, instantiate the two black boxes. Include the two black box files with your ISE project. Now run xst on top.v. Before you run translate (ngdbuild) on top.v, use -sd option to specify search path for the cores that were created. Then complete the implementation. HTH, Jim (jimwu88NOOOSPAM@yahoo.com remove NOOOSPAM) http://www.geocities.com/jimwu88/chipsArticle: 72785
Jim Wu wrote: >>Just to be clear, I have a layout akin to: >> >> top.v >> |-top.ucf >> +-middle.v >> |-middle.ucf <-- contains floorplanner RPM >> +-lower.v >> +-lower.ucf <-- contains floorplanner RPM >> >>in my Webpack 'Sources in project' box. >> >>I have previously run Synthesize/Implement on 'middle.v' and 'lower.v' >>and then edited the routed floorplan then saved as an RPM. When I then >>run Synthesize/Implement on the 'top.v' module, the RPM's don't appear >>to be being picked up (eg: the carry chains are in different relative >>positions). >> >>Is there something I have to do, so that Webpack will pick up the >>submodule UCF's ? I thought having them in the tree (and hence in the >>project) would be sufficient. > > > I tried a test case and here is how it works: > > Move middle.v to a separate directory. Synthesize it with xst to > generate a ngc file (turn off I/O buffer insertion if needed). This > ngc file does NOT have RPM info. Run floorplanner to floorplan the > middle module and write out RPM constraints to middle.ucf. Now run > ngcbuild (not ngdbuild) on the ngc file that xst generated. ngcbuild > will read in middle.ucf and middle.ngc to create a new ngc file. This > ngc file will have RPM info. You need to delete the old middle.ngc and > rename the new ngc to middle.ngc. > > Move lower.v to another directory and do the same thing as above. > > Create two black box module files middle_bb.v and lower_bb.v with the > same module name as middle.v and lower.v respectively and only the > port definitions. In top.v, instantiate the two black boxes. Include > the two black box files with your ISE project. Now run xst on top.v. > Before you run translate (ngdbuild) on top.v, use -sd option to > specify search path for the cores that were created. Then complete the > implementation. > > HTH, That doesn't just help, that's effort above and beyond the call, thankyou very much indeed - I'll give it a go as soon as I can :-)) Simon.Article: 72786
I am planning to purchase a Spartan 3 starter kit. It says: XC3S200-4FT256C included ISE Evaluation version 6.2i Can I build a complete VHDL design for the XC3S200 with free software (ISE Web Pack?) or do I have to purchase ISE BaseX or some other expensive software for hundreds of dollars ?Article: 72787
Before using xpower for my design, I decide to check for a simple
design of fibonacci series. I am facing following issues:
I am running xpower with vcd generated with post par simulation and
during parsing I encounter the following warnings:
WARNING:Power:91 - Can't change frequency of net CLK_BUFGP/IBUFG to
741.84Mhz.
WARNING:Power:91 - Can't change frequency of net CLK_BUFGP to
741.84Mhz.
WARNING:Power:91 - Can't change frequency of net CLK_BUFGP/IBUFG to
741.84Mhz.
WARNING:Power:91 - Can't change frequency of net CLK_BUFGP to
741.84Mhz.
...
The frequency for signals in data view shows some values inthe range
of 2-9% in all cases except CLK_BUFGP/IBUFGP and CLK_BUFGP.. Any
attempts to change this value results in power:91 warnings as above.
The confidence level shows Accurate. I am confused as the report shows
zero power for clock/ logic nets and still the confidence level is
accurate.
The report summary is :
Total estimated power consumption: 439
Peak Power consumption: 1081711
---
Vccint 1.50V: 65 98
Vccaux 3.30V: 100 330
Vcco33 3.30V: 3 11
---
Clocks: 0 0
Inputs: 0 0
Logic: 0 0
Outputs:
Vcco33 2 8
Signals: 0 0
---
Quiescent Vccint 1.50V: 65 98
Quiescent Vccaux 3.30V: 100 330
Quiescent Vcco33 3.30V: 1 3
Whats going wrong here? Anybody encountered similar problems?
Feedback/ help from Xilinx folks please.
--
Mukesh
Article: 72788Yes, you will be able to complete a VHDL design for the Spartan-3 Starter kit using the ISE Web Pack software. Shalin- Kroko wrote: > I am planning to purchase a Spartan 3 starter kit. > It says: > > XC3S200-4FT256C included > ISE Evaluation version 6.2i > > Can I build a complete VHDL design for the XC3S200 > with free software (ISE Web Pack?) or do I have to > purchase ISE BaseX or some other expensive software > for hundreds of dollars ? > > > >Article: 72789
Shalin Sheth <Shalin.Sheth@xilinx.com> wrote:
: Yes, you will be able to complete a VHDL design for the Spartan-3
^^^^
: Starter kit using the ISE Web Pack software.
s/will/should
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 72790Eric Crabill wrote: > If you are building a universal card, the "right" way > to do it is have two designs/bitstreams only differing > in what SelectIO Mode is used. Then, at power-on, use > an analog comparator to compare the slot's VIO with > ~4.15v (make it with a voltage divider...) and load one > of two bitstreams based on the result. Interestingly, that's very simlar to what I actually do right now: I am using two biased comparators comparing PCI 5V with PCI VIO such that even with maximum allowable voltage tolerances the result would be predictably correct. Until now I'd written the first word in config ROM with some well-known header telling the kind of config written to the ROM and warned the user (some LED or whatever) if there was some mismatch with the actual environment. But since there's ample space in the config ROM for at least two complete streams your suggestion is the _definitive_ way to go. It seems that I wasn't dreaming up too unusual things here ;-) Thanks & regards, Christian BoehmeArticle: 72791
Austin Lesea wrote: > Virtex and Spartan II are what I call "Classic" FPGA parts: they do 5V > PCI, they have hot insertion tri-state behavior, etc. In a way, the > last of the great simple FPGAs. Spartan II is just perfect for my projects. The one limitation that gave me some headaches and that was the number of different Vcco for IO banks available in PQFP versions (namely 1 ;). But that was about it already. I am actually more constrained by the software tools than by the target hardware. -ChrisArticle: 72792
Thanks Marlboro, I did what you recommended and find FPGA A reaches timing closure with the automatic pin assignment. Good lesson for me. But how can i minimize the effect of pin assignment? I think i should do floorplanning but i just don't know where to start. can you recommend me some documents about floorplanning? Thanks a lot.Article: 72793
On Sun, 29 Aug 2004 22:47:20 -0700, "Ying Hu" <huying@lastechnologies.com> wrote: >Frankly speaking, I know nothing about floorplanning. Could anyone >recommend any book/tutorial on this topic? I wrote this tutorial about 8 years ago, so it describes tools that don't exist on chips that are not available. Nevertheless, I think it still has enough info and comparison of effort to results, that I haven't taken the page down: http://www.fliptronics.com/floorplanning1.html The underlying constraint system and the make up of slices in todays FPGAs is quite similar to what I used for these examples. Final chips are displayed here: http://www.fliptronics.com/gallery.html and the last 5 designs show what can be achieved if one is really persistent. Philip Philip Freidin FliptronicsArticle: 72794
Hi, I am new to FPGAs and in as much I may be looking at a solution to my needs from the wrong perspective. So i shall list my needs intermixed with and concluding with what i think i need/want in a 'simple' FPGA board. A) will be running cryptographic primitives and massive amounts of number theory computations at it B) i need anywhere from 400,000 to 1.2 million gates (so probably a spartan 3 from xilinx, maybe cyclone 2 i dunno am more familiar with xilinx at labs) C) i need decent I/O rate ... not this bogus load via cable / serial blah blah blah. i am not sure what the USB 2.0 spec is nor if most cards that have that I/O ability ever reach its peak. so either i need pci interface or usb 2.0 D) fpga clock rate of 100mhz or greater E) i do NOT need other fluff useless-for-my-purposes components on the card [such as led interfaces, serial/parallel I/O, microcontrollers etc ad nauseum] F) if the avg i/o rate for the card is good so i can shuttle my data in and out then i wouldnt really need any high speed sram/dram. if it isnt so hot then 8 mb of 200 mhz or faster memory would be nice (heck 16 or 32mb if possible :) G) cost under $280 US [although if there are any 2 fpga cards [totalling over 1million gates] with the above features for under $450 US i'd be interested in that] H) software none needed i'd be creating some *nix and maybe win32 tools to go with my needs and upload the circuit layouts i need to run my gigs of data through (but if it came with some of its own gui layout tools that would save me a few weeks creation time *grin* so I wouldnt knock a gifthorse in the mouth) i looked at ... some from memtec that came closest to my needs spartan3LC and umm spartanIIPCI200 (or some model # close to that) also saw one from mesanet pci interface that was close ... but really seems like they have so many extra components driving up the price that would be completely useless to my needs NOW if no one knows of a manufacturer that has such a board does anyone know of enough freeware docs out there and can point me to them so i could make my own minimalist boards to the specs i need? [ee is not my thing nor is soldering but i can if i have to lol i prefer the closest i get to hardware is inserting new componentsin a pc and assembler routines for karatsuba/kcm/fft code :)] C++ya, xkeyArticle: 72795
That's not viable for me since I'm in Australia. I'm not using programming hardware on this computer. I have tried some diagnostic software from the Rainbow web site with no success. I might try calling our local Altera distributor. "Subroto Datta" <sdatta@altera.com> wrote in message news:<1OkZc.10208$FV3.129@newssvr17.news.prodigy.com>... > Hi Wilhelm, > > Please contact the Altera Applications group. Also can you check if the > dongle can be seen when the programming hardware is not connected to the > dongle port? If the dongle can be seen without programming hardware, ask for > a license tied to your NICID. > > Hope this helps. > Subroto Datta > Altera Corp. > > "Wilhelm Klink" <kommandantklink@hotmail.com> wrote in message > news:6011e208.0408312252.3b0ef36@posting.google.com... > > I'm running Quartus (versions 4.0 and 4.1) on a Dell Inspiron 8600, > > with a dongle connected to the parallel port. The other day the > > dongle stopped being detected in Quartus. A printer still works off > > the port so it is fine, and port is set to ecp as required. The > > dongle works with other machines I am using. Has anyone got a program > > to determine the problem between the dongle and the parallel port? > > Maybe I will have to resort to using a debug tool to locate the > > problem.Article: 72796
dhruvish@gmail.com (Drew) wrote in message news:<ad2011c0.0409010950.7e12dc2b@posting.google.com>... It's a 44 pin PLCC package. I figured out that I will have to use JTAG support provided by EPM3064-44 LC. I have never ever programmed with JTAG support. I have Byteblaster cable to download. Now, I dont know that how I setup things, I have my programming file, I will attach Byteblaster with the PC. But, what's the interface between ByteBlaster cable and EPLD? What do I need for that interface? Should I mount the EPLD somewhere, have some sort of port on the PCB which will connect eventually to the Byteblaster? Any intermediate circuitry needed? I appreciate any pictures of this sort of set-up.Article: 72797
Brian Dam Pedersen wrote: > ted wrote: > >> Hi, >> >> Does anyone know if it's possible to run the Xilinx ISE 4.2i software in >> Linux? I would like to develop VHDL code and then program my FPGA (I >> use a >> parallel port JTAG programmer). Being able to do this from Linux >> would make >> the project easier as I need to develop a Linux device driver at the same >> time. I was thinking I could use WINE. Do any websites with >> instructions >> exist? >> >> Thanks. >> >> > > Hi > > Programming the actual FPGA using JTAGcannot be done from within the ISE > - you need to find a third-party program to do that under linux, Such as xc3sprog for the Spartan 3 http://www.rogerstech.co.uk/xc3sprog/ but at > least ISE 6.x will run under Wine otherwise (mostly). See my page on how > to do it here: > > http://www.danbbs.dk/~kibria/xilinx.html > > Excellent. I was considering writing something on this myself, no I can just write a link:) BTW, I am using Wine 20040813 version and the command line tools work great. ise.exe loads but I don't use it. Regards Andrew -- Spartan3 configuration JTAG download tool for GNU/Linux available from http://www.rogerstech.co.uk/xc3sprog/Article: 72798
Hi all!
I am developing the firmware for a small project. I've completed the
design prototype stage in a XC4036-3HQ240 and I have had no major
problem.
When I "passed" (re-synth and P&R for the new part) the design to the
final device (XQ4036-3PG411) I've noticed that I'm unable to place a
single FF/Latch to work (10MHz). The same code works as expected in
the commercial version.
The configuration process is performed through the JTAG chain and is
OK (done high) as all combinational assignments are OK, but no
sequential (FF/Latch), independent on location of FF/Latch or of
Startup/BUFGP instantiation.
The symptoms resemble to reset being permentely asserted but I have the
reset pin hardwired to GND and the code performs reset when reset=1.
This implies that the chip is only reseted by the power-on-reset
performed when loading the bitstream. It doesnt seem to be this.
I'm using Leonardo for synthesis and Webpack Classics (ISE 4.2.03i)
for P&R and programming.
If any one as ever passed through this problem or have any idea how to
solve it please let me know.
Tanks in advance,
Rui Ferreira
--------------------------------------------------------------------------------
--This test code should generate a 5MHz clock on test_clock_o;
--output signal is always stuck at reset value ('1');
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY newtest IS
PORT (
comm_clock_i : IN STD_LOGIC; --10MHz signal
comm_reset_i : IN STD_LOGIC;
test_clock_o : OUT STD_LOGIC
);
END newtest;
ARCHITECTURE rtl OF newtest IS
SIGNAL test_clock : STD_LOGIC;
--------------------------------------------------------------------------------
BEGIN
p_process : PROCESS (comm_reset_i,comm_clock_i)
BEGIN
IF (comm_reset_i='1') THEN
--reset
test_clock <= '1';
ELSIF( comm_clock_i'EVENT AND comm_clock_i='1' ) THEN
test_clock <= NOT test_clock;
END IF;
END PROCESS p_process;
test_clock_o <= test_clock;
--------------------------------------------------------------------------------
END rtl;
Article: 72799"Duane Clark" <junkmail@junkmail.com> wrote in message news:ch4u8m016m6@news1.newsguy.com... > Paulo Dutra wrote: > > You need SWIFT support which is available with EE version I believe. > > http://support.xilinx.com/techdocs/14019.htm > > Modelsim SE has the swift support. > It's also an option for PE.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z