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soar2morrow@yahoo.com wrote: > Dirk Bruere at Neopax wrote: > >>Robert Baer wrote: >> >> >>>Eric Smith wrote: >>> >>> >>>>wtxwtx@gmail.com writes: >>>> >>>> >>>>>Why 'a plurality of N' or 'the plurality of N' must be used fo 'N' in >>>>>patent claims? >>>> >>>> >>>> >>>>Because patents are written to be legal documents, not engineering >>>>documents. Legal documents are written using traditions that have >>>>evolved over hundreds of years. Since patent examiners, lawyers, and >>>>judges all expect patents to be written in a certain way, if you >>>>submit an application that isn't written that way, you're just wasting >>>>money. >>> >>> Again, that is what i call "patent-ese". >>> Instead of "many" or "multiple" one sees "a plurality of". >>> Like i said, follow the terminology and useage that you find in other >>>patents that are closely related to your particular idea. >> >>Legalese is a very precise language, quite comparable to computer languages. >>If you ever see "...time is of the essence..." in a contract, prepare to run. > > > Legalese is designed to keep lawyers employed. It is not, by itself, > "precise". Contracts and other legal documents written in "plain > English" are just as enforceable as the legalese version. Maybe even > more so, because a jury (non-lawyers) can understand them. > > MOOYMMV. > > Tom Seim > Perhaps, but the question pertains to terminology in patents.Article: 94051
>But schematic entry oftem leads to non-registered designs, where you should >allow several month of debugging too... I can't quite figure out what that means. It sounds like forgetting to put in FFs to hold the data. But why does that happen more often with schematics than when using a HDL? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 94052
"Antti Lukats" <antti@openchip.org> wrote in message news:dpgq0c$rd1$02$1@news.t-online.com... > > there is no need to talk to the monitor at all, its only informative to > query the capabilities, monitor does not care if that info is accessed or > not. > > CH7301 however needs I2C initialization in order to be operational, this > both for Analog bypass and for DVI modes, with cold start defaults there > is no useable output from the CH7301, I assume its the same thing with the > other DVI transmitters > > we use an small PicoBlaze design to feed the CH7301 with register > initialization sequence > > if you are interested we have PCB boards ready for DVI tests, the PCB can > be fitted for you with just the DVI part that is the board would hold > > 1 DVI connector > 2 CH7301 > 3 power input jack > 4 power supply ics > 5 Cable IV header > 6 Virtex 4LX15 (or LX25 or FX12) > 7 Clock oscillator > > the board has some other components as well that can be fitted, > unfortunatly I dont have full specs or pictures ready, please email me if > interested > > Antti Thanks, Antti. I'll contact you if we need a board. RobArticle: 94053
Good day, I am trying to simulate a design for an Spartan3-200, on Webpack 7.1i SP4 with ModelSim XE III/Starter 6.0a. The design simulates perfectly for a functional simulation, running own .do file on ModelSim. However, if I run the same .do file on the simulation model generated with the "Generate Post-Synthesis Simulation Model" process, I get the following messages (several times): # ** Error: (vsim-3601) Iteration limit reached at time 2350 ns. # ** Note: (vsim-3602) Delays were truncated during elaboration of the design. And the design does not simulate further than 2350 ns (clock cycle is 100 ns, on .do file) The same happens if I run the same .do file on the simulation model generated with the "Generate Post-Place & Route Simulation Model" process. What do those messages mean, and how can I solve this issue? For your help, thank you very much. Regards, --- Jaime Andres Aranguren Cardona jaac@sanjaac.com SanJaaC Electronics Soluciones en DSP www.sanjaac.comArticle: 94054
On Thu, 5 Jan 2006 00:43:31 -0500, "Jaime Andres Aranguren Cardona" <jaac@nospam.sanjaac.com> wrote: ># ** Error: (vsim-3601) Iteration limit reached at time 2350 ns. ># ** Note: (vsim-3602) Delays were truncated during elaboration of the >design. I am not a modelsim user but that message means that the event simulator doesn't converge, ie you have combinational loop somewhere which is generating arbitraryly large number of events at that simulation time so the simulation point doesn't progress and the simulator gives up at some point. This can happen when the input of an inverter is connected to its output etc., also with combinational latches. You need to figure out which device(s) is causing the loop and some how prevent it going into the loop. You may have to force some nets to reset the combinational latches or pass through a state where the input is X etc. Although there is a very small likelyhood that your iteration limit is too low and increaing it may help, I doubt that's your problem. HTH.Article: 94055
"gja" <gja@hotmail.com> schrieb im Newsbeitrag news:nq%uf.3818$DY3.3339@fe09.lga... > I'm looking for some suggestions as to what else to look at to fix this > problem: > > Using a Virtex II xc2v40 and xcf02s prom connected in master serial mode. > JTAG is also implemented. We've built around 50 of these boards without > this problem so I believe it's just this particular board. It > intermittently doesn't configure on power up. > > A power chip holds INIT_B low until 3.3v is 3v to delay configuration, not > really needed since power ramps up in around 5ms. When it fails, I see on > a scope that INIT_B never goes high after power is up and PROG is high. > PROG is pulled up to 3.3v thru 4.75k. When it works, INIT_B goes high > within 5ms of PROG going high. > > As a test, I connected PROG to GND with a wire and then powered up the > board. After say 5 secs, I disconnected GND, and sometimes INIT_B would > go high as expected, But sometimes it would remain low. If it went high, I > could pulse PROG low and INIT_B would work as expected everytime. > > When the fpga is in its nonworking state, it doesn't respond on the JTAG > port either. > > I lifted the prom pin and the power chip connected to INIT_B to verify > that when it fails, it's the fpga that is holding INIT_B low and not the > other chips. > > Any ideas on what else to look at? > if INIT_B does not go high there isnt much too look at - init output and its corresponding bit in IR capture readback and in configuration status register does indicate "internal housecleaning complete" if it remains Low then FPGA is basic internal failure mode only power supply and PROG_B can possible prevent the INIT_B from going low (or malfunctionining FPGA) if JTAG works at all you can check the init_b bit in IR capture, if JTAG doesnt work at all, then I assume bad FPGA or bad power supply -- Antti Lukats http://www.xilant.comArticle: 94056
>> 0,1,2,3,4,5,6,7... ? >> well it doesnt, it counts >> 0,5,2,3,4,1,6,7... ! >please dis-regard my prev. posting, it was incorrectly sent as >reply and the issue with the counter seems to be solved it really >is a damaged internal FPGA structure, by floorplanning the >counter into different locations I can produce various >types of wrong counting sequences. So issue solved I think. Can anybody figure out what sort of damage it would take for a counter to flip between those patterns? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 94057
>If I had been able to use MatLab, MatchCad, or Mathematica when I was in >school, I would be even further along than I am today. With these math >tools avaialble, get one, and master it. GNU Octave is free. http://www.octave.org/ >The idea of hand cranking any of the DSP math is so paiful (I did it!) >that now I can not even imagine doing it by hand today. > >You learn the concepts, and the theory faster if you have something that >allows you to get through the math bits. > >As a good friend of mine once said "the faster I can make mistakes, the >fatser I can learn." With a good math program, you can make mistakes >faster than ever. Some of us learn more/better when we make our mistakes in the low level details. Maybe only the first few mistakes while getting off the ground. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 94058
Hi Jaime, Just type in verror 3601 to get some more info : vsim Message # 3601: The simulator iterates at a given simulation time in zero delay until there is no more activity at that time. In order for it to not hang if there is a zero-delay oscillation, it limits the number of iterations to a default of 5000. If you reach this limit, the simulation will stop with an error. If you receive this error you can increase the iteration limit, (via "set IterationLimit <newvalue>") and then try single stepping to attempt to determine which instances in the design may be oscillating. [DOC: ModelSim User's Manual - Detecting infinite zero-delay loops] Hans www.ht-lab.com "Jaime Andres Aranguren Cardona" <jaac@nospam.sanjaac.com> wrote in message news:43bcb076$0$28926$6d36acad@roc.nntpserver.com... > Good day, > > I am trying to simulate a design for an Spartan3-200, on Webpack 7.1i SP4 > with ModelSim XE III/Starter 6.0a. > > The design simulates perfectly for a functional simulation, running own > .do file on ModelSim. > > However, if I run the same .do file on the simulation model generated with > the "Generate Post-Synthesis Simulation Model" process, I get the > following messages (several times): > > # ** Error: (vsim-3601) Iteration limit reached at time 2350 ns. > # ** Note: (vsim-3602) Delays were truncated during elaboration of the > design. > > And the design does not simulate further than 2350 ns (clock cycle is 100 > ns, on .do file) > > The same happens if I run the same .do file on the simulation model > generated with the "Generate Post-Place & Route Simulation Model" process. > > What do those messages mean, and how can I solve this issue? > > For your help, thank you very much. > > Regards, > > --- > Jaime Andres Aranguren Cardona > jaac@sanjaac.com > SanJaaC Electronics > Soluciones en DSP > www.sanjaac.com > >Article: 94059
Thanks Richard, I knew I'd get a definitive answer here as quick as I could anywhere else :) Robin BruceArticle: 94060
Thank you Ray, that was a good summary! Seems like we have our work cut out for us if we want the full potential, and I beleive I have to re-think the usefulness of my original intent of a quick "ball-park figure"... /LarsArticle: 94061
Hi Peter, that wasn't meant to be unpolite... But why wouldn't you send a bunch of them to AVNET EU so that they could distribute them to their customers? or shall we all squeak? ;-) RalphArticle: 94062
"Hal Murray" <hmurray@suespammers.org> schrieb im Newsbeitrag news:wr6dnZSzzJBYTCHenZ2dnUVZ_tKdnZ2d@megapath.net... >>> 0,1,2,3,4,5,6,7... ? > >>> well it doesnt, it counts > >>> 0,5,2,3,4,1,6,7... ! > >>please dis-regard my prev. posting, it was incorrectly sent as >>reply and the issue with the counter seems to be solved it really >>is a damaged internal FPGA structure, by floorplanning the >>counter into different locations I can produce various >>types of wrong counting sequences. So issue solved I think. > > Can anybody figure out what sort of damage it would take for > a counter to flip between those patterns? > Hi Hal, I found it interesting/strange too - the big problem was that several simple designs worked with no observable misbhevior so I assumed the FPGA healty. after seeing this weird counting, I tried to locate undamaged are on the FPGA by floorplanning the counter into different areas, but that was only giving different types of wrong counting, like 0,7,0,7,... I did not manage to find working area for the counter, so I re-implemented the counter with fault-tolerance in mind and after that first attempt instantly worked 100% ok, without the need to find a undamaged area I will keep this half-damaged FPGA for special testing, if I can develop automated testing that shows what resources are damaged that may be of some interest :) -- Antti Lukats http://www.xilant.comArticle: 94063
Hal Murray wrote: >>>0,1,2,3,4,5,6,7... ? > > >>>well it doesnt, it counts > > >>>0,5,2,3,4,1,6,7... ! > > >>please dis-regard my prev. posting, it was incorrectly sent as >>reply and the issue with the counter seems to be solved it really >>is a damaged internal FPGA structure, by floorplanning the >>counter into different locations I can produce various >>types of wrong counting sequences. So issue solved I think. > > > Can anybody figure out what sort of damage it would take for > a counter to flip between those patterns? This must be the holidays - too many idle brain cells... :) Strangest chip-damage fault I saw, was a processor PIN that actually flipped: so TRUE was 0, and False was 1. Must have somehow shorted IP-OP on a pre-inverter, much more common is the short-to-rail failure. -jgArticle: 94064
On Tue, 3 Jan 2006 12:36:41 +0100, "Antti Lukats" <antti@openchip.org> wrote: [...] >> 0,1,2,3,4,5,6,7... ? >> >> well it doesnt, it counts >> >> 0,5,2,3,4,1,6,7... ! >> >> I have verified this behaviour multiply times and its still >> counting this weird sequence where 1 and 5 are changed. > >please dis-regard my prev. posting, it was incorrectly sent as >reply and the issue with the counter seems to be solved it really >is a damaged internal FPGA structure, by floorplanning the >counter into different locations I can produce various >types of wrong counting sequences. So issue solved I think. Antti, you're too experienced to make this mistake I think... but I remember, many years ago when I didn't understand these things, that I got this sort of behaviour because I had used a general-purpose net to distribute a clock, instead of using one of the dedicated clock nets. So I got lots of hold time violations, strongly dependent on placement, and the counter failed to count correctly at any clock frequency. In my case it was a count to 24 that mysteriously stopped at 14. If you get more than one different sort of bad count, it seems to me that this is the most likely problem. cheers -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@MYCOMPANY.com Fax: +44 (0)1425 471573 Web: http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 94065
Hi, First of all, thanks for your reply. Certainly, I've got some stuff to deal with, as can be read from the warnings that I get. I am posting them here, asking for your kind guide on what should I apparently correct, what errors are inferred from these warnings. In advance, please apologize for the long post. >From the Synthesis report, I get the following warnings / infos: WARNING:Xst:737 - Found 1-bit latch for signal <wr>. WARNING:Xst:737 - Found 19-bit latch for signal <addressint>. WARNING:Xst:737 - Found 1-bit latch for signal <rd>. WARNING:Xst:737 - Found 1-bit latch for signal <status>. WARNING:Xst:737 - Found 1-bit latch for signal <cs>. WARNING:Xst:737 - Found 19-bit latch for signal <diffcount>. WARNING:Xst:737 - Found 1-bit latch for signal <direction>. -- trimmed INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. -- trimmed Found area constraint ratio of 100 (+ 5) on block memtest, actual ratio is 3. FlipFlop presentState_FFd1 has been replicated 3 time(s) FlipFlop presentState_FFd3 has been replicated 1 time(s) FlipFlop presentState_FFd4 has been replicated 1 time(s) -- trimmed -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 9 | _n0029(_n00291:O) | NONE(*)(rd) | 3 | _n0030(_n00301:O) | NONE(*)(addressint_12) | 19 | _n0031(_n00311:O) | NONE(*)(status) | 1 | _n0032(_n00321:O) | NONE(*)(diffcount_2) | 19 | _n0033(_n00331:O) | NONE(*)(direction) | 1 | -----------------------------------+------------------------+-------+ (*) These 5 clock signal(s) are generated by combinatorial logic, and XST is not able to identify which are the primary clock signals. Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. -- Also, from the Map Report, I get the folowing warnings: WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0029 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0030 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0032 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0033 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net _n0031 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. -- From the Place and Route, I get this warning / information WARNING:Route - CLK Net:_n0029 may have excessive skew because 3 CLK pins failed to route using a CLK template. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX3| No | 8 | 0.001 | 1.011 | +---------------------+--------------+------+------+------------+-------------+ | _n0029 | Local| | 3 | 0.633 | 1.670 | +---------------------+--------------+------+------+------------+-------------+ | _n0030 | Local| | 10 | 0.046 | 2.518 | +---------------------+--------------+------+------+------------+-------------+ | _n0032 | Local| | 10 | 0.087 | 1.655 | +---------------------+--------------+------+------+------------+-------------+ | _n0033 | Local| | 1 | 0.000 | 0.500 | +---------------------+--------------+------+------+------------+-------------+ | _n0031 | Local| | 1 | 0.000 | 1.599 | +---------------------+--------------+------+------+------------+-------------+ "mk" <kal*@dspia.*comdelete> wrote in message news:j9fpr15bdhuk6ij7654e0mm2g1td85t456@4ax.com... > On Thu, 5 Jan 2006 00:43:31 -0500, "Jaime Andres Aranguren Cardona" > <jaac@nospam.sanjaac.com> wrote: > >># ** Error: (vsim-3601) Iteration limit reached at time 2350 ns. >># ** Note: (vsim-3602) Delays were truncated during elaboration of the >>design. > > I am not a modelsim user but that message means that the event > simulator doesn't converge, ie you have combinational loop somewhere > which is generating arbitraryly large number of events at that > simulation time so the simulation point doesn't progress and the > simulator gives up at some point. This can happen when the input of an > inverter is connected to its output etc., also with combinational > latches. You need to figure out which device(s) is causing the loop > and some how prevent it going into the loop. You may have to force > some nets to reset the combinational latches or pass through a state > where the input is X etc. Although there is a very small likelyhood > that your iteration limit is too low and increaing it may help, I > doubt that's your problem. > > HTH.Article: 94066
Dear all:
When I generate an EDIF from Handel-C in DK3.1, I want simulate it with
Xilinx ISE waveform analyzer, but always the output signals appear with
the "U" (undefined) value (I test it creating a schematic symbol from
EDIF with the edif2sym tool). This problem also exists using modelsim
waveform analyzer.
With older Xilinx Foundation 4 this problem doesn't appear (in this
version, the schematic symbol is generated from EDIF as menu option in
the schematic tools).
For example, I've used the following code for testing purposes:
//Test
/*========================================*/
/**** Xilinx Virtex V2000E-6/7/8-BG560 ****/
/*========================================*/
set clock = external_divide 3;
unsigned int 1 x_init;
interface bus_in (unsigned int 1) init()
with {data={"A27"}};
unsigned int 5 x_result;
interface bus_out () result (unsigned int 5 OutPort=x_result)
with {data={"B25","C28","C30","D30","A3"}};
unsigned int 1 x_end;
interface bus_out () end (unsigned int 1 OutPort=x_end)
with {data={"D9"}};
/*========================================*/
void Algorithm(void) {
unsigned int 5 cont;
cont = 0;
while(cont<15) {
cont++;
}
x_result=cont;
}
/*========================================*/
void main(void)
{
x_end=0;
while(x_end==0)
{
x_init=init.in;
if(x_init==0) {
x_result=28;
}
else {
Algorithm();
x_end=1;
}
}
}
/*========================================*/
Does anybody have the same problem? Can anybody help me?
Thanks a lot.
Best regards,
--
Juan A.
University of Extremadura
Spain
Article: 94067"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> schrieb im Newsbeitrag news:cl1qr19qv23meaarh5elttfba6o81bpin0@4ax.com... > On Tue, 3 Jan 2006 12:36:41 +0100, "Antti Lukats" > <antti@openchip.org> wrote: > > [...] >>> 0,1,2,3,4,5,6,7... ? >>> >>> well it doesnt, it counts >>> >>> 0,5,2,3,4,1,6,7... ! >>> >>> I have verified this behaviour multiply times and its still >>> counting this weird sequence where 1 and 5 are changed. >> >>please dis-regard my prev. posting, it was incorrectly sent as >>reply and the issue with the counter seems to be solved it really >>is a damaged internal FPGA structure, by floorplanning the >>counter into different locations I can produce various >>types of wrong counting sequences. So issue solved I think. > > Antti, you're too experienced to make this mistake I think... > but I remember, many years ago when I didn't understand > these things, that I got this sort of behaviour because I had > used a general-purpose net to distribute a clock, instead of > using one of the dedicated clock nets. So I got lots of hold > time violations, strongly dependent on placement, and the > counter failed to count correctly at any clock frequency. > In my case it was a count to 24 that mysteriously stopped > at 14. > > If you get more than one different sort of bad count, it > seems to me that this is the most likely problem. > > cheers > -- > Jonathan Bromley, Consultant Hi Jonathan, you are right I am way to experienced ! the malfuncitoning counter (lowest 3 bits tested) is here Process_DRCK1 : process (DRCK1) is begin if (SHIFT='0') or (SEL1='0') then ADDR <= "0000000000000000000000000"; else if DRCK1'event and DRCK1 = '0' then ADDR <= ADDR + "0000000000000000000000001"; end if; end if; end process Process_DRCK1; Anything wrong with it? XST does synthesize a carry chain RPM out of it. the above counter (its low 3 bits) did count differently wrong depending on the foorplanning constrained are. each malfunctioning bitstream worked wrong the same way if loaded into FPGA after a malfunctioning bitstream was loaded the next load of another working design resulted FPGA to work with partial errors as well. this FPGA is never seen by XMD when trying to debug, and ChipScope cores are seen by ChipScope only once in a blue mooon. so I am 100% sure that I have a FPGA with internal faulty fabric - a StrataFlash on the same board was damaged in scuh way that device ID query works but CFI QRY returns garbage, so I dont actually wonder the FPGA is damaged as well, the only thing that confused me is that 2 old design for that FPGA remained functional after the FPGA got damaged by power surge. As of my expertize - after seeing the FPGA being damaged I did think and implemented as fault tolerant as possible counter, and that counter does work properly also in the damaged FPGA (it does not use any LUT at all...) Or, do you think it could be that counter RTL code that makes the loaded next good known working bitstream to malfuntion ?? -- Antti Lukats http://www.xilant.comArticle: 94068
On Thu, 5 Jan 2006 13:10:38 +0100, "Antti Lukats" <antti@openchip.org> wrote: >> Antti, you're too experienced to make this mistake I think... [...] >you are right I am way to experienced ! OK! >so I am 100% sure that I have a FPGA with internal faulty fabric - a >StrataFlash on the same board was damaged Hmmm. It would appear that your FPGA board was too close to the lightning rod that you were using for your Give-My-Creature-Life project :-) Very bizarre. cheers -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@MYCOMPANY.com Fax: +44 (0)1425 471573 Web: http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 94069
Hi, I'm trying to implement a second order costas loop for carrier recovery in AM DSB-SC and BPSK. I 've done simulations for AM DSB-SC in MATLAB, but I couldn't implement my design in Xilinx with VHDL. After designing this part for the transmitter, I will design an adaptive equalizer, but I still have serious problems with carrier recovery and have no so much time. I also tried to use System Generator. System Generator has a demo about costas loop, but I couldn't figure it out what kind of logic that it uses. It is a little bit different than typical costas loop model. I would be very greatful if you can share VHDL codes related with carrier recovery or costas loop esp. for AM DSB-SC and BPSK if you have or at least someone please tell me the logic of the costas loop model in system generator demo part. Thanks for your help! ~EmrahArticle: 94070
It's an interesting question though. I can't remember what exactly happens when I installed my ISE. Does the SW get a validation from the Web or something or would a fresh installation simply work again on another machine? If so it's a bit weak of Xilinx since they charge so much for ISE Foundation. Rog. "Monica" <monica_dsz@yahoo.com> wrote in message news:1136397969.354645.215170@g44g2000cwa.googlegroups.com... > Hallo gerald, > > This is not recommended.You may use ISE webpack freely as long as you > want.You may download it from > http://www.xilinx.com/ise/logic_design_prod/webpack.htm > > Cheers, > Monica >Article: 94071
You can use a counter to sub divide the frequency, and output the counter output to the bufg buffer, and it could behave just like a clock.Article: 94072
Hi all, What should I read to find out about timing constraints in detail? not just syntax but some theory. and how are the constrains interpreted? is the logic routed according to timing constraints? What if I use more than 90% of the available resources? Also I am using an async fifo in my design. Is it necessary to use timing constraints for this? Thanks in advance SubhasriArticle: 94073
Now I want to design a RISC cpu for study the cpu architecture, and I am puzzled about how to start? Whether should I start with a RISC 16 bit cpu, including just serveral instructions like add, substract, multiply and divide? And I wonder whether I should introduce the pipeline and superscalar into the architecture?Article: 94074
Hi all, i am facing a problem with Xilinx DCM in DFS (not in DLL mode, in which you need to provide a feedback clock for phase alignmen). So my DCM is working in without feedback (internal as well as external) mode. I am trying to generate a 32Mhz clock from a 16Mhz input clock. Most of the time it works fine but sometimes after giving a reset to FPGA or reprogramming the FPGA the DCM is not able to multiply the clock to give a 32Mhz clock and gives the same input 16Mhz clock as the output. But according to Xilinx DCM datasheet, in DFS mode we should be able to multiply or divide clocks with frequency > 1 Mhz. So if anyone has faced any such problem or if there is any synthesis attribute which I need to set etc then please guide me. Thanks in advance Debashish
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