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Are you giving the state machine a clean synchronous reset? Are all inputs to the state machine properly synchronized? You might add logic on a test pin to indicate if the state machine enters an illegal state such as zero hot or 2-hot. -JeffArticle: 92951
Synthesise the code and send a netlist (after synthesis or P&R), use the -nodebug switch in Modelsim (receiver must use Modelsim), use an obfuscator (not that secure), translate the model into C/C++/SystemC and send the compiled code (receiver needs to use PLI/FLI/DPI etc to interface to the model), use a professional HDL->SystemC translator like Carbon (not low cost but very powerful) or set up an NDA and just send the RTL :-) Hans www.ht-lab.com "fad" <fahad.arif@gmail.com> wrote in message news:1134156402.394894.138500@g43g2000cwa.googlegroups.com... > Hi, > I know tha some EDA tools provide encryption feature to protect > confidentiality of the HDL source code but how do we do this in > ModelSim/FPGA Adv or in Xilinx ISE? > So that I can provide an encrypted source code to someone and yet it > works as real RTL desription. > Please suggest. > Thanks, > Fahad >Article: 92952
Designer is easy to use, not that many features, can easily be scripted up (designer.exe "script: xxxx.tcl"), supports SDC constraints, P&R and FlashPro download very slow (and I mean slow!), good support (at least in my case),impossible to install under Linux (at least I failed), nice parts like the A3PE3000-PQ208 not available for some time to come (AFAIK). I would go for just Designer, synthesis either Precision or Synplify, and I would advice to get a JTAG debugger like Dialite or FS2. The days of C-Module only FPGA's like the A1010 and tools like ACTMap and Asyl+ are long gone :-) Hans www.ht-lab.com "jweissberg" <weissber@NOSPAMusc.edu> wrote in message news:dnahm5$i7v$1@gist.usc.edu... > I'm considering these parts for a new design, and the low static power and > small footprint, instant-on features seem nice. In terms of performance > or density, this app is not demanding at all, but we want more headroom > than a CPLD gives. > > I haven't used Actel parts or SW for over 10 years - how have > design/supply/support experiences been on ProAsic3E?? How decent are the > Actel tools for HDL based designs? I'm very familiar with the Xilinx IDE. > I'd be in the 30K device to start with. > > If you want to keep your #$%! answers more private, you can mail me > directly. I can sum up for the group later. > > Thanks in advance! >Article: 92953
Hi Abbs, Do a search on the web for Transaction Level Modelling (TLM), Constraint Random (CR) stimulus generations, assertions (like PSL/SVA/OVL) and functional and formal verification. Hans www.ht-lab.com "Abbs" <abrar_ahmed_313@yahoo.co.in> wrote in message news:1134038928.859327.248170@o13g2000cwo.googlegroups.com... > > Thomas Stanka wrote: >> > code in TESTBENCHES. >> > If there are many other ways of testing and validation which i'am >> > unaware of PLEASE let me know. >> >> Code review, testbenches, static timing analyses and formal >> verification are the major verification tasks. Don't know which of them >> makes sense for your designs and team. >> >> > One last doubt, in verification, do we even work on STATIC TIME >> > ANALYSIS and SYNTHESIS. or this is done by the designer itself.. >> >> How could we know if you don't? STA is usually perfomed after layout, >> has your designer feedback from layout? Do you have to verify after >> layout or are you only responsible for functional verification until >> synthesis? >> >> bye Thomas > > hi > i was told to study corner case testing, different testing scenarios > and BFM models. i have to test the design before the layout. before > after synthesis not to sure... i wana get good knowledge regarding > verification. can you help me with links that gives a brief idea > related to testing... > thanks > Bye >Article: 92954
"Antti Lukats" <antti@openchip.org> writes: > check out development board package deals, sometimes it makes sense to buy > some dev board with bundled ISE (or EDK) as the board price will then be > haevily reduced compared to board+ISE price if purchased separatly. In fact, sometimes you can find deals where ISE w/ a board costs less than just ISE. If you need BaseX, just wait for the imminent release of WebPack 8.1i, which apparently will do everything BaseX did. And if you need the full ISE, you can buy BaseX 7.1i now, and get an upgrade to full ISE 8.1i, for a combined total price less than the price of the full ISE alone. But if you want to do that, do it quickly before they stop offering BaseX 7.1i.Article: 92955
The IPcore is very small and actually not S3e only, but it was written because of Spartan3E, namly because S3e added the SPI loading capability and acces to all the dual purpose pins from fabric so the spi flash can be accessed after config. So thats why I wanted to have the JTAG-to-SPI bridge, it is available here http://xilant.com/component/option,com_remository/Itemid,53/func,select/id,4/ included are sample toplevels and some short description and minimal testbench the ipcore has been tested in Virtex4 and now thanks to www.cesys.de also with Spartan-3E, but it should actually work also with cyclone and latticeEC the core has been tested using secial custom Application that talks to the SPI over the FPGA jtag chain, but the core also allows any SVF or JAM player capable tool to be used to program the spi flash, for that purpose we have developed a very simple language standard to write down SPI programming data that embedds the programming algorithm, this in turn can be either directly executed to some JTAG cable hardware or converted to JAM/stapl or SVF, again example is in the ipcore archive. the generated SVF has been tested with real spi flash device using impact 7.1 as SVF playback engine. Antti who is pretty happy to see something working in S3e silicon !Article: 92956
FX12 parts are available. If your distributor does not stock them, it might be because he does not want to stock ES-type parts that he cannot return. Just ask for "FX12 CES" or ask for "FX12 Production SCD0965". The latter is the same die, but it has gone through production qualification. There are some minor errata that you can get from your distributor. Peter Alfke, Xilinx ApplicationsArticle: 92957
Antti Lukats wrote: > The IPcore is very small and actually not S3e only, but it was written > because of Spartan3E, namly because S3e added the SPI loading capability and > acces to all the dual purpose pins from fabric so the spi flash can be > accessed after config. So thats why I wanted to have the JTAG-to-SPI bridge, > it is available here Why is a core required? Can't you just access the SPI pins directly from JTAG boundary scan? Or is this easier? Alan NishiokaArticle: 92958
"Alan Nishioka" <alan@nishioka.com> schrieb im Newsbeitrag news:1134171563.493657.248360@g49g2000cwa.googlegroups.com... > Antti Lukats wrote: >> The IPcore is very small and actually not S3e only, but it was written >> because of Spartan3E, namly because S3e added the SPI loading capability >> and >> acces to all the dual purpose pins from fabric so the spi flash can be >> accessed after config. So thats why I wanted to have the JTAG-to-SPI >> bridge, >> it is available here > > Why is a core required? Can't you just access the SPI pins directly > from JTAG boundary scan? Or is this easier? > > Alan Nishioka > sure it can be done via boundary scan, but if you need to reflash and 64mbit serial flash you can figure out how long it takes over boundary scan! sending 111110aaaaaaaa1111 to user jtag register will be translated to single byte SPI transaction and CS pulse so there is only 1 JTAG clock per SPI byte overhead during SPI access AnttiArticle: 92959
Thanks for the advice. Looking on the web site though, it looks like I'm already too late. There's no mention of BaseX anymore. They've gone down to just 2 versions, FREE and EXPENSIVE. Rog. "Eric Smith" <eric@brouhaha.com> wrote in message news:qhu0dhual2.fsf@ruckus.brouhaha.com... > "Antti Lukats" <antti@openchip.org> writes: >> check out development board package deals, sometimes it makes sense to >> buy >> some dev board with bundled ISE (or EDK) as the board price will then be >> haevily reduced compared to board+ISE price if purchased separatly. > > In fact, sometimes you can find deals where ISE w/ a board costs less > than just ISE. > > If you need BaseX, just wait for the imminent release of WebPack 8.1i, > which apparently will do everything BaseX did. > > And if you need the full ISE, you can buy BaseX 7.1i now, and get an > upgrade > to full ISE 8.1i, for a combined total price less than the price of the > full ISE alone. But if you want to do that, do it quickly before they > stop offering BaseX 7.1i. > > >Article: 92960
> And if you need the full ISE, you can buy BaseX 7.1i now, and get an upgrade > to full ISE 8.1i, for a combined total price less than the price of the > full ISE alone. But if you want to do that, do it quickly before they > stop offering BaseX 7.1i. Is that right? I recently purchased the ML403 dev board for $900 USD, which includes the Virtex4 FX12 dev board + BaseX + EDK...I was pleased with the purchase, but when I heard that they were stopping BaseX, I wasn't sure where that left me (I was guessing that the 8.1 WebPack was all that I would have access to wen 8.1 comes out). Is this true? I assue you're stating that I would have to pay the difference between BaseX, and the full ISE if I want to get to ISE 8.1 instead of just the WebPack. Thanks for any clarification! JohnArticle: 92961
>>A thought cross my mind ... >> >>I've been working much on Virtex4 lately and getting fast (~300-350 Mhz) >>logic for the datapath isn't really hard. But making the control stuff >>go that fast is a whole lot more tricky, just a 10 bits comparator >>becomes "a lot" at that speed ... and some control signals have high >>fanout and that brings the net delay in the 1 - 1.5 ns range which is >>half of the period ... >> >>So what if every now and then in the FPGA fabric, there was a small >>cluster of like 1 CLB with "Super LUTs" that would have a whole lot >>faster logic (but no special func like SRL and distributed ram) and >>"bigger" drivers to charge/dischare the net faster to propagate the >>controls. >> I think if you look at the logic that is not making speed, it is probably using the carry chain (comparators over 7 bits do, for example). General logic is quite fast in V4. The carry chain is very slow comparatively, which has been a beef of mine. Simply speeding up the carry chain so that reasonable sized adders (16-24 bits) can run at speeds similar to the block rams and DSP slices would make all the difference. (yes Austin, I know the "simply" isn't all that easy). You already do have "super LUTs" in the Virtex4. They are called RAMB16, and can be used for logic functions with up to 14 inputs, at clock rates of 400 MHz in a -10 part. The other option you do have is to optimize your control logic to reduce the reliance on difficult structures such as carry. For example, if your control is using a compare to decode a count, consider instead using a down counter so that the terminal count is the most significant bit. Also consider other counter architectures, such as linear feedback shift register counters to eliminate wide logic functions. >Article: 92962
"Roger" <enquiries@rwconcepts.co.uk> writes: > Thanks for the advice. Looking on the web site though, it looks like I'm > already too late. There's no mention of BaseX anymore. They've gone down to > just 2 versions, FREE and EXPENSIVE. Looks like they still have the PowerPC & MicroBlaze Development Kit for $895. That includes BaseX (regularly $695), an ML403 Virtex-4 FX development board (regularly $495), and either a Perallel Cable 4 (regularly $95) or Platform USB Cable (regularly $149). So if you buy that, you should be able to get the ISE 8.1i full upgrade for an additional $1495. Total price of $2190, while the full ISE is normally $2495 and doesn't include a board or programming cable. Note that I'm just a customer and don't have any inside information, so you'll have to research this yourself and decide if this plan will really work. I don't offer any guarantee. For instance, I don't have any way to know whether ordering the kit today will really get you BaseX (rather than Webpack 8.1i), and I don't know with certainty that it will qualify you for the reported $1495 upgrade price. Also check the distributor sites (e.g., Avnet and Nu Horizons). They often have attractively priced bundles including BaseX or full ISE. EricArticle: 92963
Ray Andraka wrote:
>>> A thought cross my mind ...
>>>
>>> I've been working much on Virtex4 lately and getting fast (~300-350 Mhz)
>>> logic for the datapath isn't really hard. But making the control stuff
>>> go that fast is a whole lot more tricky, just a 10 bits comparator
>>> becomes "a lot" at that speed ... and some control signals have high
>>> fanout and that brings the net delay in the 1 - 1.5 ns range which is
>>> half of the period ...
>>>
>>> So what if every now and then in the FPGA fabric, there was a small
>>> cluster of like 1 CLB with "Super LUTs" that would have a whole lot
>>> faster logic (but no special func like SRL and distributed ram) and
>>> "bigger" drivers to charge/dischare the net faster to propagate the
>>> controls.
>>>
> You already do have "super LUTs" in the Virtex4. They are called
> RAMB16, and can be used for logic functions with up to 14 inputs, at
> clock rates of 400 MHz in a -10 part.
... Well 400 MHz if you register both side and don't have too many logic
before and after.
A block ram without output reg is like 2.1 ns clock to out and around
0.5 ns net delay after. If you have output reg then it's 0.9 ns clock to
out. But sometimes you just can't have a 1 or 2 clock cycle latency ...
And here I was more referring to the drive strenght than the number of
input nets. For example if you have to generate a clock ena
combinatorially (just a single LUT level but still) and it controls like
50 FFs, the net take like 1.5 ns propagation ... half of my period ...
> The other option you do have is to optimize your control logic to reduce
> the reliance on difficult structures such as carry. For example, if
> your control is using a compare to decode a count, consider instead
> using a down counter so that the terminal count is the most significant
> bit. Also consider other counter architectures, such as linear feedback
> shift register counters to eliminate wide logic functions.
Well, yes optimizing control is good but sometimes very hard ... I've
basically spent the last few days just doing that to finally meet
timing. My comparators are not for counters but to detect a "empty"
condition in a FIFO like block. ('FIFO like' because it's quite more
complicated than a simple FIFO).
Sylvain
Article: 92964john.orlando@gmail.com writes: > Is that right? I recently purchased the ML403 dev board for $900 USD, > which includes the Virtex4 FX12 dev board + BaseX + EDK...I was pleased > with the purchase, but when I heard that they were stopping BaseX, I > wasn't sure where that left me (I was guessing that the 8.1 WebPack was > all that I would have access to wen 8.1 comes out). Is this true? I > assue you're stating that I would have to pay the difference between > BaseX, and the full ISE if I want to get to ISE 8.1 instead of just the > WebPack. ISE 8.1i hasn't officially been announced, so I don't know for sure. But a news report says that there will be a BaseX-7.1i-to-full upgrade available for $1495, with part number DX-ISE-BX2FND-71I: http://www.esp2000.ro/articol.php?id_ar=2850 I'm guessing that 8.1i will be officially announced next week.Article: 92965
Antti Lukats wrote: > sure it can be done via boundary scan, but if you need to reflash and 64mbit > serial flash you can figure out how long it takes over boundary scan! That's a good point. I plan to use an SPI flash with a Spartan 3e, and I haven't quite decided how to handle the initial programming and in system programming. Thank you for the core. Alan NishiokaArticle: 92966
Agreed about the BRAM speed. You pretty much have to use the DO_Reg for a 400 MHz design in a -10 part. There shouldn't be any logic between the previous register and inputs to the BRAM, and the outputs can go through a single level of logic, but placement isn't critical. As I said, the real stumbling block for fast fabric stuff is the carry chain. If you are using an SX part, you can use the DSP48's to get faster arithmetic, but at a considerable cost. I stand by my contention that if the carry chains were faster (more specifically, the time to get on and off them), you'd probably find it a lot easier to make timing in your design.Article: 92967
Thanks for the reply. Yeah I am giving the FSM a clean sycnhronous reset and the inputs are all sychronous. I'll test for the FSM going into illegal state. Sudhir Jeff Cunningham wrote: > Are you giving the state machine a clean synchronous reset? Are all > inputs to the state machine properly synchronized? You might add logic > on a test pin to indicate if the state machine enters an illegal state > such as zero hot or 2-hot. > > -JeffArticle: 92968
Hi All, I just got myself an evaluation license for ChipScope Pro 6.2. I used the Core Inserter tool to insert the ICON and ILA cores into my design. The first time I used the Pro Analyser to load the configuration file it all went ok. However, I tried to load the same configuration file the next day and now Analyser gives me the following messsage: COMMAND: configure 1 "C:\my_design_cs.bit" 0 INFO: Found 0 Core Units in the JTAG device Chain The configuration file hasn't been changed. I have tried multiple times but no luck. Has anybody else had the same problem? Is this some sort of limitation put on ChipScope evaluation version? Thanks in advance SudhirArticle: 92969
"Carsten" <xnews1@luna.kyed.com> wrote in message news:lehjp19rgq012omivffaerbdr58ofjfblp@4ax.com... > > >>> I must develop a system with lots of I/O, about 180-190. My chief don't >>> want use BGA (fg320), but pq208... >>> so I thought to connect 2 fpga pq208. >> >>> I think it'is bad... but there are other chances? >> >>> Otherwise does exist a BGA adapter for fg320 package to change it into a >>> pq320? >> >>Why not use a FPGA module like the Zefant Modules? (www.zefant.de)? > > I have one of those Zefant S3-1000 boards + Baseboard , it's an > excellent combination. > > There is even 47 pcs. 5v tolerant CPLD pins in addition to the FPGA > pins. > > > > Carsten It seems good. I'll look for it. Many Thanks MarcoArticle: 92970
Marco wrote: > "Antti Lukats" <antti@openchip.org> wrote in message > news:dn6b3a$h6c$01$1@news.t-online.com... > > "Marco" <marcotoschi@nospam.it> schrieb im Newsbeitrag > > news:dn643r$hbo$1@nnrp.ngi.it... > >> Hallo, > >> does anyone has connected 2 FPGA? > >> Which kind of connection have used? > >> > >> Many Thanks > >> Marco > > > > FPGAs are often connected to each other by different means. > > > > your question can have no reasonable answers as you are the only person > > who know WHY you want to connect the FPGA, and the answer to that question > > is needed in order to decide HOW. It all depends why and what you are > > going to achive. > > > > Antti > > > > I must develop a system with lots of I/O, about 180-190. My chief don't want > use BGA (fg320), but pq208... > so I thought to connect 2 fpga pq208. > > I think it'is bad... but there are other chances? > > Otherwise does exist a BGA adapter for fg320 package to change it into a > pq320? > > Many Thanks > Marco What reasons do you have for not using BGAs? Any contract manufacturer (who will do the reflow soldering) will quote you **cheaper** on BGAs than quad packs, because they are easier to place. If you intend to sell a lot of them, the manufacturing price becomes important. As noted, if you need debug access to the pins, bring them out to a header that simply would not be fitted in production. As to prototyping with BGAs, there are people around who successfully put down BGAs with heat guns. Of course, you could use a plugin module, but then you expose yourself to the single greatest failure mechanism in all electronic equipment; mechanical connections. Cheers PeteSArticle: 92971
<Sudhir.Singh@email.com> schrieb im Newsbeitrag news:1134198567.431150.54350@f14g2000cwb.googlegroups.com... > Hi All, > I just got myself an evaluation license for ChipScope Pro 6.2. I used > the Core Inserter tool to insert the ICON and ILA cores into my design. > The first time I used the Pro Analyser to load the configuration file > it all went ok. However, I tried to load the same configuration file > the next day and now Analyser gives me the following messsage: > > COMMAND: configure 1 "C:\my_design_cs.bit" 0 > INFO: Found 0 Core Units in the JTAG device Chain > > The configuration file hasn't been changed. > I have tried multiple times but no luck. > Has anybody else had the same problem? Is this some sort of limitation > put on ChipScope evaluation version? > > Thanks in advance > Sudhir > no if the .bit file has the icon-ila in it and the analyzer starst it SHOULD display the core info. you most likely downloaded the wrong .bt file anttiArticle: 92972
Hi Peter, your reply made me think... I assumed that with gray-codes I am safe for mismatches from one count to the next, but not if the skew between the bits is more than one complete cycle, because than two bits might be wrong instead of only one. Now I made a gray-code-table on a sheet of paper and I found no situation where even this would be "catastrophic", because even then the count is only of by 1 or 2. (But I think, it can lead to wrong or "jumping" level-indication, even when the effects in the final application are most likely of no concern.) However, still a controlled delay between this register stages would give me a better feeling, as otherwise you never can know how long the delay of the fill-level-indicator is. Thanks, Thomas www.entner-electronics.com "Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:1134163688.314446.32550@o13g2000cwo.googlegroups.com... > Thomas, it only depends on your clock speed. Even the domain-crossing > registers have a whole clock tick to make up their mind. With > Gray-coded values, you already assume that you might unavoidably clock > in a mixture of the older and the newer value, but that does not matter > with Gray codes. It's either the old or the new value, never anything > else. > In other words, you don't have to be super-fast, as long as you meet > the required (synchronous) timing constraints, determined by the clock > rates. > > Peter Alfke, Xilinx Applications. >Article: 92973
Thanks for the hint, attribute maxdelay: string; attribute maxdelay of read_cnt_gray: signal is "4ns"; -- ensure that the clock-domain-crossing-pass is short was what I was looking for... Thomas www.entner-electronics.com "John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:1Dmmf.91$pX1.458@news-west.eli.net... > Something like NET *read_cnt_gray* MAXDELAY=3ns; perhaps? > > "Thomas Entner" <aon.912710880@aon.at> wrote in message > news:4399d29c$0$22256$91cee783@newsreader02.highway.telekom.at... >> >> Let's say, my critical FF's are: >> >> signal read_cnt_gray: unsigned(8 downto 0) := (others => -- in >> read-clock-domain >> and >> signal read_cnt_gray_pre_sync_wr: unsigned(8 downto 0) := (others => -- >> in write-clock-domain >> >> is there a way to add the timing-constraint in the VHDL-source (so that I >> can easily reuse the module for different designs, without always editing >> the ucf-file, etc.)? >> >> Thomas >> >> www.entner-electronics.com >>Article: 92974
As far as i know this happens often with the 6 series of chipscope. I havent experienced it with the 7 series. a couple of things which could help is create a new inserter core and then rerun the place and route or just open the chipscope once and then rerun the place and route and so on. Good luck!
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