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Melanie, In order to protect the sub-circuit models for our foundries (proprietary to the fabricators of our devices), we are not allowed to distribute the spice files in unencrypted form. We also do not want to tell the world how we designed all of our circuits (protect our own intellectual property). This practice is typical of the entire semiconductor industry. Instead, I suggest you use the IBIS models which are also available for use. Austin Melanie Nasic wrote: > Hi community, > > I got a problem you might be able to assist me in solving. I downloaded > several HSPICE models for the Xilinx Virtex-II Pro FPGAs from the Xilinx > homepage. They are stored in a format I don't know: *.inc. The included > readme-file says that all models are encrypted and must be used in Synopsys > HSPICE. All I got is a free PSPICE version running that supports file > formats like *.opj, *.dsn, *.sch, *.olb, *.lib, *.vhd, *.txt. I already > generated several schematics with PSPICE which I want to test in combination > with the Xilinx models. Unfortunately it looks like that is not possible at > all. Has anyone of you made similar experiences or has a hint how to solve > that incompatibility problem? Any help is highly appreciated. > > Regards, Melanie Nasic > >Article: 93201
A quick addition to the replies you've already received:- Always route out on the PCB the connections to the on-chip temperature diode. DXN, DXP. That way you know what's going on, directly on the die. I suspect that the DCM isn't your problem, I've run parts near the temperature specs and occasionally beyond (when the fan broke!) and didn't have any problems with DCMs. Mind you, I do take great care of my Vccaux supply. HTH, Syms.Article: 93202
> > And you only really have to elevate it above the cost of bribing one of > your employees :) > Jim, That's a key insight! I read Kevin Mitnick's books recently. Although the security breaches he writes about involved an amount of technical engineering knowledge, the social engineering undertaken was usually the key to unlock the first door! Cheers, Syms.Article: 93203
Ages ago, IC manufacturers used to specify a max ambient temperature (70 degr.C for commercial parts). We soon found out that this makes no sense for programmable parts. The FPGA manufacturer does not know what the user implements inside the chip (what clock frequency, what utilization) and how the chip is cooled. The only reasonable specification that we can guarantee is the max junction temperature. So we pioneered the Tj max 85 degr.C specification for all commercial parts. The user is the only person who then can evaluate whether the chip is operating within these guaranteed limits, and can modify the design or the cooling to bring it within specification. It would be nice if the FPGA-manufacturer could guarantee operation at a given ambient temperature, but that is inherently impossible, especially for parts where the user can program the logic and choose the clock speed. As a rule of thumb, no package without a heatsink has a thermal resistance (junction-to-ambient) below 10 degr.C per Watt. ( the very biggest get down to 8 degr./W), and a heatsink is needed when power exceeds a few watts. Peter Alfke, Xilinx ApplicationsArticle: 93204
Melanie Nasic wrote: > Hi community, > > I got a problem you might be able to assist me in solving. I downloaded > several HSPICE models for the Xilinx Virtex-II Pro FPGAs from the Xilinx > homepage. They are stored in a format I don't know: *.inc. The included > readme-file says that all models are encrypted and must be used in Synopsys > HSPICE. All I got is a free PSPICE version running that supports file > formats like *.opj, *.dsn, *.sch, *.olb, *.lib, *.vhd, *.txt. I already > generated several schematics with PSPICE which I want to test in combination > with the Xilinx models. Unfortunately it looks like that is not possible at > all. Has anyone of you made similar experiences or has a hint how to solve > that incompatibility problem? Any help is highly appreciated. > > Regards, Melanie Nasic > > Hi Melanie, Sorry, but you are out of luck. Due to some interesting 'legal' constraints, PSpice can't read the HSpice encrypted models, and very few manufacturers have yet gone to using the PSpice encrypted models, either. Also, you will probably be unable to use the IBIS models either, as the translators makes too large of files for the student version. What you end up doing is making some reasonable guesses from the datasheets as to the drive and loads, and creating your own models, either as an LRC with a current/voltage driver, or as a behavioral. Best, of course, would be a digital I/O model, but that requires some speciallized knowledge and skills that only a very few have taken the time to master. I know, because I am NOT one of them! Charlie CharlieArticle: 93205
I am implementing a design in a Xilinx FPGA, using ISE 6.1.3i and for reasons that are not important right now, have to flatten the hierarchy "Keep Hierarchy = NO". Because I am doing this I have lost my hierarchical net names that I use in my constraints file. My question quite simply is "How can I identify a net name that was once embedded in a hierarchy and now has been changed into a different net name due to the hierarchy being flattened?" Thanks in advance. SimonArticle: 93206
ITs an AMIRIX AP1070 board . It has a pci bridge external to fpga which acts as an interface between (10/100mbps etherenet, pmc module , 64 bit pci) and the fpga. . I can send data to the pci bridge . i got to find out how to address this data to the host through the 64 it pci. I can send data to the etherenet over the pci brdge..I dont know whther the pci bridge will generate the control signals needed for data transfer to the host since this is not in my control.I can just send data to the bridge . I am also not sure how to confirm that the data has indeed reached the host. NiteshArticle: 93207
Hi Jax, After 5 days of discussion on how to protect the IP, could you say what it is you want to protect? If it's valuable enough for someone to want to copy, it may also be valuable enough for someone to want to buy...Article: 93208
"JustJohn" <john.l.smith@titan.com> schrieb im Newsbeitrag news:1134676056.051566.61770@f14g2000cwb.googlegroups.com... > Hi Jax, > After 5 days of discussion on how to protect the IP, could you say > what it is you want to protect? > If it's valuable enough for someone to want to copy, it may also be > valuable enough for someone to want to buy... > I wondering as well, there are hardly any IP that could make sense to be valued at 100,000 USD for single FPGA netlist license. I cant imagine what it could be that is valued at such high price. If such an IP exist that really is so valueable, then I bet a clean room engineering would be done almost instantly and there is no way to protect against that. Of course in case that the clean room RE is possible without some deep secret know how. humm.. AnttiArticle: 93209
>Weng wrote: >Do you use 'mirror' algorithm to handle the side image pixels? I don't currently have median in anything shipping at the moment, if I did, product documentation would say. >Mirrored frame of image: >row1, row0, row1, ... row1023, row 1022 You've got it! Easy right? Other common options are: 1) Duplication: row0, row0, row1, ... row1023, row 1023 2) Extension: (2*row0-row1), row0, row1, ... row1023, (2*row 1023-row1022) Extra credit if you design it to handle all three. umm Weng, this may be getting a bit far from comp.arch.fpga and comp.lang.verilog, You might try posting to sci.image.processing, they're nice folks over there too. Regards, JohnArticle: 93210
Prateek Singhal wrote: > Hi, > Unfortunately, I can't even do that manually. My port (LPT1) doesn't > come in the list of the ports. The list is empty in fact. Any ideas > what could be wrong? Any checklists for me to double check? Hi, Are you sure you connected the cable at the LPT1 port. The LPT1 should be in the list when you start the iMPACT ouput cable setup. When you select Parallel Cable only port you can select is LPT1 port. Also you need to initialize entire boundary scan chain otherwise you would not be able to program the device if intialize partial chain.Article: 93211
singhal.prateek@gmail.com napisał(a): > Hi, > > Xilinx iMPACT is not detecting my parallel cable III when I am trying > to download > projects to the board. My board is Spartan-3. [...] Maybe, you have computer with LPT port disabled, look at BIOS setup, and be sure that your system (Win XP in Control Panel) see this port. good luck. Jerzy GburArticle: 93212
Simon, You madman, it's hard enough keeping track of the random net name changes every time I run Synplify, let alone flattening the hierarchy. I wonder if you could write a Perl script to compare the before flattening and after EDIF files and recover the names that way? Cheers, Syms. <simon.stockton@baesystems.com> wrote in message news:1134674948.024250.96570@g47g2000cwa.googlegroups.com... >I am implementing a design in a Xilinx FPGA, using ISE 6.1.3i and for > reasons that are not important right now, have to flatten the hierarchy > "Keep Hierarchy = NO". > > Because I am doing this I have lost my hierarchical net names that I > use in my constraints file. > > My question quite simply is "How can I identify a net name that was > once embedded in a hierarchy and now has been changed into a different > net name due to the hierarchy being flattened?" > > Thanks in advance. > > Simon >Article: 93213
al99999 wrote: > Thanks, I'm not using EDK, only ISE, so I need a simple controller for > the CE, OE and WE pins and to put the data and address on the correct > buses at the right times. fpga-cpu group threads about async SRAM strobe & OE timing: http://groups.yahoo.com/group/fpga-cpu/messages/539?threaded=1 http://groups.yahoo.com/group/fpga-cpu/messages/2039?threaded=1 fpga-cpu post with S3 kit SRAM tester: http://groups.yahoo.com/group/fpga-cpu/message/2177 The archive for that is here ftp://members.aol.com/fpgastuff/ram_test.zip And a post on re-compiling it under 7.1 : http://groups.google.com/group/comp.arch.fpga/msg/8955e7209e0c3929 That example includes pipelined SRAM control logic (registered address, data, and tristate contols in IOB registers, gated write pulse ) for the Xilinx/Digilent S3 eval kit. I've started a newer version of that, using a DCM duty cycle tweak, that works at around 60 Mhz with address & data lines all in SLOW slew rate mode, I'll probably update that archive file sometime next month. BrianArticle: 93214
Hi, I work on Xilinx ISE, and my synthesis tool is XST and synplify. I use verilog to write a Inverter Chain (delay ) like out = ~(~(~(~...in)). But the circuit be synthesised cancel all the invorter. How to synthesis out all the inverter chain I want? Any suggestions will be appreciated! Best regards, DavyArticle: 93215
Davy wrote:
> How to synthesis out all the inverter chain I want?
> Any suggestions will be appreciated!
I would use a counter or shifter
to generate the delay.
-- Mike Treseler
Article: 93216Hi Mike, I mean a comb logic delay. DavyArticle: 93217
Hi Andr=C3=A9
I have just completed a 802.3 implementation and I think I can give you
some answers.
First of all my CRC implementation was based on the following paper "A
Symbol Based Algorithm for Hardware Implementation of CRC", R. Nair, G.
Ryan and F Farzaneh.
This implementation uses xor equations to calculate CRC.
In this case the CRC is reset to zero before commencing a new
computation.
2) The final output needs to be bit reversed and inverted i.e
for i in 31 downto 0 loop
CRC(i) <=3D not CRCReg(31 - i);
end loop;
3) On the receiver you pass the whole packet through the CRC generator
including the CRC.
The result in the CRC register after the last byte has gone through
is called the residue, and in the
case of 802.3 it is 0xC704DD7B if there are no errors. All you need
to do is compare the CRC register
with the residue. Note that this is not the bit reversed and
inverted value.
Hope this will help
Sudhir
ALuPin@web.de wrote:
> Hi,
>
> I have been googling for a while
> having noticed that there is no clear answer to my following problem:
>
> The IEEE Std. 802.3 says the following: (section 3.2.8 Frame Check
> Sequence field)
> >Mathematically,the CRC value corresponding to a given frame is de =EF=AC=
=81ned by the following procedure:
> >a)The =EF=AC=81rst 32 bits of the frame are complemented.
> >...
> >e)The bit sequence is complemented and the result is the CRC.
>
>
> I use the following CRC32-VHDL module:
>
> -- File: PCK_CRC32_D8.vhd
> -- Purpose: VHDL package containing a synthesizable CRC function
> -- * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
> -- * data width: 8
>
> -- Info: tools@easics.be
>
> Now I want to simulate the CRC according to the IEEE standard. I have a
> transmitter including the CRC32
> module and a receiver including the CRC32 module.
> But I have some doubts on how to perform a conform simulation.
>
> Let's assume that the following bytes are transmitted via Ethernet(one
> byte interface), they are fed into the easics- module:
> byte0 =3D "00000000" (Integer 0)
> byte1 =3D "00000001" (Integer 1)
> ...
> byte255=3D"11111111" (Integer 255)
>
> Are the following assumptions correct ?
>
> 1. The CRC has to be initialized to
> NOT ("00000011 00000010 00000001 00000000")
>
> 2. The calculated CRC has to be inverted and appended in the following
> manner:
> first byte appendix: NOT CRC(31 DOWNTO 24)
> second byte appendix NOT CRC(23 DOWNTO 16)
> third byte appendix NOT CRC(15 DOWNTO 8)
> fourth byte appendix NOT CRC(7 DOWNTO 0)
>
> 3. To which value do I have to reset the "remote" CRC module ?
>
> 4. Do I have to remove the CRC32 appendix of the Ethernet packets and
> replace the four bytes with "00000000" ?
>
> I would be very thankful if you could shed some light on it.
>=20
> Rgds
> Andr=C3=A9
Article: 93218Davy wrote: > Hi Mike, > > I mean a comb logic delay. > > Davy A combinatorial chain of inverters is probably a bad idea. The timing isn't easily guaranteed within a tight range especially since routing isn't constrained to specific paths. If you *must* try to keep the inverters, synplify would use the syn_keep attribute on the combinatorial elements you don't want removed. Even then, you may need similar constraints in place & route. Please don't go there.Article: 93219
actually whaen u r generating a netlist if u r using series of inverters but using only first input and the final output the synthesis tool will won't consider and it will think as redundant terms during translation phase ............... i think it's easy to use a counter to generate delay .............if there is any ways of generating delay just let me knowArticle: 93220
Hi, Thank you for your help :-) Do you think what's the best way to generate delay smaller than a clock period? Best regards, DavyArticle: 93221
Nitesh, I took a quick look on amirix site : interesting board... The board guide (developboard.pdf) claims that theboard is provided with all necessary stuffs in particular the "apcontrol-windows" (board windows driver + test app) If PCI transfers are single Read/Write initiated from the host, some signals will be updated and your FPGA design should exploit them : to simplify : transfer flag , transfer direction, transfer adress When host reads data, you must provide them in the appropriate register(s) For other PCI transfers - burst / bust mastering , it is a bit more complicated .... The main thing for you is to look at the PCI controller of your board (documentation , programmation method) "Nitesh" <nitesh.guinde@gmail.com> wrote in message news:1134675967.936128.110380@g44g2000cwa.googlegroups.com... > ITs an AMIRIX AP1070 board . It has a pci bridge external to fpga which > acts as an interface between (10/100mbps etherenet, pmc module , 64 bit > pci) and the fpga. . I can send data to the pci bridge . i got to find > out how to address this data to the host through the 64 it pci. I can > send data to the etherenet over the pci brdge..I dont know whther the > pci bridge will generate the control signals needed for data transfer > to the host since this is not in my control.I can just send data to the > bridge . I am also not sure how to confirm that the data has indeed > reached the host. > Nitesh >Article: 93222
According to <http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D27812%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html> The spartan 3e starter kits are available yet xilinx says they are not ? AlexArticle: 93223
"Alex Gibson" <alxx.nospam@nospam.tpg.com.nospam.au> schrieb im Newsbeitrag news:40f560F19kqhsU1@individual.net... > According to > <http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D27812%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html> > > The spartan 3e starter kits are available yet xilinx says they are not ? > > Alex > 6 weeks ago Avnet told me that they have already shipped 400 pieces of the s3e kit. and I belive they did not lie about that. the only s3e I have seen on board from cesys http://www.cesys.de/index.php?language=en&doc=advanced&docparams=USB3FPGA&menuparams=53 so at least one company is actually shipping s3e boards (I assume avent is not shipping as they are out of stock..or are those 18 boards they had still unsold?) AnttiArticle: 93224
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:dntnb5$3d1$1@online.de... > "Alex Gibson" <alxx.nospam@nospam.tpg.com.nospam.au> schrieb im > Newsbeitrag news:40f560F19kqhsU1@individual.net... >> According to >> <http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D27812%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html> >> >> The spartan 3e starter kits are available yet xilinx says they are not ? >> >> Alex >> > > 6 weeks ago Avnet told me that they have already shipped 400 pieces of the > s3e kit. > and I belive they did not lie about that. > > the only s3e I have seen on board from cesys > http://www.cesys.de/index.php?language=en&doc=advanced&docparams=USB3FPGA&menuparams=53 > > so at least one company is actually shipping s3e boards > (I assume avent is not shipping as they are out of stock..or are those 18 > boards they had still unsold?) > > Antti > > uups, I did not check out your link, I dont have any idea if Avnet shipping the 500E board, they have shipped 100e boards for sure, and as others are shipping 500e based boards I guess avent may as well have them ready for shipping. so its only Xilinx itself who is delaying with dev board releases Antti
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