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I Am Doing A Project On FPGA Using LZ Algo In VHDL. Can SomeOne Help On how to go about it and with code also i will be indeed greatful. thank you Lt ApurveArticle: 93251
This is why I like redirects. Here is a better link to the Xilinx Spartan-3E Starter Kit board web page. http://www.xilinx.com/s3estarter ... which redirects to the correct location ... http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-DK --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 93252
Possibly Avnet was referring to their Spartan-3E Evaluation Kit, which has an XC3S100E FPGA on it. This board has been shipping for awhile. http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D21564%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html The XC3S500E-based Spartan-3E Starter Kit board should be available in the next few weeks. http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D27812%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 93253
The Spartan-3E Starter Kit board will be available in roughly two weeks. You can sign up to receive E-mail notification when order entry is opened. http://www.xilinx.com/xlnx/xebiz/utils/availabilityform.jsp?key=HW-SPAR3E-DK The board was delayed for a good reason. Two of our board partners upgraded the Flash and DDR SDRAM memory -- now twice the density of the previous description at no additional cost! --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 93254
Aaaargh! Pilot error on my part. My apology. This is why I like redirects. Here is a better link to the Xilinx Spartan-3E Starter Kit board web page. http://www.xilinx.com/s3estarter ... which redirects to the correct location ... http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.j... --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 93255
"Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> schrieb im Newsbeitrag news:1134761443.681907.191430@g44g2000cwa.googlegroups.com... > The Spartan-3E Starter Kit board will be available in roughly two > weeks. You can sign up to receive E-mail notification when order entry > is opened. > http://www.xilinx.com/xlnx/xebiz/utils/availabilityform.jsp?key=HW-SPAR3E-DK > > The board was delayed for a good reason. Two of our board partners > upgraded the Flash and DDR SDRAM memory -- now twice the density of the > previous description at no additional cost! > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/-3E FPGAs > http://www.xilinx.com/spartan3e > --------------------------------- > The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. > so whats the target date? it was promised in December but its still only 'register for notification' what effectivly says nothing. AnttiArticle: 93256
John and Kolja: The quality of the input signal is something I suspected initially but I ruled out any major interference problems early on. Here's my line of thinking: - The bad pixels are always the same color as the image data. Corrupted colors do not occur. If I create a white background with a blue box in the center, there will be some white pixels scattered inside the box and blue pixels scattered around outside. - Each time the input is clocked (by the external Z80), the internal write pointer is incremented. If there were any glitches on this line, the image would be offset and for my test cases (boxes and such), it would be very noticable. What I initially wanted to do to fix the problem is write some code like this: if clk_50mhz'event and clk_50mhz = '1' then -- main clock if input_clk_prev = '0' and input_clk = '1' then -- input clock detected. sample the data end if; input_clk_prev <= input_clk; end if; It didn't work. Although it may have sort of helped solve the problem, what was happening is that it was triggering much more often than it should, causing the write pointer to increment incorrectly and thus garbling up the image. I did a test where I had an 8051 send a set number of clock pulses to the FPGA and I displayed the number on the LEDs. It was always correct. When I used the above code, it would be off by 1 every now and then. johnp wrote: > Also, you mentioned trying to synchronize the sram_do_write signal > to the 50MHz clock - you must do that! Otherwise, you've got an async > signal feeding into your state machine - just a matter of time before > it screws up. This is probably the issue. Last night, I may have fixed it. What's unusual is that I had tried similar code before to synchronize the signal and it failed to make a difference. I'll try to show you what I did. I don't have my code with me at the moment so this is going off of memory. Any thoughts on whether this is a sound method? Is it too much of a kludge? process(input, clk_50mhz) begin if input(4)'event and input(4) = '1' then -- input(4) is input CLK do_write <= NOT do_write; end if; if clk_50mhz'event and clk_50mhz = '1' then if do_write_prev /= do_write then sram_do_write <= '1'; end if; if sram_state = SRAM_WRITE then sram_do_write <= '0'; end if; do_write_prev <= do_write; end if; end process; The idea is that I monitor do_write and when it changes, I signal sram_do_write in sync with the FPGA master clock. Oddly enough, I tried code almost exactly like this earlier (both in this process and in the SRAM state machine) and it never worked! I was using a XOR to detect a change (if the XOR result was 1, a change occured) -- would that make a difference? To me, it seems the two are functionally equivalent. Thanks for the input so far!Article: 93257
Great !! The problem was actually trivial. It was exactly what you said. All the ports were disabled in the BIOS configuration. Thanks a lot. :) Prateek Singhal Jerzy Gbur wrote: > singhal.prateek@gmail.com napisa=B3(a): > > Hi, > > > > Xilinx iMPACT is not detecting my parallel cable III when I am trying > > to download > > projects to the board. My board is Spartan-3. > [...] > > Maybe, you have computer with LPT port disabled, look at BIOS setup, and > be sure that your system (Win XP in Control Panel) see this port. >=20 > good luck. >=20 > Jerzy GburArticle: 93258
<acetylcholinerd@gmail.com> schrieb im Newsbeitrag news:1134749195.253021.113850@g44g2000cwa.googlegroups.com... > Hello! Having finished a board design with a Virtex-4FX and with > promising leads on the silicon, I sat down to begin my HDL coding... > when I discovered that the simulation models for the Virtex-4 PPC and > MAC components are only available in encrypted form. After poking > around a bit on the net and usenet, it seems that only the really > high-end simulators can support these encrypted models. Has anyone > found an inexpensive HDL simulator which supports these encrypted > models, or any other way to design with the cool features of the Virtex > 2-pro and Virtex-4FX? > > Thanks, > ...Eric > the only low cost thing is... the silicon itself, set the stuff up and load into the FPGA together with ChipScope and test it out AnttiArticle: 93259
The price is ridiculously low.. u guys are gonna kill the competition, and your partners which are selling sub $200 fpga board too. If im not mistaken, there will be a usb downloader (usb platform cable) as an additional goody? Any idea when we'll see XC3S-E up for sale on the xilinx website? Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote: > The Spartan-3E Starter Kit board will be available in roughly two > weeks. You can sign up to receive E-mail notification when order entry > is opened. > http://www.xilinx.com/xlnx/xebiz/utils/availabilityform.jsp?key=HW-SPAR3E-DK > > The board was delayed for a good reason. Two of our board partners > upgraded the Flash and DDR SDRAM memory -- now twice the density of the > previous description at no additional cost! > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/-3E FPGAs > http://www.xilinx.com/spartan3e > --------------------------------- > The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 93260
"Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> wrote in message news:1134761443.681907.191430@g44g2000cwa.googlegroups.com... > The Spartan-3E Starter Kit board will be available in roughly two > weeks. You can sign up to receive E-mail notification when order entry > is opened. <snip> So no Christmas this year! And here I was hoping "available in December" was a tease for the present pile rather than a New Year's eve party favor. Thanks for the updates, Steve.Article: 93261
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:eEFof.83$lb5.41@news-west.eli.net... > "Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> > wrote in message > news:1134761443.681907.191430@g44g2000cwa.googlegroups.com... >> The Spartan-3E Starter Kit board will be available in roughly two >> weeks. You can sign up to receive E-mail notification when order entry >> is opened. > <snip> > > So no Christmas this year! > And here I was hoping "available in December" was a tease for the present > pile rather than a New Year's eve party favor. > > Thanks for the updates, Steve. > uups! I did think (silly me) that what Steve was referring to was that avnet will ship their s3e500 board in 2 weeks, as Xilinx promised the their S3e starterkit in December! well roughly 2 weeks means defenetly after christmas and possible not in 2005 at all. meaning that the only boards shipped from public online orders this year could be 1) s3e-100 eval from avnet 2) s3e-500 usb board from cesys 3) or is there any other s3e board already been shipped to customers (available for general public orders!)? but the xilinx s3e-starter board has most bang for the buck so it pays to wait for it of course AnttiArticle: 93262
Please email offers. Looking to purchase immediately.Article: 93263
yes the main problem was the apcontrol program ( I am using linux based ) can read data from memory onboard. But I want to do burst transfers to host from module in fpga and I need to capture this data on host side. I am integrating PLB master module to transfer data to the pci and then will look into the host side communication. My doubt initially was how does the tranfer between the pci bridge and host pci take place. Should I intiate some control signals. However there are no extra control signals ... i.e I can send a ping to etherenet over the pci bridge with no additional signals just address and data .Hopefully it will be same in the pci case. Any other advise for what I should be looking into....Article: 93264
Bart - I suspect the problem is that you are supplying no setup/hold time on the sram address bus. Also, no hold time on the data bus: sram_addr <= sram_write_addr; sram_ce <= '0'; sram_we <= '0'; sram_io_t <= '0'; Try using a 3 clock cycle sequence to write the rams: a) assert the correct address b) assert data, CE, and WE c) remove CE and WE If your ram is fast enough, you can shorten the to 2 clock cycles by using a negedge clock to assert/remove WE. Good luck! John ProvidenzaArticle: 93265
Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote: > Aaaargh! > > Pilot error on my part. My apology. > > This is why I like redirects. Here is a better link to the Xilinx > Spartan-3E Starter Kit board web page. > > > http://www.xilinx.com/s3estarter > > > ... which redirects to the correct location ... > > > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.j... > > > > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/-3E FPGAs > http://www.xilinx.com/spartan3e > --------------------------------- > The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. > Hi Steve, the avnet site indicates that there will be a vga port (I assume similar to the Spartan 3 eval board) + a 2 line LCD but the Xilinx site does not mention the vga port. Is it still on the S3E board? Thanks GlennArticle: 93266
Nitesh, This is the PCI controller of your board which initiates the burst transfer (bus mastering) , Before that, either your application (C/linux) or your design (VHDL) must provide transfer length AND physical memory start adress. Lookt at your doc to see how the actual 'go' signal (i.e start DMA transfer) is provided to the controller (onthe board i use at work, it is up to the C application to write to a register of the DMA ctlr) "Nitesh" <nitesh.guinde@gmail.com> wrote in message news:1134779159.628317.217180@g43g2000cwa.googlegroups.com... > yes the main problem was the apcontrol program ( I am using linux based > ) can read data from memory onboard. But I want to do burst transfers > to host from module in fpga and I need to capture this data on host > side. I am integrating PLB master module to transfer data to the pci > and then will look into the host side communication. My doubt initially > was how does the tranfer between the pci bridge and host pci take > place. Should I intiate some control signals. However there are no > extra control signals ... i.e I can send a ping to etherenet over the > pci bridge with no additional signals just address and data .Hopefully > it will be same in the pci case. Any other advise for what I should be > looking into.... >Article: 93267
Hi, I am looking for a FPGA based video prototype board with the following components: 1 Video decoder for 1 color composite Video in 1 FPGA preferably Altera About 1 Megabyte SRAM Some spare IO pins 1 Color composite video out The boards I have found are too expensive and have a lot of other hardware like multiple FPGAs or DSPs, which I don't need. Someone an idea? Thanks! MarkusArticle: 93268
Hi all ! I bought a S3board from digilent. I ran some program to test it, included a serial parallel multiplier :) I'm currently thinking of a new project "just for fun". When I learned vhdl at university, we start a project by coding a very simple processor, who looks like a very simple picoblaze. Do you think if it's do-able to implement a pico blaze, plug it (internally in the fpga) with an uart and to run a kind of monitor ? For example with a 68K board, when from the console you can access to memory, dump or modify it, run some assembler command etc etc. I would like to run a kind of very simple SBC with this system. I read the documentation about picoblaze, but I'm afraid that the program must be written when compiling the vhdl ? Could we load the execution code, for example in the sram ? Thanks a lot, xavier.Article: 93269
xavier.tastet@gmail.com <xavier.tastet@gmail.com> wrote: > Hi all! Hi! > I read the documentation about picoblaze, but I'm afraid that the > program must be written when compiling the vhdl? This is possible. You can also use your own module which evaluates the address signal and returns the opcodes. Actually, the compiled-in vhdl is just a BRAM, I don't see why one shouldn't replace it by an SRAM-handling module. > Could we load the execution code, for example in the sram? Perhaps you might also want to have a look at <http://www.xs4all.nl/~marksix>, there is an UART-example available. If you want to download the code from the host, you can use the BRAM as a handler and poke the stream from the rs232 to the SRAM, afterwards switching the instruction source (with another module located between BRAM and SRAM, probably controlled by one of picoblaze's outports). -- mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver Die Liebe ist wie ein Bauantrag: am besten, du kümmerst dich nicht drum, dann erledigt sich die Sache von selbst (Jochen Busse in "Das Amt")Article: 93270
Hi, I have a memory controller desing implemented for Virtex4 chip. I know there are some timing problem and suspect that it is because the delay difference between the different timing pathes are too much. There is a common clock generated from DCM driving all the logic. Currently I launtch the desing in FPGA Editor and try to collect the delay for all the pathes, but that is really a lot of work. I start from the DCM output, count the delay one net by one net up to the pad, and sum them up. And do this for all the pathes seem impossible. I wonder if there are any trick to do this kind of thing faster? Thanks.Article: 93271
Hi John, Thank you for your inputs. I am wondering if there is a median value filter algorithm to deal with 1 pixel for 1 clock. That is, one pixel is in and one pixel is out in real time. Is there any advantage if the algorithm is found? The article and the algorithm you mentioned from Xilinx design paper uses 3 clock to handle 1 pixel. WengArticle: 93272
In terms of free model checkers, I've had the best luck with NuSMV. It doesn't have an HDL front-end, but does support a subset of PSL. There is a path to get Verilog into NuSMV using Icarus and Confluence's netlister (FNF), but the Verilog front-end is bit out of date. A better option is HDCaml. It already has a builtin simulator; once the link to NuSMV is completed, any counter example would produce VCD waveforms for debugging. HDCaml already generates synthesizable Verilog and SystemC. You'll find both the Icarus-FNF-NuSMV tool chain and the HDCaml HDL here... http://www.confluent.org/ Of course if money's no object, I recommend Cadence IFV. -TomArticle: 93273
<xavier.tastet@gmail.com> schrieb im Newsbeitrag news:1134858416.979455.73070@o13g2000cwo.googlegroups.com... > Hi all ! > I bought a S3board from digilent. I ran some program to test it, > included a serial parallel multiplier :) I'm currently thinking of a > new project "just for fun". When I learned vhdl at university, we start > a project by coding a very simple processor, who looks like a very > simple picoblaze. > Do you think if it's do-able to implement a pico blaze, plug it > (internally in the fpga) with an uart and to run a kind of monitor ? > For example with a 68K board, when from the console you can access to > memory, dump or modify it, run some assembler command etc etc. I would > like to run a kind of very simple SBC with this system. > I read the documentation about picoblaze, but I'm afraid that the > program must be written when compiling the vhdl ? Could we load the > execution code, for example in the sram ? > Thanks a lot, xavier. > look at thre are several examples http://www.dulseelectronics.com/ BTW we have a gui for the Picoblaze based Logic Analyzer from the dulse website AnttiArticle: 93274
This should fit your needs.... http://altera.com/education/univ/materials/boards/unv-de2-board.html Greats, Karl. Markus Knauss wrote: > Hi, > > I am looking for a FPGA based video prototype board with > the following components: > > 1 Video decoder for 1 color composite Video in > 1 FPGA preferably Altera > About 1 Megabyte SRAM > Some spare IO pins > 1 Color composite video out > > The boards I have found are too expensive > and have a lot of other hardware like multiple FPGAs or DSPs, > which I don't need. > > Someone an idea? > > Thanks! > > Markus
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