Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
JustJohn <john.l.smith@titan.com> wrote:
> Hi Adrian,
Hi!
> There is a lot wrong here, and I can't teach you all about H/W design
> vs. S/W coding, but will try to touch on some key points. I had a look
Thank you so much, these were exactly the points I needed. They've
guided me on the (more or less complete) rewrite.
> All the problems here stem from a common source, thinking that a H/W
> process is like a S/W procedure or function, but it is not. Concentrate
> on the basic way process works in synthesizable code: Whenever an event
> occurs on a member of the sensitivity list, the process is entered,
> statements run 'in an instant', and the process exits.
This was necessary to understand and it works now. I'll ask
my professor to slightly change the basic vhdl course[0];
we do not do a lot, just combine some flip flops, but never
realize that there are statements which compile but won't
work (and yes, I thought the VHDL compiler is as strict
as an Ada compiler)
Thank you (and the others) for your patience.
[0] You cannot call this a course, it is only a laboratory with
let's say five hours for VHDL in total
--
mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver
Alt-F4 ist die Grundlage jeden vernünftigen Arbeitens mit Windows.
Article: 92251Antti Lukats wrote: > S3E development board, how low can it go? > http://xilant.com/content/view/15/51/ Interesting, - but isn't 28 pins a little light - just 16 FPGA I/O ? perhaps double rows, would keep a similar form factor, backward compatible to DIP28, but allow 0.1" expansion to 56 pins ? No mention of the size/speed of the dataflash ? re Lattice "newsflash"on link above - hmmm, reads like classic competitor FUD. OK, their balance sheets are not stellar, but are fairly typical for an average semi company. Their sales trends indicate to me that their older parts are tailing off faster than the new parts ramp up, but that is temporary. Assets look strong, and they are pumping money into Fujitsu for long term FAB edge. All up, I'd take such FUD as signs the competitor is seriously worried by what they can see comming ! :) Altera must be miffed by Lattice, who have trumped their MAX II, with the better MachXO, AND also have Zero Power CPLDs, so have Altera's old technology CPLD market in a pincer movement. What are Xilinx planning in CPLDs ? -jgArticle: 92252
Hi all, is there a way to access the phase accumulator in Xilinx DDS 5.0? (preferably from VHDL) I'd like to determine the carrier phase between two modulated signals by phaselocking an NCO on each one and then subtracting the phase accus. Given that there is a great DDS already, I dislike reinventing it just to tap an internal signal. BTW the register interface is nice if I want to setup everything with a microcontroller. But --- in a pure hardware environment it is clumsy to multiplex frequency word and phase modulation to a 32 bit data bus + address line + WE, knowing the first thing to happen is that they will be demultiplexed again into different registers. In addition the update rates are halved and potentially simultaneous frequency/phase updates need to be scheduled. (Options for DDS 5.1???) best regards, GerhardArticle: 92253
Martin One good place for information is the libraries guide. A version of it is here http://toolbox.xilinx.com/docsan/xilinx7/books/docs/lib/lib.pdf . The RAMB16 macros are basically the size of a single block ram - 16Kbit (18Kbit with parity). There is also help on ram component instantiation in ISE (I believe this is in Webpack). If you click on the lightbulb icon in the ISE tool you should get to some templates. I don't think you will find any other size as ready built macro for Xilinx RAM. You will have build that up yourself if you don't have Coregen. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> wrote in message news:4385f45c$0$12126$3b214f66@tunews.univie.ac.at... >> The RAMB16 elements are the raw RAM macros. The Sx part of the name >> indicates the port width. You can build up bigger memories in Coregen >> which is a bit like the Altera Megawizard tool or build them up yourself >> using generic statements using the raw macros. > > Can you describe this a little bit more specific, please? Are the > other components available to describe Xilinx block RAMs? > > BTW: With the web edition I don't have Coregen and I also don't > use the Megawizzard in Quartus. Ideal setup is a single generic > parameter with the memory size (in lenght of the address). > >> If you looking at switching between vendors one trick is to hide a RAM >> inside a wrapper file. If you use the wrapper level as the RAM component >> for instantiation then you will only have to change the technology based >> memory element in one place i.e. the the wrapper file. > > That's the way I do it. I switch between technologies with different > files in the project. I also use this different VHDL files in projects > for other customization - primitiv, but efficient. > > >> Some synthesisers are capable of inferring RAM usually using an indexed >> array of something like VHDL's "std_logic_vector". I can't tell you much >> about the results as it isn't my own preferred method but a non-vendor >> synthesiser may do better than one offered by the silicon vendors. > > The Xilinx tool interffered distributed RAM from the VHDL description. > A thing I definitely don't want. Quartus had problems with the > different port sizes, but single port sizes work very well. > > Martin > > >>> >I would like to code the on-chip memory in vendor neutral VHDL. >>>> I got it running for a dual-port memory with single clock and >>>> same port sizes for the read and write port. >>>> >>>> However, I need a memory with a 32-bit write port and an 8-bit >>>> read port. So far I was not able to code it in VHDL in a way >>>> that the Synthesizer inferres the correct block ram without >>>> an extra read MUX. >>>> >>> >>> I'll give up one this vendor independent block RAM project. For >>> the 32-bit write data, 8-bit read data with registered address, >>> in data and unregistered out data RAM coded in VHDL I got: >>> >>> On the Altera Cyclone: generates a 32-bit dual port RAM with an >>> external 4:1 MUX. This MUX hurts fmax (from 94MHz down to 84MHz)! >>> >>> On the Xlinix Spartan-3: The RAM gets implemented as distributed >>> RAM! Uses a lot of LCs and the fmax goes from 65MHz down to >>> 50MHz >>> >>> So I will bite the bullet and use two vendor specific VHDL files. >>> However, there is one open issue: I want the memory size be >>> configurable via a generic. This is possible with Alteras >>> altsyncram. >>> >>> For Xilinx I only know those RAMB16_S9_S36 components where >>> the memory size is part of the component name. Is there a >>> a Xilinx block RAM component where I can specify the size? >>> >>> Thanks, >>> Martin >>> >> >> > >Article: 92254
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:43862d44$1@clear.net.nz... > Antti Lukats wrote: >> S3E development board, how low can it go? >> http://xilant.com/content/view/15/51/ > > Interesting, - but isn't 28 pins a little light - just 16 FPGA I/O ? > perhaps double rows, would keep a similar form factor, backward compatible > to DIP28, but allow 0.1" expansion to 56 pins ? > > No mention of the size/speed of the dataflash ? > > re Lattice "newsflash"on link above - hmmm, reads like classic competitor > FUD. > > OK, their balance sheets are not stellar, but are fairly typical for an > average semi company. > Their sales trends indicate to me that their older parts > are tailing off faster than the new parts ramp up, but that is > temporary. Assets look strong, and they are pumping money > into Fujitsu for long term FAB edge. > > All up, I'd take such FUD as signs the competitor is seriously > worried by what they can see comming ! :) > > Altera must be miffed by Lattice, who have trumped their MAX II, > with the better MachXO, AND also have Zero Power CPLDs, so have > Altera's old technology CPLD market in a pincer movement. > > What are Xilinx planning in CPLDs ? > > -jg > Hi Jim, there is actually a pin desnsity upgrade available in the same form factor, but reatining compatibility with single density, so board standard goes to some 96 ios BTW the competitor gossip was not from Altera ;) and I personally really think that the MachXO is way better than MAX2 and tha new Lattice low cost/flash FPGAs are nice too. But Lattice has also tons of old too expensive chips that nobody really wants I guess, and at the time they are working towards 90nm and 65nm FPGAs the profit lass could be temporary - interesting times in any case AnttiArticle: 92255
Jim, I do not know what Xilinx CPLD are (American:" is") planning, and if I knew I would not tout it in this public forum. But think about it: going up against a small but established, hard-working but money-losing, floundering and increasingly desperate competitor is not the most exciting proposition. Might get anybody a bloody nose... Peter AlfkeArticle: 92256
Hi Group, from "Actel is bringing ARM7 to the masses with no upfront licensing fees and no royalties" - this is totally nonsense! I have been trying to buy 1 sample ARM7 ready device from Actel for some time now, calling them and asking all over again. They claim that ARM ready PA3 silicon is available, but pricing? As soon as I try to ask the prices they will start to explain the licensing policy. So the best pricing I have gotten is: "if you buy 100,000 then for the 'ARM ready' feature the additional price per FPGA is 1 USD, for smaller quanties the additional pricing has to 'scaled' down" ...I can do the math I think. Actel has failed to give any prices at all for any ARM ready silicon (other than the quote above). Smallest PA3 that could be ARM ready is 250 device, where the ARM would occupy 98,2% meaning its actually fully unuseable. Smallest PA3 where ARM use would make sense as of resource utilization is the 600 device, what is targetterd to be available in Q1... ... year 2007 So the only PA3 that is ARM ready and available now is PA3 -1000, available means that it is claimed to be available, 4+ weeks lead time is to added in any case. Not to mention that the website downloadable ARM Core integrator tool is not FREE but time limited for 45 Days (sale price not known!) and that the current version does not allow any user IP cores to be added to the ARM SoC !!! This is promised in next release. That will become available after the free evaluation time is expired I guess. Not to mention that the Actel FPGA optimized ARM core runs at bazing speed of 25MHz max. way to go! down Antti's 2 cents PS Sorry Martin M,.I do say what I think.Article: 92257
A follow-up to my lamenting ;-)
I started to define and implement a 'new' SoC inertconnect
(Yes, just another interconnect 'standard'). However, will
see how far this gets.
> In the WB specification (AFAIK) there is no way to perform pipelined
> read or write. However, for blocked memory transfers (e.g. cache
> load) this is the usual way to get a good performance.
>
> Conclusion -- I would prefer:
>
> * Address and data (in/out) register in the slave
> * A way to know earlier when data will be available (or
> a write has finished)
> * Pipelining in the slave
>
> As a result from this experience I'm working on a new SoC
> interconnect (working name SimpCon) definition that should avoid the
> mentioned issues and should be still easy to implement the master
> and slave.
The idea for (some) pipeline support is twofold:
1.) The slave will provide more information than a single ack
signal or wait states. It will (if it is capable) signal the
number of clock cycles remaining till the read data is available
(or the write has finished) to the master. This feature allows
the pipelined master to prepare for the upcoming read.
2.) If the slave can provide pipelining, the master can use
overlapped wr or rd requests. The slave has a static output
port that tells how many pipeline stages are available.
I call this 'pipeline level':
0 means non overlapping
1 a new rd/wr request can be issued in the same cycle
when the former data is read.
2 one earlier and
3 is the maximum level where you get full pipelining
on the basic read cycle with one wait state
(command - read - wait - result).
The draft of the spec at the moment are few sketches on real
paper - takes some time to draw all diagrams for a document
(BTW does anybody know a tool for quick drawing of timing
diagrams).
The spec. is still not written, but I've implemented it in JOP
for the Cyclone and for the Spartan-3. Both sub-projects use
now the same memory interface and the Spartan version
benefits from the bytecode block cache that was up to now
only available in the Cyclone version.
If you are interested in the implementation download the sources
from [1] or from the CVS [2] at opencores.org. You can find
the SimpCon master in mem_sc.vhd and a slave for a 32-bit SRAM
in sc_sram32.vhd. The master uses a pipeline level of 2 for
the bytecode cache load. There is also a ModelSim simulation
available at modelsim/sc.bat.
Comments are very welcome,
Martin
[1] http://www.jopdesign.com/download.jsp
[2] cvs -d :pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous -z9 co -P jop
Article: 92258"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1132870104.343175.63960@f14g2000cwb.googlegroups.com... > Jim, I do not know what Xilinx CPLD are (American:" is") planning, and > if I knew I would not tout it in this public forum. > But think about it: going up against a small but established, > hard-working but money-losing, floundering and increasingly desperate > competitor is not the most exciting proposition. Might get anybody a > bloody nose... > > Peter Alfke > Xilinx is the only FPGA vendor that does not offer non volatile fpga's. (Altera MAX2 is an small FPGA no matter what their marketing says). Xilinx has not made any (significant) new PLD announcements for a while -so either Xilinx will eventually completly get out from flash-pld nonvolatile things, or ... something would come ? If it comes, I hope that Xilinx Press Release will appear AFTER Xilinx webshop has been setup to take orders for the new NV device family (for immediate shipping). That would be something! When the V4 spins off nicely, then it could be good idea to make a quick take and grab off the cream of NV-pld business as well, there is exactly enough time to monitor how the altera-lattice small pld-nvfpga things (max2-machXO) are doing. Could be there is not much money to grab on that market of course. I wonder why ST cancelled their project to introduce ARM with on chip PLD? Possible their stacked die technology would have been to expensive, or there wasnt enough interest (my interest doesnt seem to be enough...) AnttiArticle: 92259
Hi, I realize that using XST division and mod is only possible when the divisor is power of 2. May I know whether is there any way of getting around this problem? Does the usage of std_numeric solve this problem, or do I have to write my own algorithm to do this? Is there any predefined package somewhere that can do this for me?Article: 92260
> > S3E development board, how low can it go? > http://xilant.com/content/view/15/51/ > > Hello Antti, your board is very similar to our GOP_XC3S200 FPGA board, which has a DIL24 PAL/GAL compatible footprint. And your company is in our neighborhood. Let's have a beer together ? MIKE -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho !Article: 92261
Wow. That's it exactly. I inverted the first DCM lock and fed it to the second DCM reset and all the clocks scope good now. I'll play around with adding a delay, as you suggested, later. Thank you ever so much. Brad Smallridge aivison.com > Therefore, I think you need to hold the second DCM in reset until the > first > DCM locks (this is mentioned in several app-notes).Article: 92262
Hello, I have a ChipScope ILA and ICON instantiated on the top-level MHS file like this: BEGIN chipscope_icon PARAMETER INSTANCE = chipscope_icon_0 PARAMETER HW_VER = 1.00.a PORT control0 = control0 END BEGIN chipscope_ila PARAMETER INSTANCE = chipscope_ila_0 PARAMETER HW_VER = 1.00.a PARAMETER C_DATA_SAME_AS_TRIGGER = 0 PARAMETER C_DATA_IN_WIDTH = 256 PARAMETER C_NUM_DATA_SAMPLES = 2048 PARAMETER C_TRIG0_TRIGGER_IN_WIDTH = 32 PARAMETER C_TRIG0_UNIT_MATCH_TYPE = "range with edges" PORT CHIPSCOPE_ILA_CONTROL = control0 PORT TRIG0 = chipscope_ila_0_TRIG0 PORT CLK = sys_clk_s PORT DATA = chipscope_ila_0_DATA END BEGIN my_pcore ... PORT debug_port = chipscope_ila_0_DATA ... END The issue I'm having is with how the ILA is interpreting the bit-ordering of the DATA input. chipscope_ila_0_DATA is a 256-bit bus declared as [255:0] inside my pcore and in its MPD file as well. Because the waveform output are not making any sense, I set 4 bits in the bus high. These bits are [157:154] in my debug_port. In the ChipScope wave viewer, they are bits [221:218]. Now, I suspected that maybe the ILA is reversing the ordering, but when you switch the order (bit 255 becomes 0), [157:154] should be [98:102]...What could ChipScope be doing with the ordering of the bits? Thanks, NNArticle: 92263
Antti Lukats wrote: > Hi Group, > snip > > Not to mention that the Actel FPGA optimized ARM core runs at bazing speed > of 25MHz max. > > way to go! Amazing, I've done several fpga protypes of arm7tdmi-s SoCs in Virtex2e and without even touching the ARM rtl or attempt any floorplaning it'll run faster than that using XST -LasseArticle: 92264
Antti Lukats wrote: > Hi Group, > > from "Actel is bringing ARM7 to the masses with no upfront licensing fees > and no royalties" - this is totally nonsense! > I have been trying to buy 1 sample ARM7 ready device from Actel for some > time now, calling them and asking all over again. They claim that ARM ready > PA3 silicon is available, but pricing? As soon as I try to ask the prices > they will start to explain the licensing policy. > > So the best pricing I have gotten is: > > "if you buy 100,000 then for the 'ARM ready' feature the additional price > per FPGA is 1 USD, for smaller quanties the additional pricing has to > 'scaled' down" > > ...I can do the math I think. > <snip> > Not to mention that the Actel FPGA optimized ARM core runs at bazing speed > of 25MHz max. > > way to go! Hmmm, Philips offer ARMs starting at $1.47 - and you get FREE RAM.FLASH.ADC.SPI.UART perhipherals, less EMC, faster operation.... What Actel should quote is the incremental cost, of adding ARM into an Actel FPGA : Oops, need to upsize the FPGA - say +$30, and pincount, and add memory; what I need more PCB layers too ? Seems merely someone in marketing thought it was a good idea.... -jgArticle: 92265
My settings are Dell Precision 420, 1GB RAM, Multilinx with COM1, a JTAG chain comprising five xc18v04, one xc18v02. My FPGA is virtex 2 - 6M gate. It took me some 20 minutes to program each one of the PROM device, and it tend to fail in the middle, maybe 3,4,5th device. Is this normal behavior? Thanks in advance.Article: 92266
One more question, My FPGA is tied with the 6 PROMs, so on power on, FPGA is automatically programmed by the PROM. Now some of my PROMs are erased and some failed programming, thus an incomplete bitstream in the PROMs. What will happen when I switch on power? My board gave me dimmly lit LEDs (tied to FPGA pins). Why when I reprogram the FPGA alone via JTAG cable, it always fails? Previously some other people programmed PROM successfully, FPGA is programmed by PROM upon power-on, and I could reprogram FPGA via JTAG connectors.Article: 92267
I've made a PowerPC Application for Virtex-II FPGA in EDK. The version is 7.1. To generate a bit file using Xilinx ISE, the bmm file (block RAM memory map file) needs to be given to the ngdbuild. I'm providing this file as '-bm system.bmm' in the xflow script. Now ngdbuild completes, but map gives following error for all BRAM blocks ERROR:MapLib:482 - Blockram ramb16_s1_s1_28 is a memory mapped blockram generated for the Microprocessor. However it is not connected properly, causing it to be trimmed. Please connect up all memory mapped blockram properly and re-run Ngdbuild. What can be the reason for this? the system.bmm is generated by EDK only. Regards, MilindArticle: 92268
Hey, mstrug, you must be kidding! For years I buy in Poland various Xilinx chips with prices almost the same as in US. And there is no problem to buy even a single piece. This was the reason why I selected (many years ago) Xilinx: in times where it was hard to buy most semiconductors, Xilinx rep offered good availability and support. Dz. <mstrug> wrote in message news:ee92126.4@webx.sUN8CHnE... > Yes, I had a reason for using XC2000 device. I'm from Poland and here there is no way to buy any of Xilinx FPGA device, even if I found in some Internet shop in Poland FPGA, it is too expensive. Buying FPGA in shop in foreign countries where FPGA are chip, price of shipping to Poland is also too high. I have two XC2064 and I want use it to build FIFO dedicated driver for SRAMs memory. I know that it could be builded in this device because I have old PC/104 single board computer which has FIFO driver in XC2064. > > If there is no way to get old XACT software, I probably buy CPLD from Atmel because its price is very less than Xilinx CPLD (in Poland). But on the other hand the software from Atmel for his CPLD is realy poor (in front of Xilinx Webpack). Meybe I design my device in webpack and then convert it to the atmel device. This will be probably the most economical solution for me.Article: 92269
Hi All, I am working on a design targeted to Altera Stratix Gx I am using high speed macro (gxb macro) in the design. while doing implementation I want to elaborate the hierarchy by using "Maintain Hierarchy" option in Synthesis. but I don't want to elaborate "gxb macro" part how do I do it...? can I declare that instance as black box...? how to do that in Quartus II...? Thanks Regards KedarArticle: 92270
Hi Antti, back from New Zealand? Thank you for saying this, 100% ACK. (I didn't dare to say as I offer a "competing" core -> ERIC5, www.entner-electronics.com ) Generally I think that Soft-Core-CPUs in FPGAs make only sense when they are tailored for that application, otherwise price / performance will never fit. Regards, Thomas "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:dm5eiu$l36$1@online.de... > Hi Group, > > from "Actel is bringing ARM7 to the masses with no upfront licensing fees > and no royalties" - this is totally nonsense! > > I have been trying to buy 1 sample ARM7 ready device from Actel for some > time now, calling them and asking all over again. They claim that ARM > ready PA3 silicon is available, but pricing? As soon as I try to ask the > prices they will start to explain the licensing policy. > > So the best pricing I have gotten is: > > "if you buy 100,000 then for the 'ARM ready' feature the additional price > per FPGA is 1 USD, for smaller quanties the additional pricing has to > 'scaled' down" > > ...I can do the math I think. > > Actel has failed to give any prices at all for any ARM ready silicon > (other than the quote above). > > Smallest PA3 that could be ARM ready is 250 device, where the ARM would > occupy 98,2% meaning its actually fully unuseable. > > Smallest PA3 where ARM use would make sense as of resource utilization is > the 600 device, what is targetterd to be available in Q1... > > ... year 2007 > > So the only PA3 that is ARM ready and available now is PA3 -1000, > available means that it is claimed to be available, 4+ weeks lead time is > to added in any case. > > Not to mention that the website downloadable ARM Core integrator tool is > not FREE but time limited for 45 Days (sale price not known!) and that the > current version does not allow any user IP cores to be added to the ARM > SoC !!! This is promised in next release. That will become available after > the free evaluation time is expired I guess. > > Not to mention that the Actel FPGA optimized ARM core runs at bazing speed > of 25MHz max. > > way to go! > > down > > Antti's 2 cents > > PS Sorry Martin M,.I do say what I think. > >Article: 92271
Okashii wrote: > Hi, I realize that using XST division and mod is only possible when the divisor is power of 2. May I know whether is there any way of getting around this problem? Does the usage of std_numeric solve this problem, or do I have to write my own algorithm to do this? Is there any predefined package somewhere that can do this for me? do you know how a division by a power of two is done in hardware?Article: 92272
Hi! Duane Thanks a lot for your answer. With "instability I mean that modelsim indicate buffer with red transition (undefined) before that normal transition begins, as you explained. I also doesn't understand the exaggerated delay (about 12-15 ns) that signals have before to change state, this delay doesn't depend on the system frequency because output isn't registered. Thans ... bye.Article: 92273
Maybe you can you use xmd. Look at the documentation pdf for more information. I'm a student and I'm also trying to set data on ddr but i'm using powerpc. Can you help with it?Article: 92274
Frank 20 minutes a prom is unusually slow. Without timing it on a board I would say 2 minutes should be more like it for each prom. This behaviour is not normal. I would check how the signals look as you are starting to get a sizeable JTAG chain. I would also check if the output TDO lines of each prom need a pullup resistor and the value if fitted. Some parts do need an external resistor and some don't. I think Virtex-2 devices themselves do need an external pullup. John Adair Enterpoint Ltd. - Soon to be home of Broaddown4. The Ultimate Virtex-4 Development Board. http://www.enterpoint.co.uk "Frank, Frank" <asdf@asdf.com> wrote in message news:43867ba9@news.starhub.net.sg... > My settings are Dell Precision 420, 1GB RAM, Multilinx with COM1, > a JTAG chain comprising five xc18v04, one xc18v02. My FPGA is > virtex 2 - 6M gate. It took me some 20 minutes to program each one > of the PROM device, and it tend to fail in the middle, maybe 3,4,5th > device. Is this normal behavior? > > Thanks in advance. > > >
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z