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"Melanie Nasic" <quinn_the_esquimo@freenet.de> wrote in message news:do95r4$4hh$1@mamenchi.zrz.TU-Berlin.DE... > Hi Pete, > > I want the compression to be lossless and not based on perceptional > irrelevancy reductions. By stating 1 kb I meant 1024 bits and that's just > about half the line data. Your recommendation "1d predictor, non-linear > quantizer and entropy coder" sound interesting. COuld you please elaborate > on that? How is it done? Where can I find some exemplary codes? How can it > be achieved with hardware (VHDL sources?) I think you first need to play around with software and a few sample images. The 1 d predictor means that you predict the next pixel in the sequence by examining pixels on the left. A simple example would be to encode the first pixel on the line, then use that as the prediction for the next pixel. In that way you send only the difference between the predicted value and what the pixel actually is. If you had enough memory to store a line you could use a 2 d predictor, where you predict from pixels to the left and pixels above. Unfortunately, you can't use the non-linear quantizer as it's lossy. I find Khalid Sayood's book "Introduction to Data Compression" quite good. It comes with a link to a bunch of simple C code that has a variety of predictors and entropy coders. You could try it on some sample images, see how good compression you get, then go to hardware when you have something acceptable.Article: 93351
JPEGs are lossy because of the quantization step. You can do it without the quantization step and still notice a significant compression. If you preload your quantization constants and Huffman codes into lookup tables, you can easily process one pixel per clock cycle in a 1500 gate FPGA. I wrote a fully piplelined version that queued up the first eight rows of an incoming image into block ram before starting on the DCTs. It worked great. Ideally you would do DCTs on blocks larger than 8x8, but the advantage to 8x8 is that you can easily do 64 8bit operations in parallel which is nice for the Z-ordering, etc. Bigger squares require bigger chips and external memory, and as soon as you have to go to external memory you lose your pipelining. You don't want to do a dictionary method for an image. In fact, I'm not sure you want to do a dictionary method in FPGA. That sounds scary to me. Use frequency domain (DCT or Wavelet) Z-ordering for photos and use raw RLE for screen shots and similar images.Article: 93352
"John_H" <johnhandwork@mail.com> wrote in message news:auWpf.7$be1.202@news-west.eli.net... > It's sad to see plagiarism. It's ridiculous to have someone make a living > off it. > It's not always entirely the "inventor's" fault. About 30 years ago I was playing around with a Shannon-Rack for audio d/a conversion. My then boss was insistent that I should patent it. The fact that it was called the Shannon rack didn't seem to be enough of a clue that it had been invented by Shannon. Things got quite heated for a few days before he relented.Article: 93353
"Brannon" <brannonking@yahoo.com> wrote in message news:1135097484.768840.95060@g44g2000cwa.googlegroups.com... > JPEGs are lossy because of the quantization step. You can do it without > the quantization step and still notice a significant compression. If > you preload your quantization constants and Huffman codes into lookup > tables, you can easily process one pixel per clock cycle in a 1500 gate > FPGA. I wrote a fully piplelined version that queued up the first eight > rows of an incoming image into block ram before starting on the DCTs. > It worked great. Ideally you would do DCTs on blocks larger than 8x8, > but the advantage to 8x8 is that you can easily do 64 8bit operations > in parallel which is nice for the Z-ordering, etc. Bigger squares > require bigger chips and external memory, and as soon as you have to go > to external memory you lose your pipelining. Is the OP not getting pixels in raster-scan order though? That, and a half-line memory limit means there's not enough storage for a 2-d DCT.Article: 93354
Reza Naima wrote: > - why do you need a clk? Why does anything need a clock? I suggest you take a course on digital electronics design. If you're asking "why do you need a clock," you've got a lot of ground to cover before you start trying to design with Verilog. -aArticle: 93355
Hi John, Thank you for your response. Yes, I did get something new about median filter. I am making living as a senior principle FPGA designer in a small company to do memory controller system and independently have designed several market successful products for my company. My hobby at home is to attack complex algorithms in computer science and electronics that either is currently implemented by software or the current algorithms in circuits that can be further improved, updated to cover more ranges, or get faster speed with less resources. I have a math background. In math, as you know, there are always many theorems that expand some previous narrower theorem. I am trying to do the same things for electronic circuits. One of targets is your paper. In the paper you really did an excellent job and I learned from the technique you have used. After reading your paper on June 13, 2005, I realized that I could and should do better than your paper in a different circuit. I finished it 2 weeks ago. I have read several papers after reading your paper and learn there is a Rank K filter that is similar to median filter and is the Kth largest data to replace the center data. Further more, there is a Stack filter further pushing the median filter method far from normal. In my opinion, developing a new algorithm for electronic algorithm doesn't need more background knowledge than printing and reading several papers describing existing best algorithms about the subjects you are interested. The reason is I will never use it and if I can develop an algorithm or a circuit, or a method, they can be used by others. If there is a chance, file a patent. If not, just publish it for fun. Due to being not in image industry circle, what I have about median filter is what I just read from your paper and other several papers. I will certainly read Khaled Benkrid's paper. I have been writing some patents now, but not for median filter. What I have done with median filter is certainly a material for patent. I will leave the decision whether or not to file a patent 1 year later. Because I am now occupied by other urgent projects at home. I appreciate your several responses very much. For example, you gave me 3 examples on how to handle edge pixels that are to be included in my algorithm without much logic. Your paper excellence is in the following points: 1. Paper is very concise; 2. Key circuit element is shown very clear; 3. Algorithm is very cleaver. Thank you. Weng If you like, send me email to wtxwtx at gmail dot com by deleting space char.Article: 93356
As I think everyone else has said TTL levels between the devices should work ok. The 9500XL parts are 5V tolerant so you can drive them with a 5V signal source. You can get some of these CPLDs from Farnell in the UK with duty issues and they usually take credit cards. Official distributor is Silica in the UK. John Adair Enterpoint Ltd. - Home of Raggedstone1. The low cost Spartan3 Development Board. http://www.enterpoint.co.uk "Philip Pemberton" <philpem@despammed.com> wrote in message news:d0ebdddb4d.philpem@dsl.pipex.com... > Hi, > I've just finished tweaking all the Verilog code for my Atari DVG > reimplementation. Problem is, I've hit the macrocell limit for the XC95216 > chip I was using, and I can't really justify using two 95216es when the > second one is only going to have 50 used macrocells on it. I've got some > 72MC > chips, but they're XC9500XL series (i.e. XC9572XL-10 in PC44 package). > > Does anyone know if an XC9500XL at 3.3V and an XC9500 at 5V will happily > communicate with each other without level converter ICs between them, or > would I be better off just adding another 95216 and some extra logic to > fill > the chip up? > > Another question - does anyone know of a (preferably UK or European) > components distributor that carries XC95288 or XC95288XL chips in small > quantities? Any leaded package is fine - QFP, LQFP, PQFP, whatever, as > long > as it has metal leads along the edges (i.e. not CSP or BGA). > I'm also looking for Coolrunner chips, same rules - leaded packages only, > small (i.e. testing samples) quantities. > > I've found loads of companies that'll sell me 20 or 30 of the things, but > I > only want two or three. I could get them from Digikey, but then I get to > deal > with UPS's "Customs brokerage fees" and such... > > Thanks. > -- > Phil. | Acorn RiscPC600 SA220 64MB+6GB > 100baseT > philpem@philpem.me.uk | Athlon64 3200+ A8VDeluxe R2 > 512MB+100GB > http://www.philpem.me.uk/ | Panasonic CF-25 Mk.2 Toughbook > No software patents! <http://www.eff.org/> / > <http://www.ffii.org/> > ... Neither Borrower Or Lender Be; routinely ignored by Congress.Article: 93357
Hello everyone. Does anyone know where I can find information about the place and route algorithms used for FPGAs, and what kind of work has been done or is being done to accelerate these algorithms. Books and/or links to web-sites will be greatly appreciated. Regards, Marco.Article: 93358
To compile and run applications on top of Linux for Virtex-II Pro and Virtex-4 based boards you have two options: 1. Cross-compile the application on your host. For that you need a cross-development environment which you probably already have since you compiled the kernel. 2. Natively use the PPC in the FPGA to compile your target application from within Linux. Personally, I believe that the second option is the easier (but slower) way to go. - Peter Eric wrote: > Hi All, > > I have Linux up running for PPC on the virtex-ii pro board (XUPV2P). > I'm new to embedded system design. Anyhow, I'm hoping to run software > applications on the board. I'm familiar with adding software to the > standalone system using EDK. But with an OS on it, what modifications > do I need to make before the executables (.elf) can be run? Is there > any reference? Thanks plenty. > > -Eric >Article: 93359
"rmanand" <murugs_india@yahoo.com> schrieb im Newsbeitrag news:r-udneWS_pGnJzreRVn_vQ@giganews.com... > Hi > > Thanks for your reply. > > I am using CABLE parallel III . Actually two device is in the > chain.Both are not detected.So checking the First device. > > I have set the control bit 101(m2,m1,m0).I have tired 1 1 1 combination > also .But no use. > > I have already used 1.2K but Nochange .So i came down to 220 ohm > resisitor.I will try to use 2k > > I have checked TCK and TMS .TDI levels .It is okay.But TDO is logic > high always.Now the cable speed is 200khz only > > Expecting your reply > > Thanks in advance > you are out of luck sitting on mal functioning board and/or FPGA what you describe is 'broken' JTAG chain, this is the point where you can not do any further testing until you get something non stuck 1 out of the TDO. unless that works the JTAG testing can not be done. the m2m1m0 do not matter. virtually nothing matters, as long as the JTAG pins are connected to correct pads and FPGA is powered up correctly, then you should see something. just use impact debug mode, set 1111 to IR scan and click scan IR until you then at least one 0 in the response you are out of luck. check schematics, PCB power etc.. do it again do it again until you get the jtag scan working if you have 2 devices in the chain you can not check the JTAG unless both of them work so check TDO of the first device first if that toggles and the TDO of the second device not then error is with first. but you can not detect 1 out of 2, it will be either 2 or nothing, in your case nothing AnttiArticle: 93360
JustJohn wrote:
> ... Weng and I have been having this extended chat
> on median filters, and because it seems
> that Weng is looking to develop something patentable, I had a look-see
> over at USPTO. I find there is a recently (04, July) granted patent, US
> 6760737, which seems to list my median circuit exactly.
> ... but on the other hand
> mildly annoyed to see someone else's name there, and wishing I'd made
> the filing myself. How would you react?
I would be annoyed as well, but I expect I would let it go.
Thanks for the posting. I have often found it
curious that there are so many posters
with very specific questions but no fundamental
knowledge in the area. Now we know one reason why.
Online patent phishing sweatshops.
> I would think the patent is useless, because I'd already shown the
> method, but am wondering if the state of law is such that Lucent could
> come after me for using my own circuit.
It might be worth an appointment
with an attorney to determine your best move,
but I think the risk is low.
Large corporations collect patents to defend
the cash-cows of the moment from other corporations.
> Corrolary question...Do most patents just make money for lawyers and
> add to the writer's resumes? Or do a majority have actual worth beyond
> that?
I think patents are a type of insurance policy
for large corporations. Very few lawyers or engineers
have become rich or famous because of a patent.
A patent citation on a resume doesn't look bad,
but a list of publications looks even better to me.
-- Mike Treseler
Article: 93361Mike Treseler wrote: > > I think patents are a type of insurance policy > for large corporations. Very few lawyers or engineers > have become rich or famous because of a patent. > A patent citation on a resume doesn't look bad, > but a list of publications looks even better to me. > > > -- Mike Treseler Mike, I agree wholeheartedly. Generally speaking, a patent is only as good as your resources available to defend it. For an individual, the cost sunk into obtaining a patent will likely never be recovered unless it has bulletproof claims, is important enough to be essential and interesting to a company that might buy it, and you've got enough financial wherewithall to defend your patent if someone does infringe it. I also agree, publications look better on a Resume than patents. Both are attractive, but the publications carry more weight with me.Article: 93362
Marco, I am sure that you will not find anything beyond very basic tutorial information. These are the "crown jewels" of any FPGA company, and these jewels are well guarded, but also polished daily. The quality of these tools determines the success of our companies, and each of us wants to be at leats a step ahead of the other company. BTW, the continuous investment by companies like Xilinx and Altera (to name just the two biggest) is enormous, and it is unlikely that an individual engineer can provide significant improvements. Unless you are a genius and addressthe problem in a very unconventioanl way. Peter AlfkeArticle: 93363
rmanand wrote: > Hi > > Thanks for your reply. > > I am using CABLE parallel III . Actually two device is in the > chain.Both are not detected.So checking the First device. Do you have a pullup resistor on the TDI/TDO chain between the FPGAs? It is needed, apparently only on the V2Pro devices (I use 150ohms). > ... >>> >>> Hi friends >>> >>> The Virtex II pro (XC2VP100) device is not Configuring through >>> Impact7.1e >>> >>> When i try to check with CRO what is happeing at the BOUNDARY >>> SCAN SIGNALS TDO ,TDI,TCK ,TMS >>> >>> I found TDI,TMS,TDI signals are okay .THE TDO is always stuck at >>> one(pulled up by 220 ohm resisitor preferred by xilinix). >>> >>> The prog Pin is pulled up to 3.3V through 4.7k.The Init pin is >>> pulled up to 3.3v through 4.7k.These all are xilinx >>> reccomendation. >>> >>> I could not understand what will be reason for the TDO is always >>> high at one and how to solve the problem. >>> >>> >>> The impact is always throughing Impact -583 error. Expeting your >>> valuabe repliesArticle: 93364
I think John answered the question by stating that the clock is useful for syncronization and debugging, but ultimatly it seems as if I am correct in my assertion that a clock is not explicitly required. Digital electronics design seems a bit vague - can you be a bit more specific? There are verilog-specific courses offered in my program (I'm in graduate school) - but I think it's an overkill for my needs. Alas, the current project I'm working can't wait for me to take more classes. Either this is implemented in a CPLD or else I'll have to use discrete components. I'm going to follow some of Art's suggestions and see how far I can get. I've also looked at some of the sample designs on opencores, and they seem a bit too complex to learn from. I'll look around for some other simpler sample code. One of the other problems with looking at sample code is that a lot of it is minimally commented, and it's very hard to figure out why people are implementing someting in one way vs. another way. With regards to a wait(), I figured the compiler/synthesizer would generate some sort of clock/counter with some sort of comparator to trigger the event. I was hoping that the synthesizers were a bit smarter than they seem to be. Thanks, RezaArticle: 93365
Oh, one other question regarding clocks. By not using one, wouldn't the device consume significantly lower power? I still don't see an advantage of having a clock in this design. Thnx, rezaArticle: 93366
marco wrote: > Does anyone know where I can find information about the place and route > algorithms used for FPGAs, and what kind of work has been done or is > being done to accelerate these algorithms. http://groups.google.com/groups?q=place+route+algorithm+fpgaArticle: 93367
Reza Naima wrote:
> I think John answered the question by stating that the clock is useful
> for syncronization and debugging, but ultimatly it seems as if I am
> correct in my assertion that a clock is not explicitly required.
True if your design is 100% combinational
without a single shifter or counter.
> Alas, the current project I'm working can't wait for me to take more
> classes. Either this is implemented in a CPLD or else I'll have to use
> discrete components.
In that case, consider schematic capture to enter your design:
http://www.eecg.toronto.edu/~zvonko/AppendixB_quartus.pdf
> With regards to a wait(), I figured the compiler/synthesizer would
> generate some sort of clock/counter with some sort of comparator to
> trigger the event. I was hoping that the synthesizers were a bit
> smarter than they seem to be.
That seems to be a common expectation.
Unfortunately it is difficult to describe
some sort of clock/counter without a clock input.
-- Mike Treseler
Article: 93368Ray Andraka wrote: > Mike Treseler wrote: > > > > > > I think patents are a type of insurance policy > > for large corporations. Very few lawyers or engineers > > have become rich or famous because of a patent. > > A patent citation on a resume doesn't look bad, > > but a list of publications looks even better to me. > > > > > > -- Mike Treseler > > Mike, I agree wholeheartedly. Generally speaking, a patent is only as > good as your resources available to defend it. For an individual, the > cost sunk into obtaining a patent will likely never be recovered unless > it has bulletproof claims, is important enough to be essential and > interesting to a company that might buy it, and you've got enough > financial wherewithall to defend your patent if someone does infringe it. > > I also agree, publications look better on a Resume than patents. Both > are attractive, but the publications carry more weight with me. yeh, seems to me its is usually somthing like; BigCompanyA has alot of (more or less) valid patents so that when BigCompanyB claim they infringe on one of their patents, they can counter sue claiming they infringe on one of their patents, eventually they reach a settlement and agree to go after everyone else instead. -LasseArticle: 93369
johnp wrote: > John - > > You mention the patent describes the Median Filter, but does it > actually claim it in the claims section? A patent can describe > anything, but the last section of the patent (the claims) is where > the patent actually claims what the invention is. If it isn't in the > claims, it is not being patented. > > > John Providenza Having had a little more time, I've read through the patent in excruciating detail now, and it turns out that despite being identical in the first stages and the last stage, Mr. Jiang (umm, Dr. Jiang?) does something very slightly different in the middle. Instead of using 4 comparisons to sort out guaranteed non-median values, he uses a control vector based on ths second stage sort of the first stage medians. This control vector presumably configures 3:1 muxes (he glosses over that, using only the word "locate" in his diagram), and allows using only 2 comparisons to my 4. So he's outdone my circuit! (at least in terms of total comparisons; the two 3:1 muxes actually use more FPGA LUT fabric than the two comparisons, because the carry-logic is free in this context). I humbly apologise to Hong Jiang for any untoward remarks. Regards all, Just JohnArticle: 93370
Eric, while it might or might not work I'd rather not do that. The EDK and Linux compilers for the PPC405 use different programming models. - Peter Eric wrote: >Thanks for the response, Peter. I have thought about those methods as >well. But, is it possible to use the compiler in EDK for software >applications running on the top of Linux? Thanks! > >-Eric > > >Peter Ryser wrote: > > >>To compile and run applications on top of Linux for Virtex-II Pro and >>Virtex-4 based boards you have two options: >> >>1. Cross-compile the application on your host. For that you need a >>cross-development environment which you probably already have since you >>compiled the kernel. >>2. Natively use the PPC in the FPGA to compile your target application >>from within Linux. >> >>Personally, I believe that the second option is the easier (but slower) >>way to go. >> >>- Peter >> >> >>Eric wrote: >> >> >>>Hi All, >>> >>>I have Linux up running for PPC on the virtex-ii pro board (XUPV2P). >>>I'm new to embedded system design. Anyhow, I'm hoping to run software >>>applications on the board. I'm familiar with adding software to the >>>standalone system using EDK. But with an OS on it, what modifications >>>do I need to make before the executables (.elf) can be run? Is there >>>any reference? Thanks plenty. >>> >>>-Eric >>> >>> >>> > > > > >Article: 93371
JustJohn wrote: >Ah, this is interesting. Weng and I have been having this extended chat >on median filters (hope it did not bore anyone), and because it seems >that Weng is looking to develop something patentable, I had a look-see >over at USPTO. I find there is a recently (04, July) granted patent, US >6760737, which seems after wading through all the pat-speak >gobbledy-gook (which is mostly in the order of a proof (that can be >done a bit simpler)), to list my median circuit exactly. One paragraph >(col 4, lines 47-50) even describes the pipelining, not verbatim from >the XCell note, but close enough. > >So has anyone else here had this happen? What was your reaction? On the >one hand, I'm pleased to see that I can generate patentable stuff (5 >years earlier than filing date on this one), but on the other hand >mildly annoyed to see someone else's name there, and wishing I'd made >the filing myself. How would you react? > >I would think the patent is useless, because I'd already shown the >method, but am wondering if the state of law is such that Lucent could >come after me for using my own circuit. > > No. You can destroy their patent by showing where you published it earlier. Of course, they COULD, actually sue you for using their (invalid) patent, but your defense should be so easy, it would be a bad idea for them to do so. >Corrolary question...Do most patents just make money for lawyers and >add to the writer's resumes? Or do a majority have actual worth beyond >that? > > Some patents are worth billions of $. See some of the patent wrangling and licensing between Intel and some of their competitors. I think TI has had some big patent cases in the past couple years, too. There was a big Xilinx patent that was finally decided this year, IIRC. The kind of thing you describe is actually quite common, as in many cases the earlier work may not be clearly published. If you have an XCell applications note available on the web, or on print form, that sounds like sufficiently clear publication to me. If somebody with deep pockets doesn't come along to infringe your patent or offer to license it, then you will never know whether your patent is valuable or not! If a billion $ corporation infringes your patent, and you are successful in suing them for that, then it could be worth a LOT of dough. But, the guys who invented the intermitent windshield wiper and the capillary blood sample tube both went to their graves after 20+ years of litlgation, only to win the cases AFTER they died! I don't recommend any individual waste their time patenting anything unless it is a blockbuster, and they have the pockets to defend the thing against all comers. JonArticle: 93372
Jon Elson wrote: > > > JustJohn wrote: > >> Ah, this is interesting. Weng and I have been having this extended chat >> on median filters (hope it did not bore anyone), and because it seems >> that Weng is looking to develop something patentable, I had a look-see >> over at USPTO. I find there is a recently (04, July) granted patent, US >> 6760737, which seems after wading through all the pat-speak >> gobbledy-gook (which is mostly in the order of a proof (that can be >> done a bit simpler)), to list my median circuit exactly. One paragraph >> (col 4, lines 47-50) even describes the pipelining, not verbatim from >> the XCell note, but close enough. >> >> So has anyone else here had this happen? What was your reaction? On the >> one hand, I'm pleased to see that I can generate patentable stuff (5 >> years earlier than filing date on this one), but on the other hand >> mildly annoyed to see someone else's name there, and wishing I'd made >> the filing myself. How would you react? >> >> I would think the patent is useless, because I'd already shown the >> method, but am wondering if the state of law is such that Lucent could >> come after me for using my own circuit. >> >> > No. You can destroy their patent by showing where you published it > earlier. Of course, they COULD, actually sue you for using their (invalid) > patent, but your defense should be so easy, it would be a bad idea for > them to > do so. There are too many could and should's here, when dealing with lawyers :) A good recent (and still alive, AFAIK) example of the first class sillyness of (too many) patents, and the decisions to litigate, is Microchip (who should know better) suing Zilog (who are quite small) for making Microcontrollers with fewer IO pins, than internal BUS width. A slew of questions arise out of this, none of which has anything to do with innovation. What next - cars with fewer doors than cylinders patented ? A sea of prior art exists, going way, way back to the Intel 4004, plus patents are supposed to not be obvious to onw skilled in the art. Maybe tiny Zilog really does have Microchip scared - but I would have thought Microchip could safely ignore Zilog, and find many better areas for their energies and funds ? > But, the guys who invented the intermitent windshield wiper > and the capillary blood sample tube both went to their graves after 20+ > years of litlgation, only to win the cases AFTER they died! Examples like these serve to confirm that patents are simply feeding troughs for lawyers. -jgArticle: 93373
Hi all, My question to u all is about the Xilinix Modular design.......any1 working on dynamically reconfigurable FPGAs?????...plz lemme know....i wanna know how we could use this for partial and dynamic reconfiguration.Article: 93374
Hello everyone. If you are interested in new ways to develop FPGA based logic, where signals and data can be viewed and modified in real time while the circuit is running, you may like to take a look at our new product called Hevday Interactive Logic which is currently in beta. The main features of Hevday Interactive Logic include: - The ability to view and modify signals and data directly on schematics in an entire multi level design while the circuit is running, paused or while stepping the circuit one clock at a time. - Digital waveform style display of Data vs. Clock Cycles. - Long time scale waveform display of signals over periods of continuous operation up to 7 days. - Setting of breakpoints for debugging circuit state after predefined conditions. - A novel approach for determining maximum allowable clock frequency, based on testing actual circuit functionality. Hevday Interactive Logic has been designed for prototyping and small volume applications. For more information, please visit http://www.hevday.com All feedback welcome. Regards, Andrew Ward.
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