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Steven, Please have them email me directly, and I will put them in touch with the right person. We definitely enjoy having talented faculty spend time here (or in our new 'EU research centre' in Dublin). Austin Steven Derrien wrote: > Austin Lesea wrote˛ : > >> >> If you are associated with a school, university, or other research lab >> and wish to join us in research > > > Hi, > > I had a glance to the XUP webpage, but it mostly focus on teaching > resources. > > Let's say "I have a friend of mine" ;) who is an academic considering > going for a sabbatical, and who would be *very* interested to join > Xilinx Labs during that time, should I also go through this channel ? > > Thanks in advance, > > Steven > >> , obtain hardware or software; please contact: >> >> http://www.xilinx.com/univ/ >> >> (xup@xilinx.com) >> >> Thank you for considering Xilinx, >> >> Austin >>Article: 92776
Ray, Thanks. There is another solution we are also looking after for the async case which is even simpler(?) with no performance hit, which looks promising. I believe all such solutions will be combined into one resource. Jim and I have been discussing the FIFO, as well as other issues recently. Austin Ray Andraka wrote: > Austin, > > FWIW, there is fairly low complexity work-around for the FIFOs that can > be made to come at least close to the FIFO16 maximum performance. It > involves operating the FIFO16 as a synchronous FIFO with one side > clocked by the rising edge and one side with the falling edge of the > same clock. This is cascaded with a small coregen async fifo. The > small (15 deep) async FIFO can be made to run at the max FIFO16 speed > with some minor modifications and/or floorplanning around the flag > counters. This looks like it will completely avoid the potential flag > issues in the FIFO16 for both async and sync operation. > > For synchronous use, the FIFO16 can be clocked by opposite edges of the > same clock, which is fine for lower performance designs. For high speed > designs, either use the above async fifo clocked on the FIFO16 side by > the falling edge of the fifo clock, or use a double rank register with > the first rank clocked by the rising edge, passing data to the second > rank which is clocked by the falling edge, which then passes the data > onto the write side of the fifo16. Placing the register ranks in > adjacent columns will meet the max timing of the fifo16 without the hit > you'd normally get by running one side on the negative clock. > > I passed this solution on to your applications folks through Jim > Simkins. Hopefully it will make it into an app-note or answer record as > a work-around. >Article: 92777
"Simon Peacock" <simon$actrix.co.nz> wrote in message news:43952591@news2.actrix.gen.nz... > Of course, the invention of time travel will make all patents null and > void > :-) Including the patent on the time travel machine?!! Cheers, Syms.Article: 92778
Hi, I was just wondering some technicalities about a board. Ive got the XUP virtex-II pro from digilent and I believe it was designed by the XRL. Well I was wondering what kind of CAD (schematic capture + pcb layout) software does the team used. And also, out of curiosity, what PCB manufacturer do they use and the number of layers involved. A friend of mine thinks it's around 12. Which I doubt. So to make things clear, I am asking the experts here. Thanks for the tip, but im impressed by the job and I wanna know what it takes to do that. JA Steven Derrien wrote: > porterboy76@yahoo.com a =E9crit : > > glen herrmannsfeldt wrote: > > > >>porterboy76@yahoo.com wrote: > >> > >> > >>>I am looking for the homepage of Xilinx Research Labs, but Google is > >>>not helping me. Does anybody know if they even have a homepage. > > Hi, > > They used to have one (well, Satnam Singh had his page until he left > Xilinx). > > >>> I'd like to know what type of research they do at Xilinx, whether it = is all > >>>at the solid state and IC level, or whether they undertake higher level > >>>algorithmic research as well. > > From what I know (i.e. academic perspective) Xilinx folks mostly focus > on higher level problems (system level design, hardware compilation, > runtime reconfiguration, etc.). > > If you want to have more details have a look to some FPGA related > academic conference proceedings such as FPL or FCCM, you will > probably find some papers by people from Xilinx. > > Besides, I am sure that Peter Alfke and Austin Lesea will be glad to > answer your questions. > > > >> > >>Post to comp.arch.fpga and ask there. > >> > >>-- glen > >=20 > >Article: 92779
Which distrib do you use ? In Fedora Core 4 it works fine. I had a problem trying the first time to install it from an NFS share. But uncompressing the files to a LOCAL location solved the problem.Article: 92780
Marco wrote: > Hi, I need a link to a free VHDL SPI core to deal with a temp sensor > in serial mode. Thanks for your help. Marco Any reason why you can't use verilog? Regards, MarkArticle: 92781
Marco wrote: > Hi, I need a link to a free VHDL SPI core to deal with a temp sensor in > serial mode. > Thanks for your help. > Marco SPI is little more than a shift register ... not at all that hard to code. -aArticle: 92782
Antti Lukats wrote: > ISE 8.1 release was planned for mid nov, now its mid december soon, I wonder > if it is known how much more the ISE 8.1 release is delaying? Xilinx is > advertising ISE webcast on Dec 14, I wonder if that will only cover soon to > be obsoleted 7.1 or be focused on 8.1? > > Actually I am more waiting for the EDK 8.1 in the hope DDR2 support is > added, but as EDK 8.1 release was projected 4 weeks after ISE 8.1 release I > guess the EDK 8.1 actuall release date is slipping also :( most likely into > 2006? I suppose the better question is, "when will the first service pack be available?" -aArticle: 92783
> > I suppose the better question is, "when will the first service pack be > available?" > Andy, It's a brave (or possibly desperate) man who dives in before SP3! ;-) Cheers, Syms.Article: 92784
Porterboy76, Glen, and Others, I work in Xilinx Research for our CTO and would very much like to hear of any external research or sabbatical proposals you may have. You can send them directly to me and I'll follow up with you outside of this news group. Incidently, I read this newsgroup infrequently. Regards, Stephen Ps we don't have an external web page, yet, but we are evaluating options, so please send us suggestions if there's something specific you'd like to see. porterboy76@yahoo.com wrote: > glen herrmannsfeldt wrote: > > porterboy76@yahoo.com wrote: > > > > > I am looking for the homepage of Xilinx Research Labs, but Google is > > > not helping me. Does anybody know if they even have a homepage. I'd > > > like to know what type of research they do at Xilinx, whether it is all > > > at the solid state and IC level, or whether they undertake higher level > > > algorithmic research as well. > > > > Post to comp.arch.fpga and ask there. > > > > -- glenArticle: 92785
Andy Peters wrote: > Antti Lukats wrote: > >>ISE 8.1 release was planned for mid nov, now its mid december soon, I wonder >>if it is known how much more the ISE 8.1 release is delaying? Xilinx is >>advertising ISE webcast on Dec 14, I wonder if that will only cover soon to >>be obsoleted 7.1 or be focused on 8.1? >> >>Actually I am more waiting for the EDK 8.1 in the hope DDR2 support is >>added, but as EDK 8.1 release was projected 4 weeks after ISE 8.1 release I >>guess the EDK 8.1 actuall release date is slipping also :( most likely into >>2006? > > > I suppose the better question is, "when will the first service pack be > available?" and an even better one.... "When will it be safe to unleash on legacy designs ? " -jgArticle: 92786
Ray - I've got to agree with you that finding stuff in the answer data base is hit-n-miss at best. I use XIlinx parts in my designs and I like the parts, but, the support from the web site leaves a lot to be desired. Thank goodness Peter and Austin pay attention to this group! I often think that web masters should be forced to sit with users for a while so they end up understanding how slow and poor the user experience is. My most recent frustration was trying to find information on a DCM bug requiring the bitgen centered option. Good luck finding info on it. John Providenza.Article: 92787
Thanks very much for your replies and suggestions. At this moment, I do not have the development kit with me, so I cannot continue testing of my design on the FPGA. Thus, any changes I make cannot be programmed and checked. When I get the board back from my colleagues, I'll try out your suggestions at once. Ryan, I do understand what you mean. That's why I thought it was baffling that the behavioural model was transferred onto the FPGA, because I ran Translate, MAP and PAR. I simulated all verilog models (behavioural, post-translate, post-map and post-PAR). The post-translate, post-map and post-PAR simulations results were the same, but they differ from the behavioural model. Initially, when I tested the outputs using a digital oscilloscope, the results I got seemed to match the behavioural model, and not the post-translate, model or PAR. John, To answer your questions, (1) I'm not sure if I understood your first question but all verilog models were simulation output from ISE. The behavioural model follows the RTL which I wrote. (2) Yes, my model has signal relationsips defined by clock edges. The models synthesised OK. There were several warnings, but the severity is very low. (3) It read an NGC file. I'm afraid I do not know what this means, because I'm very new at FPGAs and hardware design. Please see below for the translation report: --------------- Command Line: ngdbuild -intstyle ise -dd c:\rtl_fpga/_ngo -uc test.ucf -p xc2s300e-fg456-6 test.ngc test.ngd Reading NGO file 'C:/rtl_fpga/test.ngc' ... Applying constraints in "test.ucf" to the design... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 53236 kilobytes Writing NGD file "test.ngd" ... Writing NGDBUILD log file "test.bld"... ----------------- I did output the internal clocks to pins to monitor the results. The internal clocks and signals work OK, but the outputs were not as expected. Unfortunately, I encountered another problem. Like I mentioned before, I currently do not have the FPGA development board with me, so I can't continue to do any checking of signals. I made some changes to the design in RTL, and after synthesis, translate, map and PAR, I ran a simulation on all the verilog models. The behavioural model worked as expected. However, the post-translate, map and PAR models were wrong. There were no errors nor timing violations during synthesis. There were also no errors in design translate, map and PAR. Could the problem be in my pin assignment? There were no errors there though. I didn't use the Xilinx PACE, but LOCed my input/output pins instead. Any suggestions? Please feel free to ask for any more information, as I do not know what to add, as I did not encounter any errors. Again, please forgive the triviality of the questions as I am very new to this. Thanks very much in advance for all your help. Appreciated :) ChloeArticle: 92788
><jaxato@gmail.com> schrieb im Newsbeitrag >news:1133913172.512557.30990@o13g2000cwo.googlegroups.com... >Hi, I was just wondering some technicalities about a board. > >Ive got the XUP virtex-II pro from digilent and I believe it was >designed by the XRL. >Well I was wondering what kind of CAD (schematic capture + pcb layout) >software does the team used. And also, out of curiosity, what PCB >manufacturer do they use and the number of layers involved. A friend of >mine thinks it's around 12. Which I doubt. So to make things clear, I >am asking the experts here. > >Thanks for the tip, but im impressed by the job and I wanna know what >it takes to do that. > >JA if you want to 'see' the technical then take a look at ML300 on Xilinx website, I think there are gerber files provided for it, you can use some gerberviewer to look at the layers :) but ML300 is designed by SEG not XRL AnttiArticle: 92789
looking for tutorial program for FPGA programmingArticle: 92790
Oh, by the way, I did get this in my Post-translate Simulation Model report: Command Line: netgen -intstyle ise -sdf_anno true -w -ofmt verilog -sim test.ngd test_translate.v WARNING:NetListWriters:550 - Ignoring non-applicable option -sdf_anno for input file with 'ngd' extension. Reading design 'test.ngd' ... Can anyone tell me if that's wrong? Thanks in advance.Article: 92791
Kolja> A very abstract answer: > I a single layer network every input connects to N other pins. > These everage wire length for each input is at least proportional to > (n*sqrt(n)), same for the capacitance. > Therefor the bandwidth is reciprocal to n^3, the latency is proportional > to n^3. > > The other extreme is a tree of 2-way switches. Each path has log(n) > switches. Each connection has 2 pins. The area is n^2 (n*log(n) is only > true for unbounded number of rounting layers). The average wire length > is n. The bandwidth is constant, the latency is proportional to log(n). > > Of course the latency of the switch will have a larger constant value > than the wire. But the difference between log and n^3 is extreme, so the > break even point will be for rather small n. > > Kolja Sulimma I see some more issues. Some switches are entirely on a single chip. I've heard of folks implementing these as multi-layer switches. Perhaps if something specific about the switching pattern is known, that may make sense. (e.g. it's a 64-bit shifter, implemented as 3 layers of 4-way muxes). Or perhaps when latency does not matter. But when latency matters, a full crossbar, implemented on a single chip, seems quite reasonable to me, even for e.g. 64 16-bit ports. My reasoning is that it's not the 64 64-way 16bit muxes that's going to chew up the area, it's the buffering and scheduling. And a full crossbar should have fewer scheduling issues than a multi-layer switch. Once your switch is distributed across more than one chip, you have a very different problem. The wires between chips cost so much more than the wires on chip ($0.02 each versus $0.00001 each) that you can't afford to stall a board wire due to contention for a chip wire. I'm currently quite enamoured with the load-balanced switch idea. (Previously I was enamoured with the Tiny Tera design, both have come from Nick McKeown's group at Stanford.) The nice thing about a load-balanced switch is that the switch fabric itself can be a shifter, or pair of shifters, which is a *lot* easier to implement. I think a load balanced switch implemented on a single chip is an interesting idea, that may have already been implemented as part of a shared memory switch.Article: 92792
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:43964263$1@clear.net.nz... > Andy Peters wrote: >> Antti Lukats wrote: >> >>>ISE 8.1 release was planned for mid nov, now its mid december soon, I >>>wonder >>>if it is known how much more the ISE 8.1 release is delaying? Xilinx is >>>advertising ISE webcast on Dec 14, I wonder if that will only cover soon >>>to >>>be obsoleted 7.1 or be focused on 8.1? >>> >>>Actually I am more waiting for the EDK 8.1 in the hope DDR2 support is >>>added, but as EDK 8.1 release was projected 4 weeks after ISE 8.1 release >>>I >>>guess the EDK 8.1 actuall release date is slipping also :( most likely >>>into >>>2006? >> >> >> I suppose the better question is, "when will the first service pack be >> available?" > > and an even better one.... "When will it be safe to unleash on legacy > designs ? " > > -jg > Well Xilinx stopped working on 7.1 meaning they will never fix 7.1 so bugs present in 7.1 SP4 will remain unfixed. So there is no option as to be brave and go for 8.1 some day. The sooner the 8.1 is made available for testing the sooner it will come useable and those not so brave will also be able to use it. AnttiArticle: 92793
Simon Peacock wrote: > Yews and no.. it could be argued that books are by design, designed to be > read. Take a look at the copyright message for most software. "cannot be > disassembled for any purpose" is a very common phrase > > "In order to protect them you may not decompile, reverse engineer, > disassemble, or otherwise reduce the Software to a human-perceivable form." > That sort of phrase is common in EULAs, not copyright messages. And in most countries, it is legally unenforceable (IANAL, of course). In fact, you'd have a great deal of trouble finding a software EULA that is entirely legally enforceable in any jurisdiction. Reverse engineering is a perfectly legal technique for certain purposes (interoperability with other software is a prime example - look at samba), and disassembly, etc., is part of that. Of course, directly copying an existing system is generally illegal, whether by reverse engineering or otherwise. > This is from the Xilinx EULA for the development tools. I don't have > core-generator handy, but as you can see, they don't want you to view in any > shape or form their software. Altera might be different but that is because > their tools were built with or include GNU > > You can of course copy directly from a book, I think anyone would be hard > pressed to stop someone or even to prove they had exclusive rights to > something found in print, you would only have to find it in a different book > printed before the one in question to automatically invalidate any clams. > > Of course, the invention of time travel will make all patents null and void > :-) > > Simon >Article: 92794
Hallo, does anyone has connected 2 FPGA? Which kind of connection have used? Many Thanks MarcoArticle: 92795
Hi Jim, Thanks for your suggestions. I tried inverting the clock and it now works !Article: 92796
"Marco" <marcotoschi@nospam.it> schrieb im Newsbeitrag news:dn643r$hbo$1@nnrp.ngi.it... > Hallo, > does anyone has connected 2 FPGA? > Which kind of connection have used? > > Many Thanks > Marco FPGAs are often connected to each other by different means. your question can have no reasonable answers as you are the only person who know WHY you want to connect the FPGA, and the answer to that question is needed in order to decide HOW. It all depends why and what you are going to achive. AnttiArticle: 92797
you can try http://www.opencores.org/projects.cgi/web/spi/overviewArticle: 92798
Hi all, I am needed to talk with a microcontroller through an I2C interface from my FPGA. I dont want to write a code for it as well not use an opensource core. This is partly due to space constraints and testing. Speed and cost are not constraints. So I was hoping to find a chip which would sandwich between the FPGA and I2C interface. Searched on the net but could not find any. If anyone has suggestions please let me know. Thank you regards vasudev srinivasanArticle: 92799
<svasus@gmail.com> schrieb im Newsbeitrag news:1133949644.536667.201480@z14g2000cwz.googlegroups.com... > Hi all, > > I am needed to talk with a microcontroller through an I2C interface > from my FPGA. I dont want to write a code for it as well not use an > opensource core. This is partly due to space constraints and testing. > Speed and cost are not constraints. > So I was hoping to find a chip which would sandwich between the FPGA > and I2C interface. > Searched on the net but could not find any. If anyone has suggestions > please let me know. > > Thank you > > regards > vasudev srinivasan > there is no such thing. most likely the overhead to talk to the external I2C controller chip is larger than implementing it in the FPGA if there is some softcore processor in the FPGA you may implement the I2C as software bit bang on GPIO port that consumes very little overhead or if you need external thing, take any small MCU and use it as custom I2C controller, C8051F305 is packaged in 3 by 3mm package and costs about 2USD, there are plenty of other possibilites as well Antti
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