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Slight correction in the above example: "If we represent -4 with a 3-bit signed number and 7 with a three bit signed number.." should be: "If we represent -4 with a 3-bit signed number and 7 with a three bit unsigned number.."Article: 92726
Weng Tianxiang schrieb: > I found that in Xilinx patents, all lookup table equations are > described in AND/OR/Multiplexer circuits in its claims. Describing a > logic connection for a lookup table in claims is much more complex in > English than presenting an equivalent logic equation. > > For example, a lookup table has the equation: > Out <= (A*B) + (C*D); > It is much more concise and simpler than describing the circuit in > AND/OR gate circuits. After all it is a LUT, so why not describe it as a LUT? List the output for all 16 input combinations. It is not more conscise but it is simpler than doing it in english. Kolja SulimmaArticle: 92727
Fred, OK, so I used an older version, it also happens to be online, and it also has a misprint for the figure number. Got that straight now. I don't really know the answer to your questions that you ask below (disregarding that you figured out the answer to your first question yourself). But read on: -snip- > However, this still doesn't explain what is the difference between the > following two cases: > > (See Table 2 in > http://www.xilinx.com/ipcenter/catalog/logicore/docs/addsub.pdf to > understand what I'm talking about.) > > 1. > Operand A: Unsigned, > Operand B: Signed or by input pin (2nd row), > when the input pin is set so that the operand B is signed > > and > > 2. > Operand A: Signed or by input pin, > Operand B: Signed or by input pin, (last row) > when the input pins denote that the operand A is unsigned and operand B > is signed > > In both cases 1 and 2 above the operands are exactly the same, No, one case is signed/signed (2.), and the other is unsigned/signed (1.). but the > availability of the overflow flag and the widths of the result are > different. In particular, I cannot get the result to be of the width > P=Q+2 in case 2. > WHY????????????????????????????????????????? > > Also, in table 2, why is overflow not available if I select the width > of the output to be P=Q+1???? I'll let someone else puzzle this out, but it also may be because that is the way the core is written (it is just what it does). And it also seems logical that if an overflow can not occur, then no overflow bit is required (the output has enough bits). Anyone? AustinArticle: 92728
On Mon, 05 Dec 2005 22:22:54 +0000, c d saunter wrote: > This may or may not work - many lab power supplies and some bricks > conenct the 0V from the DC side to the mains earth, so doing this > with two such supplies will cause funny noises, bad smells and possibly > worse as the magic smoke escapes. > > If you're not sure, don't try ths aproach! The bricks I've used have always isolation, but I live a relatively sheltered life. Where have you seen them, mainly? -- Regards, Bob Monsen "You told me, 'God made the World.'" "No, no!" Harshaw said hastily. "I told you that, while all these many religions said many things, most of them said, 'God made the World.' I told you that I did not grok the fullness, but that 'God' was the word that was used." "Yes, Jubal," Mike agreed. "Word is 'God'" He added. "You grok." "No, I must admit I don't grok." "You grok," Smith repeated firmly. "I am explain. I did not have the word. You grok. Anne groks. I grok. The grass under my feet groks in happy beauty. But I needed the word. The word is God." Jubal shook his head to clear it. "Go ahead." Mike pointed triumphantly at Jubal. "Thou art God!" Jubal slapped a hand to his face. "Oh, Jesus H. What have I done? Look, Mike, take it easy! Simmer down! You didn't understand me. I'm sorry. I'm very sorry! Just forget what I've been saying and we'll start over again on another day. But " "Thou art God," Mike repeated serenely. "That which groks. Anne is God. I am God. The happy grass are God, Jill groks in beauty always. Jill is God. All shaping and making and creating together ." He croaked something in Martian and smiled.Article: 92729
This could have been en enlightening discussion, if the OP had avoided the confrontational, accusatory tone. Horror over horrors, he had not gotten an answer by Monday for a question that he had asked on Thursday. That's 2 business days... Does that justify a flamethrower attack? Peter AlfkeArticle: 92730
Bob Monsen (rcsurname@comcast.net) wrote: : On Mon, 05 Dec 2005 22:22:54 +0000, c d saunter wrote: : The bricks I've used have always isolation, but I live a : relatively sheltered life. Where have you seen them, mainly? Some of the transformer based ones I have at work are - mind you I'm in the UK where almost everything has an earth (mechanical interlocks stop you plugging anything in without the third pin...) - I'm guessing this isn't an issue in places like the USA as the various American bricks I've accumulated don't have an earth pin... Cheers ChrisArticle: 92731
Hi Peter, Thank you for your response. You are a famous inventor in Xilinx and I have read many your patents and learn a lot from your patents. As a starter for an inventor, I would like to do more myself to save first investment. The best ideal way for me to follow is to get first patent filed and successfully approved by PTO. I know it is very difficult, but It should be much easier than to learn English as 2nd language. When you have first successful experiences with patent application, then it will go smoother for next patent applications. I think it is better to ask for advices and suggestions on the groups and to get first hand experiences from other experts and to avoid misstep as much as possible. I met a layer who hasn't finished his patent license testing yet and prepared to open the patent application business and to help me file patent applications. I have read many patents from Xilinx and especially pay attentions on their claims. No patent claims from Xilinx contain any logical equations. I did remember once I read a patent that is not Xilinx's, but certainly contains an equation. But I cannot find it any more. Using a logical equation for LUT in claim area in a patent certainly helps explain the idea of the invention. But Xilinx's layers never use them, even though in the description area logical equations are used. So I guess there are some rules in USPTO forbidding to use logical equations for LUT in patent applications. Weng Peter Alfke wrote: > You can file for a US patent up to a year after having divulged the > idea. > That grace period does not apply to foreign filing. There you lose the > right to file immediately after divulging. So, foreign filing is more > demanding, not less. > > As far as equations vs LUTs, I think it makes no difference. But > equations may be more widely understood. BTW, the OP is confusing in > the example, using a logic equation that is actually AND and OR... > > Peter Alfke (with about 30 patents, but all filed by company patent > lawyers)Article: 92732
Weng Tianxiang wrote: > Hi, > I am writing a patent application for FPGA and have no prior > experiences with patent writing. > > I found that in Xilinx patents, all lookup table equations are > described in AND/OR/Multiplexer circuits in its claims. Describing a > logic connection for a lookup table in claims is much more complex in > English than presenting an equivalent logic equation. > > For example, a lookup table has the equation: > Out <= (A*B) + (C*D); > > It is much more concise and simpler than describing the circuit in > AND/OR gate circuits. > > Do you have experiences with and any advices on writing an equivalent > logic equation in a patent claim field ? You should be aware that 'Clarity' and 'Patent' are often mutually exclusive :) Patent lawyers have motivation to obfuscate, for many reasons. Patents are merely a license to litigate, (and an income stream for the lawyer) so they tend to break them into many small claims, that can be argued. If there is prior art, it also helps to sound a lot different, even if you are the same. This also helps to get over the first hurdle, of Patent examiner. Most (all?) FPGA patents will be electronic searchable, so scan those yourself, and then "work your claim into the gaps" between those patents. -jgArticle: 92733
>> In both cases 1 and 2 above the operands are exactly the same, > No, one case is signed/signed (2.), and the other is unsigned/signed (1.). No it's not. For case 2 I wrote: " when the input pins denote that the operand A is unsigned and operand B is signed" So, there are 2 pins, A_SIGNED and B_SIGNED, and I set them so that it is unsigned/signed, just like in case 1.Article: 92734
Peter Alfke wrote: > This could have been en enlightening discussion, if the OP had avoided > the confrontational, accusatory tone. It can still be an enlightening discussion. My accusatory tone is in response to the overall poor quality of Xilinx documentation. Besides, shouldn't the attitude be: The customer is always right? > Horror over horrors, he had not gotten an answer by Monday for a > question that he had asked on Thursday. > That's 2 business days... > Does that justify a flamethrower attack? The problem is not that I didn't get the answer fast. The problem is that everyone is so smart in giving advice to the questions that have not been asked. When I don't know the answer to some question, I don't reply to the topic. However, many people seem to want to be smart and say something, regardless of the fact that I explicitly said that I don't need those answers. I find that annoying. I might have not been clear in the beginning in terms of what my question was, but later I clarified, and I still got responses that answer the questions I didn't ask. Regards, FredArticle: 92735
c d saunter wrote: > Bob Monsen (rcsurname@comcast.net) wrote: > : On Mon, 05 Dec 2005 22:22:54 +0000, c d saunter wrote: > > : The bricks I've used have always isolation, but I live a > : relatively sheltered life. Where have you seen them, mainly? > > Some of the transformer based ones I have at work are - mind you I'm > in the UK where almost everything has an earth (mechanical interlocks > stop you plugging anything in without the third pin...) - I'm guessing > this isn't an issue in places like the USA as the various American bricks > I've accumulated don't have an earth pin... I know that you Brits have a very positive outlook, but there surely must be a way to supply a negative voltage? Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 92736
Fred, this is a public newsgroup. Answers are posted voluntarily and for free. Only a few of us are employed by companies that have a stake in this, and benefit more or less directly from the timely resolution of apparent problems (I fall into this latter category). That's why it is so important to maintain a friendly and cooperative spirit, and avoid insults and slamming. If you feel that Xilinx documentation is not perfect, I would be the first to agree. But similar critique can also be voiced about lots of other documentation. FPGAs are being used by a wide variety of designers with widely varying background and expertise. It is tough enough to avoid mistakes, even tougher to be complete, and hopeless to please everybody. Let's be friendly and cooperative, and avoid insults... PeterArticle: 92737
"Jerry Avins" <jya@ieee.org> wrote in message news:Db6dnTyYHMr6TgnenZ2dnUVZ_smdnZ2d@rcn.net... >c d saunter wrote: >> Bob Monsen (rcsurname@comcast.net) wrote: >> : On Mon, 05 Dec 2005 22:22:54 +0000, c d saunter wrote: >> >> : The bricks I've used have always isolation, but I live a >> : relatively sheltered life. Where have you seen them, mainly? >> >> Some of the transformer based ones I have at work are - mind you I'm >> in the UK where almost everything has an earth (mechanical interlocks >> stop you plugging anything in without the third pin...) - I'm guessing >> this isn't an issue in places like the USA as the various American bricks >> I've accumulated don't have an earth pin... > > I know that you Brits have a very positive outlook, but there surely must > be a way to supply a negative voltage? > > Jerry > So, wall warts almost never have an earth, even in the UK! Our wall warts usually have a plastic 'earth' pin to overcome the interlock. Most power supplies that are a separate 'brick' connect with a two wire connection to the mains, live and neutral, as in the US. Here's a photo of a UK mains lead for this:- http://www.maplin.co.uk/images/Full/1168i0.jpg In the UK, such things are called 'double insulated', see :- http://en.wikipedia.org/wiki/Double-insulated That said, some bricks do have an earth connection as Chris says. These often use a IEC connector like this:- http://en.wikipedia.org/wiki/Power_connector Dunno if the output 0V is connected to this earth. I suspect not in most cases. All the bench DC power supplies I've used, both in the UK and in the US, have separate isolated 0V and earth, usually connectable with a bit of metal. FWIW, Syms.Article: 92738
My first reply would be "buy one". Cost of a PSU is a lot less than the cost of an average board... Otherwise, and assuming your load is less than ~40mA, you can use the circuit in http://sound.westhost.com/project43.htm with a 10v supply. Be careful to separate GND's (since the GND of your +/- 5V is really at 5V....) SimonArticle: 92739
DISCLAIMER: I am not a lawyer, but I have watched them on TV and they all have better hair than me, so I know this is not a career for me. On 5 Dec 2005 15:18:11 -0800, "Weng Tianxiang" <wtxwtx@gmail.com> wrote: >I met a layer who hasn't finished his patent license testing yet >and prepared to open the patent application business and to help >me file patent applications. Correct spelling is lawyer. Using a lawyer who hasn't yet passed the appropriate tests might be cheap, but may not be the best idea. A poorly written patent may still get issued, but will be easier to invalidate later. >I have read many patents from Xilinx and especially pay attentions on >their claims. No patent claims from Xilinx contain any logical >equations. That's because Xilinx does not typically file systems patents. They don't care how the parts are used, just that they are used by many customers. This is one of the reasons why you can't find details of LUT contents. Another really important one in your case is the following question: Does your idea REQUIRE that it be implemented in a LUT, or is your idea DEPENDENT on being implemented in a LUT, or is your idea a NEWER/BETTER LUT. If your answer is no to all of these (and I am guessing it probably is) then you probably do not want to tie you patemt application to implementation in a LUT. In fact, tying it to details of LUT implementation provides a huge hole for someone else to implement the idea in non-LUT stuff and get around your patent. Same thing for implementation in an FPGA. You probably should not require FPGA implementation to practice your idea, since an ASIC, or a bag of TTL chips would also bypass your patent. Xilinx files patents because they don't want someone else to make FPGAs that use the technology that they have invented. This is independent of the LUT contents, which is why you don't see patents from Xilinx that refer to specific contents. You might find the following patent educational: 6148313 It goes to a level of detail even below logic equations, it gives the raw bit patterns of the LUTs, since this is part of the preferred embodiment. You will find no reference to LUTs in the claims though. The patent should show how the claims could be implemented, but the claims leave it far more open to cover other implementations that depend only on what is in the claims. The patent is the first to my knowledge that describes addition through code compression (population counters), but the details of the compressors is not in the claims. The primary claim of the patent does not depend on code compressors. >Using a logical equation for LUT in claim area in a patent certainly >helps explain the idea of the invention. But Xilinx's layers never use >them, even though in the description area logical equations are used. >So I guess there are some rules in USPTO forbidding to use logical >equations for LUT in patent applications. Again, unless your patent can only be implemented in LUTs, you probably do not want to restrict your patent by mentioning LUTs in the claims section. (But remember, I am not a lawyer). >Weng PhilipArticle: 92740
Hello Tomoya-san, We have an errata sheet published on www.altera.com/literature/lit-stx2.jsp which shows the differences between the ES and production devices. There's nothing there that is directly connected to DDR memory interfaces, but I suggest that you take a look and see if anything in your design is related to these errata. Of course your bigger question is "How can I make a DDR interface work?" We have various literature, IP, and development kits on DDR memory (also DDR2), so there's some resources there to help you in the debug process. We have many customers using these memories so in general the Altera device can implement the interface. http://www.altera.com/technology/memory/sdram/mem-ddr_sdram.html http://www.altera.com/technology/memory/dram/ddr2/mem-ddr2.html Often when two seemingly similar parts behave differently, there may be a subtle timing problem, and a part being a little faster or slower than the other can cause a problem. Particularly with DDR, where there's the added complication of the round trip where the FPGA drives the clock of the DDR memory, so the data coming back to the FPGA must be resynchronized. The literature I cited above has some information on how to implement this. Another source of timing problems is board power supply - we've seen some cases where the IR drop of a connector sourcing power to the board causes the FPGA's VCC to be below spec, which slows it down. Another good thing to check. If you think the PLL is a cause here, you could check the jitter on the output of the ES part and the production device. But that's usually pretty robust. Another good tool (in case you don't know about it) is SignalTap, which lets you probe the interior design of the FPGA and view the results on your PC. I hope that these suggestions help. They are pretty general but will give you a good starting point. Sincerely, Greg Steinke Altera CorporationArticle: 92741
Hi Philip, Philip Freidin wrote: > and they all have better hair than me, so I know this is not a What does a good haircut cost in Sunnyvale? :) > Xilinx files patents because they don't want someone else to make > FPGAs that use the technology that they have invented. This is > independent of the LUT contents, which is why you don't see > patents from Xilinx that refer to specific contents. They also seem to file patents on novel applications of their FPGAs. My guess is this is to prevent anyone limiting what Xilinx customers can do with Xilinx FPGAs - a kind of defensive patenting on behalf of their customers. JohnArticle: 92742
Greg-san, thak you for good comment. >From the interface point of view, DDR interfaces (there are two DDR-200/400 interfaces on the evaluation board) are worked well (DDR-200/400 runs on the both board, old and new). The DDR module and its interface runs under DCM. Then, such clock jittar (that Greg-san suggested) will be cancelled (is not seen), I guess (maybe). The only difference behavior that we had faced is, data communication. Our board has total 750 general purpose IOs (these are 2.5 Volt single-ended interface). These interface does not run under DCM. These are driven by the system clock (is generated by the FPGA internal PLL). The old one runs at 250 MHz (or more) speed. But, the new one runs at 150 MHz. So, 40% down. Therefore, I have such question (the original question). Anyway, we'll check the clock characteristics. Especially, clock jittar. Thank you for good advice. And I'm waiting for any other comments about this issue. Best regards, --- Tomoya Kaku <URL: http://www.accverinos.jp> Yokohma R&D Center, Verification System Development Division, SK-Electronics CO., LTDArticle: 92743
One of the big problems in defining a patent in the terms of logic is that it is too specific if your patent covers and/or logic. I'll just use nand/nor logic. That's a good reason why there is no logic in Xilinx's patent. As mentioned Patents have to be as broad as possible to cover as much as possible so that even if it so much as smells the same, your patent will cover it. And that's why you need an expensive patent lawyer Simon "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:4394cb3f$1@clear.net.nz... > Weng Tianxiang wrote: > > Hi, > > I am writing a patent application for FPGA and have no prior > > experiences with patent writing. > > > > I found that in Xilinx patents, all lookup table equations are > > described in AND/OR/Multiplexer circuits in its claims. Describing a > > logic connection for a lookup table in claims is much more complex in > > English than presenting an equivalent logic equation. > > > > For example, a lookup table has the equation: > > Out <= (A*B) + (C*D); > > > > It is much more concise and simpler than describing the circuit in > > AND/OR gate circuits. > > > > Do you have experiences with and any advices on writing an equivalent > > logic equation in a patent claim field ? > > You should be aware that 'Clarity' and 'Patent' are often mutually > exclusive :) > Patent lawyers have motivation to obfuscate, for many reasons. > Patents are merely a license to litigate, (and an income stream for the > lawyer) so they tend to break them into many small claims, that can be > argued. > If there is prior art, it also helps to sound a lot different, even if > you are the same. > This also helps to get over the first hurdle, of Patent examiner. > > Most (all?) FPGA patents will be electronic searchable, so scan those > yourself, and then "work your claim into the gaps" between those patents. > > -jg >Article: 92744
Yews and no.. it could be argued that books are by design, designed to be read. Take a look at the copyright message for most software. "cannot be disassembled for any purpose" is a very common phrase "In order to protect them you may not decompile, reverse engineer, disassemble, or otherwise reduce the Software to a human-perceivable form." This is from the Xilinx EULA for the development tools. I don't have core-generator handy, but as you can see, they don't want you to view in any shape or form their software. Altera might be different but that is because their tools were built with or include GNU You can of course copy directly from a book, I think anyone would be hard pressed to stop someone or even to prove they had exclusive rights to something found in print, you would only have to find it in a different book printed before the one in question to automatically invalidate any clams. Of course, the invention of time travel will make all patents null and void :-) Simon "Symon" <symon_brewer@hotmail.com> wrote in message news:4394ba9d$1_3@x-privat.org... > "Simon Peacock" <simon$actrix.co.nz> wrote in message > news:4393ddf2@news2.actrix.gen.nz... > > '...' is a pause as opposed to '.' a stop. Even text to speech recognises > > this. I will try to refrain... maybe > > > Yeah, sorry, I was just being a smartass. There's an interesting Wikipedia > article all about the ellipsis. http://en.wikipedia.org/wiki/Ellipsis > > > > But reverse engineering can be done to anything. A copyright message is > > all > > you need to 'stop' it but that isn't usually enough. I myself have been > > designing for 20+ years and have purposefully released things as GPL so > > they > > can be public. Other stuff (hardware and software) is most defiantly not > > public. I have some rather flash UARTS, Ethernet Interfaces and E1 units. > > These add value to both my pay-packet each month and to my companies > > standing. They also make sure that each company review, there is a reason > > to keep me employed. I've also started studying towards a BE-Tech and > > possibly a Masters. So why do I think its not OK to copy? There are > > multiple reasons above. > > > > The only time I would recommend breaking a copyright is when the company > > is > > defunct and you need to do an update but even then someone might have > > walked > > away with the copyright/patent. > > > > Simon > > > OK, but if 'reverse engineering' is just finding out how something works, > then that's fine, yes? For example, books are copyrighted, but you can still > read them. As to what you then do with the knowledge you gain, I guess > that's where the line between good and evil is. If you read a copyrighted > electronics text book, it's ok to use the knowledge you gain to design > electronics, or even to write your own textbook, provided you don't copy > verbatim. If you reverse engineer a FIR filter, it's ok (legally and > morally?) to use the knowledge you've gained to create your own, provided > it's not a direct copy. Maybe! In the US, maybe the DMCA has some > ramifications as to the legality of reverse engineering. > Interesting subject, I guess there's not a black and white answer. > Cheers, Syms. > >Article: 92745
Hi Jim,
The speed vs. power trade-off is user-selectable.
The default power optimization setting in Quartus II 5.1 is "Normal
compilation." On average, it achieves a dynamic power reduction of 15% vs.
QII 5.0 (which did not have algorithms specifically for power optimization),
and does not hurt design speed at all. This is a Stratix II result, but
Cyclone II is similar. We get no speed loss because we make power
optimization decisions lose to timing optimization decisions on the circuit
critical path(s) in this mode.
If you want more power reduction, you can choose "Extra Effort" power
optimization. On average, this achieves a dynamic power reduction of 21%
vs. QII 5.0, and reduces design speed by 2%. In this mode we still try to
protect the circuit critical path(s), but are not as conservative in
predicting what paths might be timing critical early in the optimization
flow, so sometimes we do hurt a speed-critical path.
> Here's a question:
> Are those power savings speed-agnostic, or do you also get
> a small improvement in speed (lower CL = Lower power )
> or
> a small degrade in speed ( lower Drive = slower, but less power .. )
>
> -jg
So basically you can choose to have the algorithms be speed-agnostic
(protect speed) or you can get more power reduction by allowing a small
slowdown. We don't get a design speed-up vs. timing-driven compile, since
timing-driven compile was already trying to minimize delay (including the
capactitive load portion of delay) on the critical paths, so trying to
minimize C further on areas of the circuit that are important to power
("power critical") does not help speed.
One last data point: if a design has very easy timing, we average 25%
dynamic power reduction with the "Extra Effort" option, since there are no
longer any timing critical paths to protect, so the whole circuit is fair
game for power optimization.
Regards,
Vaughn
Altera
[v b e t z (at) altera.com]
"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:4393c5fc@clear.net.nz...
> Vaughn Betz wrote:
>> Hi all,
>>
>> I will be giving a NetSeminar this coming Wednesday on Power Optimization
>> for FPGA designs. I'll go over three main topics:
>>
>> - Automatic Power Optimization via CAD: how the Quartus II power
>> optimization algorithms (new in version 5.1) work, how you control them,
>> and how much power they save for various designs.
>> - Design techniques that can further lower power.
>> - How to use the Power Optimization Advisor and Design Space Explorer
>> tools to search for the best power CAD settings and power design tips for
>> your design.
>>
>> See
>> http://www.altera.com/education/net_seminars/all/ns-power-optimize.html
>> for more details and the registration link.
>>
>> I think anyone interested in power will find this interesting -- we're
>> seeing a dynamic power reduction of 20% for the average design, just by
>> moving from Quartus II 5.0 to Quartus II 5.1 and turning on the power
>> optimization features. More savings are possible with the design
>> techniques we'll go over. I hope to see you there, and to get some good
>> questions from the regulars on this newsgroup.
>
> Here's a question:
> Are those power savings speed-agnostic, or do you also get
> a small improvement in speed (lower CL = Lower power )
> or
> a small degrade in speed ( lower Drive = slower, but less power .. )
>
> -jg
>
Article: 92746You may want to check the stockings by the fireplace. Simon "Antti Lukats" <antti@openchip.org> wrote in message news:dn20o1$t57$1@online.de... > ISE 8.1 release was planned for mid nov, now its mid december soon, I wonder > if it is known how much more the ISE 8.1 release is delaying? Xilinx is > advertising ISE webcast on Dec 14, I wonder if that will only cover soon to > be obsoleted 7.1 or be focused on 8.1? > > Actually I am more waiting for the EDK 8.1 in the hope DDR2 support is > added, but as EDK 8.1 release was projected 4 weeks after ISE 8.1 release I > guess the EDK 8.1 actuall release date is slipping also :( most likely into > 2006? > > Antti > >Article: 92747
"c d saunter" <christopher.saunter@durham.ac.uk> wrote in message news:dn2ho4$qhn$1@heffalump.dur.ac.uk... > Bob Monsen (rcsurname@comcast.net) wrote: > : On Mon, 05 Dec 2005 22:22:54 +0000, c d saunter wrote: > > : The bricks I've used have always isolation, but I live a > : relatively sheltered life. Where have you seen them, mainly? > > Some of the transformer based ones I have at work are - mind you I'm > in the UK where almost everything has an earth (mechanical interlocks > stop you plugging anything in without the third pin...) - I'm guessing > this isn't an issue in places like the USA as the various American bricks > I've accumulated don't have an earth pin... I have quite a lot of experience with power supply modules (the "open frame type") and I dear say that for instance NONE of the types offered in the Farnell catalog have their - or 0 connected to the PE. From a manufacturer's point of view this would be absolutely stupid because it means that he would have to have two types of each model, one with the + to PE and another with the - to PE. Also in lab supplies you will always see an extra ground terminal, often between the + and - and possibly with a supplied bracket between the ground and -. Besides, many applications need a complete separation from mains, even from ground. So that is another reason for manufacturers not to connect the - to PE(ground). MeindertArticle: 92748
Could you give me the reference of your paper, please? EricArticle: 92749
On Tue, 6 Dec 2005 08:06:58 +0100, "Meindert Sprang" <mhsprang@NOcustomSPAMware.nl> wrote: >I have quite a lot of experience with power supply modules (the "open frame >type") and I dear say that for instance NONE of the types offered in the >Farnell catalog have their - or 0 connected to the PE. From a manufacturer's >point of view this would be absolutely stupid because it means that he would >have to have two types of each model, one with the + to PE and another with >the - to PE. Also in lab supplies you will always see an extra ground >terminal, often between the + and - and possibly with a supplied bracket >between the ground and -. > >Besides, many applications need a complete separation from mains, even from >ground. So that is another reason for manufacturers not to connect the - to >PE(ground). For any low level measurements, the PE is badly polluted by the noise from switching mode power supply EMC filters etc. For this reason, a separate technical earth (TE) network is often used with only a single contact point between the neutral, grounding electrode and PE and TE earths. A single power supply with the DC side connected to PE would pollute the whole TE network and you would very quickly get rid of such power supplies. Paul
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