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Hi, I am a mature student will be doing some complex VHDL and Verilog design work for my course. As well as having to create and test the functionality of the design (in both languages) I want to document how the design is put together and it's complex hierarchy. Is there anything out there that will allow me to represent my design in some sort of hierarchical functional blocks to use as a documentation tool? As I want to use both languages for the design something that ideally can accommodate VHDL and Verilog. I am happy using my normal editing system for the code design so I don't want a 'block-to-code' type of system. Thanks for your help. James.Article: 92876
Hi Michael, The Xilinx University Program Xilinx XUP Virtex II Pro Development System (XUPV2P) has a add-on video card the VDEC-1 which accepts composite, component, or S-Video input. A reference design to start with is under Demonstrations and Reference Designs on the XUPV2P page: http://www.xilinx.com/univ/xupv2p.html A direct link to the VDEC-1: http://www.digilentinc.com/info/VDEC1.cfm Good Luck! Paul hongying meng wrote: > > Hi, > > I will do some research on video/image processing on FPGA. I will design > VHDL codes for some video/image processing algorithms. I needs a FPGA > development board with a big FPGA chip on it. I also hope it can be > connected with a digital camera or image sensor with real-time image access > into the board. It's better if the image in RGB format and input to the > board frame by frame. > > Does any one know where there exist this kind of FPGA development board or > not? If not, any suggestion should be really appreciated. > > Thanks > MichaelArticle: 92877
"Paul Hartke" <phartke@Stanford.EDU> schrieb im Newsbeitrag news:439863D7.6C3C0A0B@Stanford.EDU... > Hi Michael, > > The Xilinx University Program Xilinx XUP Virtex II Pro Development > System (XUPV2P) has a add-on video card the VDEC-1 which accepts > composite, component, or S-Video input. A reference design to start > with is under Demonstrations and Reference Designs on the XUPV2P page: > http://www.xilinx.com/univ/xupv2p.html > A direct link to the VDEC-1: http://www.digilentinc.com/info/VDEC1.cfm > > Good Luck! > > Paul Paul, that type of Video decoder does _not_ work with cmos/digital image sensor at all but otherwise the board is good at the university price :) anttiArticle: 92878
> Does any one know where there exist this kind of FPGA development board or > not? If not, any suggestion should be really appreciated. KROS Technologies now has available a daughter card for the Nios II Cyclone II dev board (the board has an EP2C35 FPGA; a nice medium-density cyclone II device): http://www.krostechnologies.com/ The card includes color LCD touch panel, a small camera, and some very interesting example designs. Jesse Kempa Altera jkempa -#at#- altera -#dot#- comArticle: 92879
svasus@gmail.com schrieb: > Hi all, > > I am needed to talk with a microcontroller through an I2C interface > from my FPGA. I dont want to write a code for it as well not use an > opensource core. This is partly due to space constraints and testing. > Speed and cost are not constraints. > So I was hoping to find a chip which would sandwich between the FPGA > and I2C interface. > Searched on the net but could not find any. If anyone has suggestions > please let me know. I2C is a protocol. You can use the FPGA to talk to the uP via the I2C protocol. Or you can use another chip that talks to the uP via I2C, but then, how do you talk to the other chip? You need another protocol to do that. You can not get rid of a communication protocol implemented by FPGA logic. What you are assuming is, that there is some other protocol that is a lot easier and smaller to implement than I2C. But that depends on were your data is coming from and going to. If your data inside the FPGA is processed bit serial I am sure that it is simpler to output it by I2C than using a parallel processor bus. However, if you have a uP inside your FPGA a peripheral chip as other posters suggested is of course simpler. So you are down to what protocol you use for comunication inside your FPGA. Resources depend a lot on that and your data pattern. For example using SLR16s it should not take much more than three luts to send a single byte once or repeatedly over I2C. (assuming you have a slow clock available) Kolja SulimmaArticle: 92880
(translate + map + PAR) == synthesis If you're simulating post-PAR, you -are- simulating the synthesised modelArticle: 92881
You might want to look at XAPP807 for an example application where UltraController-II is used in combination with the Virtex-4 Tri-Mode Ethernet MAC to run a web server completely from the PPC caches. This application uses the data side OCM port on the PPC for communication with the TEMAC and could, in your application, be replaced with BRAMs for the parameters. - Peter http://direct.xilinx.com/bvdocs/appnotes/xapp807.pdf reidek@gmail.com wrote: > All, > > Is it possible to run programs on the embedded PowerPC in the Xilinx > chips without external RAM and/or operating system? The PPC will only > be doing some minor work and it would be much better if we can get away > with not putting any RAM on the boards. The ideal would be to store > the instructions in block RAM on the FPGA and then trigger the PPC to > run. Is this possible? > > Thanks! > > Eric >Article: 92882
We used sockets on one board. I wouldn't expect to use them in production, the cost if far to excessive. If you can find a place that does BGA assembly you will find it much better. We have had very good success lately with assembly of boards with PBGA packages Simon "Marco" <marcotoschi@nospam.it> wrote in message news:dn927g$gr1$1@nnrp.ngi.it... > > <nospam.eric@gmail.com> wrote in message > news:1134033868.487979.128590@g49g2000cwa.googlegroups.com... > > Hi > > > > At a minimum we need to know how much bandwidth and latency you > > accept/require for the communication between your FPGAs and how much of > > your FPGAs you intend to dedicate to inter-FPGAs communication. The > > caracteristics of the FPGA themselves are also welcome. > > > > Waiting for your answer, > > > > Eric DELAGE, Senior ASIC/FPGA Architect > > EMail: nospam DOT eric AT gmail DOT com > > Homepage: http://eric-delage.no-ip.info > > > > Many Thanks in advance! > > Fortunately I make sure my chief changes his mind toward the use of 2 FPGA. > Now we're searching for an adapter for BGA package. > I have found this from Interconnect Systems: HiLoTM BGA Socketing Supports > Xilinx® Virtex 4 BGA Packages > > Does anyone has already used it? Could proive feedback? > > Many and many thanks > MArco > >Article: 92883
Hi All, I have a embedded desig where I communicate with two boards via Fast ethernet. The design is very simple, the packets are generated from a fpga and sent to the ethernet phy on MII. In the new design I'd like to replace the ethernet phy with a VSDL2 chipset, so I need only one twisted pair and for supporting more than 100 m. Has anybody did something similar? IMO it should be very straight forwarded to replace the phy with a VDSL2 chipset, but please let me know if I'm wrong. Regards, KimArticle: 92884
one other point.. if you do use a BGA.. put about 20 pins off to a dual row connector... that will allow you debug pins that can't be accessed. Also look at exposing the bottom of vias 'off-chip'... so you can probe signals to find out what's happening. Simon "Simon Peacock" <simon$actrix.co.nz> wrote in message news:43987565$1@news2.actrix.gen.nz... > We used sockets on one board. I wouldn't expect to use them in production, > the cost if far to excessive. If you can find a place that does BGA > assembly you will find it much better. We have had very good success lately > with assembly of boards with PBGA packages > > Simon > > > "Marco" <marcotoschi@nospam.it> wrote in message > news:dn927g$gr1$1@nnrp.ngi.it... > > > > <nospam.eric@gmail.com> wrote in message > > news:1134033868.487979.128590@g49g2000cwa.googlegroups.com... > > > Hi > > > > > > At a minimum we need to know how much bandwidth and latency you > > > accept/require for the communication between your FPGAs and how much of > > > your FPGAs you intend to dedicate to inter-FPGAs communication. The > > > caracteristics of the FPGA themselves are also welcome. > > > > > > Waiting for your answer, > > > > > > Eric DELAGE, Senior ASIC/FPGA Architect > > > EMail: nospam DOT eric AT gmail DOT com > > > Homepage: http://eric-delage.no-ip.info > > > > > > > Many Thanks in advance! > > > > Fortunately I make sure my chief changes his mind toward the use of 2 > FPGA. > > Now we're searching for an adapter for BGA package. > > I have found this from Interconnect Systems: HiLoTM BGA Socketing Supports > > Xilinx® Virtex 4 BGA Packages > > > > Does anyone has already used it? Could proive feedback? > > > > Many and many thanks > > MArco > > > > > >Article: 92885
Unfortunately finding a VDSL2 chip might be difficult. As with most PSTN specs, the customer end is easy, the telcom end is a bit more problematic. Telco's don't want individual ports, they want 2,000 ... so that's what they get. It also looks a bit bleeding edge.. so try to stick with one supplier to avoid interoperability issues. Simon <fpgakid@gmail.com> wrote in message news:1134066178.467301.202070@g14g2000cwa.googlegroups.com... > Hi All, > > I have a embedded desig where I communicate with two boards via Fast > ethernet. The design is very simple, the packets are generated from a > fpga and sent to the ethernet phy on MII. In the new design I'd like to > replace the ethernet phy with a VSDL2 chipset, so I need only one > twisted pair and for supporting more than 100 m. > Has anybody did something similar? IMO it should be very straight > forwarded to replace the phy with a VDSL2 chipset, but please let me > know if I'm wrong. > > Regards, > > Kim >Article: 92886
Scott Bekker wrote: > Hi, > > I have a design for a Virtex 4 SX35-10 that is not meeting my timing > constraints. The only constraint is set in the ucf file as a clock > period of 4.75 ns. Synthesis gives the following: > > Timing Summary: > --------------- > Speed Grade: -10 > > Minimum period: 7.680ns (Maximum Frequency: 130.213MHz) > Minimum input arrival time before clock: 1.890ns > Maximum output required time after clock: 5.810ns > Maximum combinational path delay: 0.000ns > > Doing a post map static timing analysis gives the following as the > first error. (place and route fails) > > Source: > uut1/overlapadd1/fifo1/BU2/U0/ss/memblk/fifo_generator_v2_2_fifo_generator_v2_2_xst_1_coreinst/fifo_generator_v2_2_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst/bm/mem/arch_v2/prim/4/b1/chk0/col/0/b2/mextd/arch_v2/c1/ram1/v2/d4096/by4/newSim8/RAMB16 > (RAM) > Destination: uut1/overlapadd1/f2_data_in_sig_0_BRB2 (FF) > Requirement: 4.750ns > Data Path Delay: 5.522ns (Levels of Logic = 1) > Clock Path Skew: 0.000ns > Source Clock: fast_clk rising at 0.000ns > Destination Clock: fast_clk rising at 4.750ns > Clock Uncertainty: 0.060ns > > Does the post map report include estimates of routing delays? Can I > constrain XST to provide better results, if so how? Is 210 MHz too fast > for this speed grade FPGA? Running XST with higher effort does not > seem to help. > > thanks > 210 MHz is apparently too fast for YOUR DESIGN in this speed grade. Any speed grade Virtex4 is capable of quite a bit faster clocking, but you need to be somewhat careful in the design. I am currently working on a floating point FFT design for an XC4VSX55-10 that is clocked at 400 MHz. If you look at the .twr timing report instead of the one that comes up in the gui, it gives more detail on the failing path, including an element by element break down of the failing path and the location of each element. Since there is only 1 level of logic, I am guessing that this failing path is sourced by a block RAM that does not have the output register enabled, and the destination has a LUT in front of the flip-flop, plus it is probably not located immediately adjacent to the BRAM. You'll want to increase or at least modify the pipelining to improve the performance, and turn on the output register on the BRAM (the clock to out of the BRAM is rather long without the output register).Article: 92887
Marco <marcotoschi@nospam.it> wrote: > "Antti Lukats" <antti@openchip.org> wrote in message > news:dn6b3a$h6c$01$1@news.t-online.com... > > "Marco" <marcotoschi@nospam.it> schrieb im Newsbeitrag > > news:dn643r$hbo$1@nnrp.ngi.it... > >> Hallo, > >> does anyone has connected 2 FPGA? > >> Which kind of connection have used? > >> > >> Many Thanks > >> Marco > > > > FPGAs are often connected to each other by different means. > > > > your question can have no reasonable answers as you are the only > > person > > who know WHY you want to connect the FPGA, and the answer to that > > question > > is needed in order to decide HOW. It all depends why and what you are > > going to achive. > > > > Antti > > > I must develop a system with lots of I/O, about 180-190. My chief don't > want use BGA (fg320), but pq208... > so I thought to connect 2 fpga pq208. > I think it'is bad... but there are other chances? > Otherwise does exist a BGA adapter for fg320 package to change it into a > pq320? Why not use a FPGA module like the Zefant Modules? (www.zefant.de)? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 92888
"Antti Lukats" <antti@openchip.org> writes: > implementing i2c in fpga in hw or sw is simpler than interfacing PCFxxx pr > PCAxxx It takes fewer pins to do I2C directly than to interface the Philips parts, unless you already have a parallel bus you're using for other stuff. But it's not particularly "simpler" to do I2C hardware yourself, at least if you care about actually meeting the full I2C specifications. I've seen a lot of bad I2C implementations that won't work under various real-world conditions. For instance, I2C masters that don't handle clock-stretching, or that don't handle arbitration. And I2C slaves that don't meet the I2C timing specs. The software bit-banging implementations are usually (but not always) the worst as far as violating the specs. I'm not saying that it's tremendously difficult to do it right, but it is definitely more difficult than just bolting on a chip with an 8-bit parallel interface that does all the "heavy lifting" for you. I've done it both ways. I wouldn't design in the Philips chip is a cost-sensitive high-volume product, but for a less cost-sensitive design, or if time-to- market is a major concern, it's a reasonable approach. EricArticle: 92889
fpgakid@gmail.com wrote: > Hi All, > > I have a embedded desig where I communicate with two boards via Fast > ethernet. The design is very simple, the packets are generated from a > fpga and sent to the ethernet phy on MII. In the new design I'd like to > replace the ethernet phy with a VSDL2 chipset, so I need only one > twisted pair and for supporting more than 100 m. > Has anybody did something similar? IMO it should be very straight > forwarded to replace the phy with a VDSL2 chipset, but please let me > know if I'm wrong. > > Regards, > > Kim > It is not clear what you are really trying to achieve, and whether VDSL2 is the right solution. There may be better options for connecting two boards in a more standard way, though I don't know what would meet your needs best. Do you need to maintain the high data rate over a much greater distance, and is it really important to achieve the high rate over only one pair? If you can live with the 100m restriction or less, and use standard cabling, it sounds simpler to stick with what you have. I have done something similar but it was before VDSL2, and I had access to proprietary hardware. You will probably be restricted by whatever interface the chipset provides, even if you can get hold of the chipsets. And it is likely to be a lot of effort to design something which will always be non-standard.Article: 92890
Eric Smith wrote: > "Antti Lukats" <antti@openchip.org> writes: > >>implementing i2c in fpga in hw or sw is simpler than interfacing PCFxxx pr >>PCAxxx > > > It takes fewer pins to do I2C directly than to interface the Philips parts, > unless you already have a parallel bus you're using for other stuff. > > But it's not particularly "simpler" to do I2C hardware yourself, at least > if you care about actually meeting the full I2C specifications. I've > seen a lot of bad I2C implementations that won't work under various > real-world conditions. For instance, I2C masters that don't handle > clock-stretching, or that don't handle arbitration. And I2C slaves that > don't meet the I2C timing specs. > > The software bit-banging implementations are usually (but not always) > the worst as far as violating the specs. > > I'm not saying that it's tremendously difficult to do it right, but it > is definitely more difficult than just bolting on a chip with an 8-bit > parallel interface that does all the "heavy lifting" for you. I've done > it both ways. I wouldn't design in the Philips chip is a cost-sensitive > high-volume product, but for a less cost-sensitive design, or if time-to- > market is a major concern, it's a reasonable approach. another alternative ( but perhaps a bit new...) is this family from Philips : http://www.standardics.philips.com/products/bridges/spi.slave.i2c.master.gpio/ This is TSSOP16, SPI-i2c master, 3Md on SPI and 400KHz on i2c. [ It may even be a pgmd LPC916 :) ? ] The overview does not say if the i2c side is 5V compliant. -jgArticle: 92891
I'm considering these parts for a new design, and the low static power and small footprint, instant-on features seem nice. In terms of performance or density, this app is not demanding at all, but we want more headroom than a CPLD gives. I haven't used Actel parts or SW for over 10 years - how have design/supply/support experiences been on ProAsic3E?? How decent are the Actel tools for HDL based designs? I'm very familiar with the Xilinx IDE. I'd be in the 30K device to start with. If you want to keep your #$%! answers more private, you can mail me directly. I can sum up for the group later. Thanks in advance!Article: 92892
Thanks for your reply. I would actually like to simulate the verilog model AFTER synthesis but BEFORE translate. Is there any way to do that? Thanks in advance.Article: 92893
Jim Granville wrote: > svasus@gmail.com wrote: > >> Hi all, >> >> I am needed to talk with a microcontroller through an I2C interface >> from my FPGA. I dont want to write a code for it as well not use an >> opensource core. This is partly due to space constraints and testing. >> Speed and cost are not constraints. >> So I was hoping to find a chip which would sandwich between the FPGA >> and I2C interface. >> Searched on the net but could not find any. If anyone has suggestions >> please let me know. > > > Look at i2c BUS controllers from Philips > http://www.semiconductors.philips.com/similar/PCF8584.html > > and the PCA9564 is a candidate. > These take a parallel uC BUS and connect to i2c - so you > will need to load some config registers, from the FPGA, but > not many. > This device goes to ~400KHz > > You could also look at any small uC that has separate SPI and i2c HW - > eg Philips LPC916 in TSSOP16, or most Silabs C8051F3xx devices and > are about the same price as the 9564- and you get ADC/DAC and proper > buffering, for free... Further to this option, Philips have more info here: http://www.standardics.philips.com/products/i2ccontrollers/ This shows the (very new) 9664, which adds a trimmed OSC, 68 byte buffer, and 50MHz databus speeds, with 1MHz i2c, so these devices are improving quite rapidly.... If such a device meant you could use the next-smallest FPGA, it would pay for itself. Could also make sense next to a MAX II or MachXO, where resource is more precious.... -jgArticle: 92894
I'll try to be a little clearer: Synthesis is translate and map. After synthesis would be after translate and map. You can't be after synthesis and before translate because translate is the 1st step in synthesis. It's sort of like saying "After I get there, but before I leave". What exactly are you looking for, anyway?Article: 92895
Chloe, When I look at the GUI for ISE 7.1i sp4, Under Synthesize - XST, I see an item to Generate Post-Synthesis Simulation Model. Is that what you want? I normally do not do a simulation at this intermediate level, so I don't have any information concerning the gotcha's involved. It looks like it will output a file compatible with Modelsim's Verilog simulator. Hope this helps, NewmanArticle: 92896
Oh really? Apologies for my ignorance. This is my first time using an FPGA's synthesis tool, so I didn't know that synthesis actually meant translate and map. I thought translate and map was using the LOCed pin assignments and inserting that with the synthesised design onto the FPGA. I previously dealt with Synopsys synthesis tool, Design Compiler, so it's a little different from FPGA synthesis. Anyways, I am having a little trouble with the design on FPGA. When I simulated the behavioural model on ModelSim, the results are correct. However, after synthesis, when I ran a simulation on the post-translate verilog model, the outputs were wrong. Ditto for post-map and post-PAR verilog models. I'm at my wits' end, because I've been working on the problem for quite some time now, and yet, I still couldn not find the root of the problem. There were no errors in my synthesis report, translate report, map report and PAR report. There were no timing violations either. Any suggestions for an FPGA rookie like me? Oh, by the way, I think it's more like "After I leave, but before I get there" ;) Thanks in advance.Article: 92897
Chloe wrote:
> I'm at my wits' end, because I've been working on the problem for quite
> some time now, and yet, I still couldn not find the root of the
> problem. There were no errors in my synthesis report, translate report,
> map report and PAR report. There were no timing violations either.
>
> Any suggestions for an FPGA rookie like me?
Post your code.
-- Mike Treseler
Article: 92898Newman: Thanks for the suggestion. I actually tried taking out the synthesised output file and running a simulation on it with a testbench on Modelsim. I imported the FPGA library into Modelsim as well, with the cell library used in the synthesised model. Unfortunately, I encounted some fatal errors which I do not understand. The fatal error seems to be connected with the library, instead of the design. Normally I would just do a simulation beyond the translation stage, but since I had no idea where the problem is in the post-translate verilog model, I thought I'd run a simulation on synthesis and see if the problem occured there as well. I'm trying to eliminate as many factors as I can in finding the root of the problem. Anyways, according to ghel, the translated model IS the synthesised model, so I guess I'll work with that instead. Thanks again :)Article: 92899
Mike: Very sorry, it's propriety information, so I cannot post my code here. I know it's silly for me to ask for help without me having to post my code here, but I thought with everyone's experience with FPGAs, I could get some suggestions or comments from y'all, or maybe some of your own experience in a similar problem and how you came about solving it. Apologies again, and thanks for the suggestions given. Chloe.
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