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>ylc199 wrote: >> Hi >> >> I have a Stratix EP1S80 DSP development board. However, i am not able to >> get the ADC or the DAC devices on the board to work. What i am trying to >> do is simply send an analog waveform (eg 1 khz sine wave) into the adc and >> then try to recover the waveform with the DAC. Can anyone please kindly >> advice on this or even better if anyone have a design example that can >> email me? Thanks > >I remember a colleague having had his problems too. >The local Altera distributor was of a great help >on the phone. > >Rene >-- >Ing.Buero R.Tschaggelar - http://www.ibrtses.com >& commercial newsgroups - http://www.talkto.net > It has been a week and the local altera distributor hasn't reply. Still with a some luck i finally got it to work; problem solved. ThanksArticle: 92851
Scott Bekker wrote: > Hi, > > I have a design for a Virtex 4 SX35-10 that is not meeting my timing > constraints. The only constraint is set in the ucf file as a clock > period of 4.75 ns. Synthesis gives the following: > > Timing Summary: > --------------- > Speed Grade: -10 > > Minimum period: 7.680ns (Maximum Frequency: 130.213MHz) > Minimum input arrival time before clock: 1.890ns > Maximum output required time after clock: 5.810ns > Maximum combinational path delay: 0.000ns > > Doing a post map static timing analysis gives the following as the > first error. (place and route fails) > > Source: > uut1/overlapadd1/fifo1/BU2/U0/ss/memblk/fifo_generator_v2_2_fifo_generator_v2_2_xst_1_coreinst/fifo_generator_v2_2_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst/bm/mem/arch_v2/prim/4/b1/chk0/col/0/b2/mextd/arch_v2/c1/ram1/v2/d4096/by4/newSim8/RAMB16 > (RAM) > Destination: uut1/overlapadd1/f2_data_in_sig_0_BRB2 (FF) > Requirement: 4.750ns > Data Path Delay: 5.522ns (Levels of Logic = 1) > Clock Path Skew: 0.000ns > Source Clock: fast_clk rising at 0.000ns > Destination Clock: fast_clk rising at 4.750ns > Clock Uncertainty: 0.060ns > > Does the post map report include estimates of routing delays? not sure. You said P&R failed -why? Were there unroutes? Timing failed? > Can I constrain XST to provide better results, if so how? There is a switch (in map setup I think) for XST to optimize for speed or area, which should be set to speed. But to get significant gains, you need to understand what the path is that is failing and how it fits in your design. Can you relate the source and destination names from that timing report back to the corresponding RAM and FF in your source code? Usually a typical design has many paths that are effectively not really ever exercised at full clock speed or maybe not at all. If you are lucky, the path that is failing is in this category. You might read up on the "multicyle" path and "ignore" constraints. If the path that is failing really needs to run that fast, you can use tricks like pipelining to break up the large slow operation into several smaller faster ones. hmmm I just noticed the failing path is just 1 logic level, so pipelining probably won't help. > Is 210 MHz too fast for this speed grade FPGA? Depends entirely on the particulars of your design. A small state machine, probably no problem. 64 bit non pipelined single cycle accumulator, probably to slow. It looks like the source of your failing path is the output of a fifo's sram. IIRC, the clock to data out of block RAM is significantly larger than that of FF's. If that's the case, maybe you can pull some trick like make the fifo output twice as wide, and feed that as a 2-cycle path into some sort of FF based mux that can run at full clock speed. In other words, if you can transfer twice as much data, you can take 2 clocks to do it, so it effectively only has to run at 105 Mhz. -JeffArticle: 92852
Vaughn Betz wrote: > Hi Kedar, > > If you are using Quartus Integrated Synthesis, there is no need (or ability > in the tool) to black box the altgxb megafunction, since Quartus has the > complete implementation available to it. > > If you are using Synplify or Precision Synthesis, then you can and should > black box this megafunction, and Quartus will fill in the implementation > later. If possible, you should use the Clear Box flow which will supply the synthesis tool with a good timing model for the megafunction. A simple black box with unknown timing can really confuse timing optimizations. Ken McElvain > > If you are using Quartus Integrated Synthesis and your goal is to make > synthesis fast by partitioning up your design so you can synthesize > sub-components separately, I'd recommend you use the Quartus incremental > compile feature to divide up your design, and then incrementally synthesis > (or synthesize & fit) various parts of the design, while other parts are > left unchanged. See Chapter 1 of the Quartus handbook at > http://www.altera.com/literature/quartus2/lit-qts-synthesis.jsp for > information on how to use incremental compilation. > > Regards, > > Vaughn Betz > Altera > v b e t z (at) altera.com > > <kedarpapte@gmail.com> wrote in message > news:1132905627.298382.157520@g49g2000cwa.googlegroups.com... > >>Hi All, >> >>I am working on a design targeted to Altera Stratix Gx >>I am using high speed macro (gxb macro) in the design. >> >>while doing implementation I want to elaborate the hierarchy by using >>"Maintain Hierarchy" option in Synthesis. >>but I don't want to elaborate "gxb macro" part >>how do I do it...? >>can I declare that instance as black box...? >>how to do that in Quartus II...? >> >>Thanks >>Regards >>Kedar >> > > >Article: 92853
Hi there, I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter 6.0a simulator. The FPGA which I am downloading my design onto is a Spartan IIE (it's on the Spartan IIE LC Development Kit, with an XC2S300E device). I'm very new in FPGAs and hardware design, and if you could help, that would be great. Is there any way for me to run a simulation on the post-synthesis model of my design? I know that with Xilinx ISE, we can run simulations on behavioural models, post-translate, post-map and post-PAR models. What about the synthesised model? Please help. Thanks very much in advance. Regards, ChloeArticle: 92854
Hi,
in my design I would like to have the possibility to switch beetween
two
clock signals: 'clk' (this is my main clock) and 'ext_clk' (the second,
external clock) and the output clock is 'clk_out'. It all depends on
one
signal - let's call it 'temp'. 'Clk_out' is then used in the
sensitivity
list of some process ("process(clk_out) ..."). But when I code it in
VHDL
like this:
clk_out <= clk when temp = '0' else ext_clk;
in ISE I get the message that clk_out signal
"is generated by combinatorial logic and XST is not able to identify
which
are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify te clock signal(s)
generated by combinatorial logic.
Some clock signals were not autmatically buffered by XST with BUFG/BUFR
resources. Please use the buffer_type constraint in order to insert
these
buffers to the clock signals to help prevent skew problems."
So how should I solve this problem correctly?
Thanks in advance,
Tomek
Article: 92855Go to the Xilinx website xilinx.com Enter six easy pieces in the search window Open the TechXclusive article with that title Scroll down to #6 and you find a circuit that allows you to switch between two unrelated clock frequencies, and do the switching asynchronously to either clock. The only limitation is that both clocks must be free-running, since you cannot switch away from a locked-up clock. Peter Alfke. Xilinx Applications You can also use this insanely unwieldly URL: http://xgoogle.xilinx.com/search?q=cache:_zwQtQeRQh0J:www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=pa_six_easy&iLanguageID=1&iCountryID=1+six+easy+pieces&access=p&output=xml_no_dtd&ie=UTF-8&client=xilinx&site=EntireSite&oe=UTF-8&proxystylesheet=xilinxArticle: 92856
Hi all I don't mean reverse engineering... in actual sense. I need a Decimation filter structure where i can update my coefficients(ie access is provided to the user to update filter coefficient, which is not provided in xilinx core generated module). I have a structure of FIR filter built by me, but that uses more resources than provided by xilinx core generator. As all of us know the decimation structure there is nothing great in that. But how to use xilinx block ram to exploit the symmetry of the coefficient may not be known to all. I am looking for a filter structure not VHDL/Verilog code. I will be very glad to use xilinx provided cores if it suits my requirement of coefficient updation, unfortunately they are not supporting it. regards bijoyArticle: 92857
"Eric Smith" <eric@brouhaha.com> schrieb im Newsbeitrag news:qhfyp45x0x.fsf@ruckus.brouhaha.com... > vasudev srinivasan wrote: >> I am needed to talk with a microcontroller through an I2C interface >> from my FPGA. I dont want to write a code for it as well not use an >> opensource core. This is partly due to space constraints and testing. >> Speed and cost are not constraints. >> So I was hoping to find a chip which would sandwich between the FPGA >> and I2C interface. > > Antti Lukats wrote: >> there is no such thing. > > Certainly there is! Look for the Philips PCF8584 or PCA9564. no there isnt - the overhead for interfacing external i2c controller is larger than the sw needed to implement the i2c in softwre only so from that point of view there is no easy solution that makes the fpga sides simpler. implementing i2c in fpga in hw or sw is simpler than interfacing PCFxxx pr PCAxxx so there is no easy sandwitch-chip Antti PS look at other posters they say the same thing I did.. and YES I do know the existance of the silicon you mentioned.Article: 92858
Hi All, I am currently developing for Xilinx SPARTAN3 FPGA. I have a design in which a FSM asserts a clock enable signal for few registers (all registers use the same clock-enable) for 1 clock cycle. My post place and route simulation shows correct operation of the design i.e the registers are updated correctly. However when I run the design on actual FPGA the registers are not updated and design doesn't behave correctly. I extended the clock enable to 2 clock cycles and this makes the design run correctly on the FPGA. I have done post PAR timing analysis and don't get any timing errors. I am also clocking the device at half the clock speed that the design can be run at. I am not sure what the problem is. Would anybody please be able to tell me what the problem might be. Thanks for your help. SudhirArticle: 92859
> code in TESTBENCHES. > If there are many other ways of testing and validation which i'am > unaware of PLEASE let me know. Code review, testbenches, static timing analyses and formal verification are the major verification tasks. Don't know which of them makes sense for your designs and team. > One last doubt, in verification, do we even work on STATIC TIME > ANALYSIS and SYNTHESIS. or this is done by the designer itself.. How could we know if you don't? STA is usually perfomed after layout, has your designer feedback from layout? Do you have to verify after layout or are you only responsible for functional verification until synthesis? bye ThomasArticle: 92860
svasus@gmail.com writes: > So I was hoping to find a chip which would sandwich between the FPGA > and I2C interface. A second microcontroller :-) Connect the PIC 16FL87X to your FPGA and program the PIC to send data received on the RB port out on the I2C port or vice versa... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 92861
Have you checked your setup/hold timings of your FPGA inputs ? Are you simulating them in an appropiate way ? Rgds Andr=E9Article: 92862
Hi Antti, I am happy to see you managed to get it up and running although using the serial port might have been easier than using chipscope. I will add an 8254 and 8259 (required for a minimum system) as soon as my workload reduces a bit (probably around Christmas) If only I had some more "spare" time...... :-) Regards, Hans. www.ht-lab.com "Antti Lukats" <antti@openchip.org> wrote in message news:dn6tpb$7oh$02$1@news.t-online.com... > seeing is beliving :) > > the modelsim precompiled version was offered by HT-LAB for free for some > time, but that did not trigger my curiosity level - but now as also EDIF > version are available its really simple and easy to test drive the CPU86 > ipcore in FPGA! it took about 1 hour to get the core todo something in an > Virtex4, the utilization in FX12 was 51% of the slices. > > http://xilant.com/content/view/19/2/ > > there is ChipScope Pro snapshot of the first succesfull test. > > and the CPU86 is from HT-LAB > http://www.ht-lab.com/ > > Antti > > Hans are you here? >Article: 92863
"Hans" <hans64@ht-lab.com> schrieb im Newsbeitrag news:PtSlf.6121$E14.3906@newsfe7-win.ntli.net... > Hi Antti, > > I am happy to see you managed to get it up and running although using the > serial port might have been easier than using chipscope. I will add an > 8254 and 8259 (required for a minimum system) as soon as my workload > reduces a bit (probably around Christmas) If only I had some more "spare" > time...... :-) > > Regards, > Hans. > www.ht-lab.com > Hi Hans, spare time for Christmas - thats I suppose the ultimate wish of all of us :) using serial port would not have been easier as I should have added a DCM to supply proper clock, and I did have any RAM in the system only the bootstrap ROM. I just wanted to make a REALquick inFPGA test. yes having a 8259+8254 would be cool or even better a minimal "PC" setup :) when I wrote my 8086 ipcore I also started the 8254 etc ipcores but they are not completed another idea what I would really like to see is some sort of 'virtual' mode where the cpu could fall back into shadow supervisor mode and emulate unimplemented hardware or instruction, with an FPGA IP core it would be really easy to implement (sure not by editing the EDIF..) Antti PS Hans I have some realworld customer queries about x86 ipcore as well so please contact me in private as wellArticle: 92864
Currently I'm looking only in 800x480 resolution with (if possible) 18-bit color (16 bit is also ok) and flat-panel digital RGB interface. Damir "Don McKenzie" <look@mysig.com> wrote in message news:43973685$0$17708$afc38c87@news.optusnet.com.au... > damir wrote: > >> I'm looking for simple VGA (XGA up to 800x600) controller for displaying >> simple images on the LCD pannel - any suggestion for available ASIC (LCD >> controller) or FPGA (VHDL core) design will do. Thanks, >> >> Damir > > http://www.dontronics.com/micro-vga.html > is one solution > > Don... > > > -- > Don McKenzie > E-Mail Contact Page: http://www.dontronics.com/e-mail.html > > Micro,TTL,USB to 1.5" color LCD http://www.dontronics.com/micro-lcd.html > USB,RS232 or TTL to VGA Monitor http://www.dontronics.com/micro-vga.html > World's smallest USB 2 TTL Conv http://www.dontronics.com/micro-usb.htmlArticle: 92865
Hi At a minimum we need to know how much bandwidth and latency you accept/require for the communication between your FPGAs and how much of your FPGAs you intend to dedicate to inter-FPGAs communication. The caracteristics of the FPGA themselves are also welcome. Waiting for your answer, Eric DELAGE, Senior ASIC/FPGA Architect EMail: nospam DOT eric AT gmail DOT com Homepage: http://eric-delage.no-ip.infoArticle: 92866
Thank you so much! I think it is a very good board for me. But I am not sure the following three things: 1. Will the image signal be got in the memory of the FPGA board? RGB or other format?Need I design some FPGA module for them? 2. For this board, is the price including the daughter board? 3. For using this FPGA design, any extra software needed for downloading or writing? Thanks again "Antti Lukats" <antti@openchip.org> wrote in message news:dn6sth$uue$01$1@news.t-online.com... > "Gabor" <gabor@alacron.com> schrieb im Newsbeitrag > news:1133966508.937738.86720@g43g2000cwa.googlegroups.com... >> hongying meng wrote: >>> Hi, >>> >>> I will do some research on video/image processing on FPGA. I will design >>> VHDL codes for some video/image processing algorithms. I needs a FPGA >>> development board with a big FPGA chip on it. I also hope it can be >>> connected with a digital camera or image sensor with real-time image >>> access >>> into the board. It's better if the image in RGB format and input to the >>> board frame by frame. >>> >>> Does any one know where there exist this kind of FPGA development board >>> or >>> not? If not, any suggestion should be really appreciated. >>> >>> Thanks >>> Michael >> >> Check out Xilinx: >> >> Virtex-4 Video Starter Kit (HW-V4SX35-VIDEO-SK-US) >> >> This seems to have an RGB image sensor built in. >> >> http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-V4SX35-VIDEO-SK-US&sGlobalNavPick=&sSecondaryNavPick= >> > > thats a nice bundle, yes. > > the FPGA board is actually a ML402 what costs far less as standalone board > > the micron camera that should be bundled is RGB camera, but its interface > does not deliver RGB as parallel, there is some multiplexing required > anyway. > > funnily the camera chip is not on the video daughter board (or nor clearly > visible) also there seems to be no suitable connector for the camera and > there is no other info so I wonder where the image sensor is hidden? > > Antti > > > > > > > > > > > > >Article: 92867
<nospam.eric@gmail.com> wrote in message news:1134033868.487979.128590@g49g2000cwa.googlegroups.com... > Hi > > At a minimum we need to know how much bandwidth and latency you > accept/require for the communication between your FPGAs and how much of > your FPGAs you intend to dedicate to inter-FPGAs communication. The > caracteristics of the FPGA themselves are also welcome. > > Waiting for your answer, > > Eric DELAGE, Senior ASIC/FPGA Architect > EMail: nospam DOT eric AT gmail DOT com > Homepage: http://eric-delage.no-ip.info > Many Thanks in advance! Fortunately I make sure my chief changes his mind toward the use of 2 FPGA. Now we're searching for an adapter for BGA package. I have found this from Interconnect Systems: HiLoTM BGA Socketing Supports Xilinx® Virtex 4 BGA Packages Does anyone has already used it? Could proive feedback? Many and many thanks MArcoArticle: 92868
Thomas Stanka wrote: > > code in TESTBENCHES. > > If there are many other ways of testing and validation which i'am > > unaware of PLEASE let me know. > > Code review, testbenches, static timing analyses and formal > verification are the major verification tasks. Don't know which of them > makes sense for your designs and team. > > > One last doubt, in verification, do we even work on STATIC TIME > > ANALYSIS and SYNTHESIS. or this is done by the designer itself.. > > How could we know if you don't? STA is usually perfomed after layout, > has your designer feedback from layout? Do you have to verify after > layout or are you only responsible for functional verification until > synthesis? > > bye Thomas hi i was told to study corner case testing, different testing scenarios and BFM models. i have to test the design before the layout. before after synthesis not to sure... i wana get good knowledge regarding verification. can you help me with links that gives a brief idea related to testing... thanks ByeArticle: 92869
On a sunny day (Wed, 7 Dec 2005 13:47:03 -0000) it happened "hongying meng" <hm512@york.ac.uk> wrote in <dn6p4m$m8m$1@pump1.york.ac.uk>: >Hi, > >I will do some research on video/image processing on FPGA. I will design >VHDL codes for some video/image processing algorithms. I needs a FPGA >development board with a big FPGA chip on it. I also hope it can be >connected with a digital camera or image sensor with real-time image access >into the board. It's better if the image in RGB format and input to the >board frame by frame. > >Does any one know where there exist this kind of FPGA development board or >not? If not, any suggestion should be really appreciated. > >Thanks >Michael You could consider buying a webcam with ethernet rj45 interface. These have a build in web server (I use D-Link DCS-900) (<150$). Then find a FPGA board with ethernet interface. This camera sends jpeg picture stream. So.. then you have to process the jpeg (opencores?) and make TCP/IP HDL. Or use a custom ASIC... mmm Simpler is to use a RGB sensor on some IO pins.... Actually many of these sensors (CMOS) will sens some multiplexed form of YUV. All depends on what your idea of 'image processing' is. Anyways I think the ethernet cams are more fun then the USB (because of drivers). I have this cam also working in Linux, seesm very popular for home security (lot of downloads): http://panteltje.com/panteltje/mcamip/ No I am not associated with D-Link. > >Article: 92870
See below
rybol wrote:
> Hi,
>
> in my design I would like to have the possibility to switch beetween
> two
> clock signals: 'clk' (this is my main clock) and 'ext_clk' (the second,
>
> external clock) and the output clock is 'clk_out'. It all depends on
> one
> signal - let's call it 'temp'. 'Clk_out' is then used in the
> sensitivity
> list of some process ("process(clk_out) ..."). But when I code it in
> VHDL
> like this:
>
> clk_out <= clk when temp = '0' else ext_clk;
>
> in ISE I get the message that clk_out signal
> "is generated by combinatorial logic and XST is not able to identify
> which
> are the primary clock signals.
> Please use the CLOCK_SIGNAL constraint to specify te clock signal(s)
> generated by combinatorial logic.
> Some clock signals were not autmatically buffered by XST with BUFG/BUFR
>
> resources. Please use the buffer_type constraint in order to insert
> these
> buffers to the clock signals to help prevent skew problems."
>
> So how should I solve this problem correctly?
>
> Thanks in advance,
> Tomek
>
intantiate a BUFGMUX (from ISE tepmlates)
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFGMUX_VIRTEX4: Global Clock Buffer 2-to-1 MUX
-- Virtex-4
-- Xilinx HDL Language Template version 8.1i
BUFGMUX_VIRTEX4_inst : BUFGMUX_VIRTEX4
generic map (
INIT_OUT => 0, -- Inital value of 0 or 1 after configuration
PRESELECT_I0 => FALSE, -- TRUE/FALSE set the I0 input after
configuration
PRESELECT_I1 => FALSE) -- TRUE/FALSE set the I1 input after
configuration
port map (
O => O, -- Clock MUX output
I0 => I0, -- Clock0 input
I1 => I1, -- Clock1 input
S => S -- Clock select input
);
-- End of BUFGMUX_VIRTEX4_inst instantiation
Regards,
Aurash
Article: 92871http://www.xilinx.com/xcell/xl37/xcell37_54.pdfArticle: 92872
Hi, I'm trying to dynamically reconfigure a Virtex-4 FPGA, by following the example of XAPP 290. I'm following the module-based partial reconfig flow, but since the tools don't support generation of partial bitstreams, I use difference-based bitstreams to reconfigure the FPGA. The generation of full and partial bitstreams works perfectly, and I have no problem when downloading the initial bitstream to the chip. However, when I try to download a partial bitstream, I have the following warning message : Warning:iMPACT:2218 - Error shows in the status register, release_done bit is NOT 1. The FPGA pauses (it seems that the outputs are 3-stated) until I click ok "ok". When I read the status register after that, the done pin has the correct value. Does anyone have an idea about the cause of this warning ? Thanks, Denis PS : I'm using a VIRTEX-4 LX25 on an Avnet board, and I'm using a parallel cable IV in Boundary scan mode. I'm working with ISE 7.1 SP3. Here are my bitgen -g options : -g ActivateGCLK:Yes -g ReadBack -g DebugBitstream:No -g CRC:Enable -g ConfigRate:4 -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g DriveDone:No -g PowerdownPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullNone -g TmsPin:PullUp -g UnusedPin:PullUp -g UserID:0xFFFFFFFF -g DCMShutDown:Disable -g DisableBandgap:No -g StartUpClk:JtagClk -g DONE_cycle:4 -g GTS_cycle:Keep -g GWE_cycle:Keep -g LCK_cycle:NoWait -g Match_cycle:NoWait -g Security:None -g Persist:No -g ActiveReconfig:Yes -g DonePipe:No -g Encrypt:NoArticle: 92873
Hey, When all of these options (equivalent_register_removal + register_duplication + register_balancing) are enabled, they all work fine and do what they are supposed to do ... but because i don't want it to remove the equivalent registers, i disabled this option but now because of disabling equivalen_register_removal both register_duplication and register_balancing don't do anything anymore? ... are all of these features heavily related to each other???? thanks in advance for your reply, kind regards, Tim VerstraeteArticle: 92874
Eric, Ultracontroller II uses the I cache (instruction cache) for the program, and the D cache (data cache) for the data. The script will place the code, and the data in the right places (the internal PPC caches) for you (if you have written the program properly). It will execute entirely inside the PPC. I don't see an issue here. The BRAM won't be involved at all. Other than the clocking to the PPC, and the one 32 bit I/O port, it shouldn't require connecting up anything else (pretty small verilog or vhdl description of the hardware needed along with the UCII core: pretty much which pins go to which IO bits, and where does the system clock go into the chip). As soon as you want to go beyond the Ultracontroller II, you pretty much have to go into some depth, as you are then going to have to choose what kind of buses to use, and what kind of memories to add, along with what kind of IO. Decoding addresses, bus widths, connections, etc. gets busy quickly if you wish to "roll your own" PPC system. Which is why the UC II is so useful to so many. For those that like to build their own computer systems, the PPC + FPGA offers some real advantages as all the pins are there, all 1000+ of them. A bonded out PPC part will have less than 200 wires to connect, so the FPGA version is really much more versatile, and you can be doing both instruction and data fetches at the same time as the buses are all brought out separately. I suggest starting with UC II, and then seeing where is goes from there. You can easily end up with a uLinux system, flash cards, DDR2 memory, VGA, sound, UART, etc. if you go all out.... http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sSecondaryNavPick=BOARDS&key=HW-V4-ML403-USA&sGlobalNavPick=PRODUCTS&BV_SessionID=@@@@0876741742.1134056726@@@@&BV_EngineID=ccceaddggmkjgkhcefeceihdffhdfkf.0 or http://tinyurl.com/932uy which is also useful if you are developing a more complex embedded system. Austin reidek@gmail.com wrote: > Austin, > > If it's not obvious, I'm new to this, so bear with me. :) > > One of the things that I need to be able to do is create a calibration > table. The PPC would read a few values from the FPGA, and create a 8K > or so table, which seems to be within the limits of the ultracontroller > II. What I'm not sure of is whether the FPGA has access to the caches, > or whether I can write to some other block RAM with the PPC that the > FPGA would have access to. > > Sorry if this isn't quite making sense. I'm a software guy and haven't > worked with this stuff in a few years. Eventually, another team member > will be writing the VHDL/firmware and I'll be writing the software that > runs on the PPC. I've been tasked with figuring out how to program the > PPC and interface it with the firmware. No one at the company has done > this type of thing before, so I'm breaking "new ground". > > Eric >
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