Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Should I explicitly put them in highZ ? or is it done automatically by tools?Article: 92826
"Joseph Samson" <user@example.net> schrieb im Newsbeitrag news:SGDlf.32622$Zv5.27024@newssvr25.news.prodigy.net... >>>hongying meng wrote: >>> >>>>Hi, >>>> >>>>I will do some research on video/image processing on FPGA. I will design >>>>VHDL codes for some video/image processing algorithms. I needs a FPGA >>>>development board with a big FPGA chip on it. I also hope it can be >>>>connected with a digital camera or image sensor with real-time image >>>>access >>>>into the board. It's better if the image in RGB format and input to the >>>>board frame by frame. >>>> >>>>Does any one know where there exist this kind of FPGA development board >>>>or >>>>not? If not, any suggestion should be really appreciated. > > Pixel Velocity makes a 'Brilliant Camera' with an AltaSens HDTV color > sensor, Virtex2Pro XC2VP20, XC2VP30 or XC2VP50, 10/100 or Gigabit > Etghernet and runs embedded Linux. > > http://pixel-velocity.com/intelligentcamera.html > > > --- > Joe Samson > Pixel Velocity or http://www.elphel.com/model313/ :) possible less expensive and with design sources c verilog schematice available for downloads for FREE AnttiArticle: 92827
>Hi, Jered, I tried months before to use MIG007 generating a DDR controller for ML310, failed and the xilinx support did not help to get through. I modified everything to fit ml310 kit and when I download the generated testbench, nothing happened in the DDR. You can discuss with me by: xjf77(at)yahoo.com. regards > I am running MIG DDR rel6 on the ML310. You need to work around to connect rst_dqs_div_in and rst_dqs_div_out outside of FPGA.Article: 92828
>Hi, Jered, I tried months before to use MIG007 generating a DDR controller for ML310, failed and the xilinx support did not help to get through. I modified everything to fit ml310 kit and when I download the generated testbench, nothing happened in the DDR. You can discuss with me by: xjf77(at)yahoo.com. regards > Hi, all, I forgot to tell you guys something. MIG DDR support only unbuffered DIMM as far as I know. The DIMM coming with ML310 is buffered DIMM. In my case, I replaced DIMM and it works fine.Article: 92829
Hi, 1. I want to know how to deal with marginal data for mean value filter, the pixels that cannot get full 9 neighboring pixels in general. 2. What is the best algorithm for mean value filter? Where is the related paper? 3. what book is the best one describing under what conditions mean value filter is useful? Thank you. WengArticle: 92830
Thank you Steven, I will make sure this happens, assuming we post an external web site and that the papers aren't copyright of any ACM/IEEE conference. Good suggestion for us to follow-up on. Regards, Stephen Steven Derrien wrote: > Stephen a =E9crit : > > > > Ps we don't have an external web page, yet, but we are evaluating > > options, so please send us suggestions if there's something specific > > you'd like to see. > > My 2 cents, > > Maybe electronic versions of xilinx publications in academic > conferences, for those who are not registered at ACM/IEEE digital librari= es. >=20 > Regards, >=20 > Steven >=20 > >=20 > >Article: 92831
"GaLaKtIkUsT" <taileb.mehdi@gmail.com> schrieb im Newsbeitrag news:1133972647.110369.251840@g49g2000cwa.googlegroups.com... > Should I explicitly put them in highZ ? or is it done automatically by > tools? > depends on the tools, usually you can select what state the unconnected IOs will be either pulldown, pullup or floating anttiArticle: 92832
All, Is it possible to run programs on the embedded PowerPC in the Xilinx chips without external RAM and/or operating system? The PPC will only be doing some minor work and it would be much better if we can get away with not putting any RAM on the boards. The ideal would be to store the instructions in block RAM on the FPGA and then trigger the PPC to run. Is this possible? Thanks! EricArticle: 92833
Stephen wrote: > Thank you Steven, > I will make sure this happens, assuming we post an external web site > and that the papers aren't copyright of any ACM/IEEE conference. Good > suggestion for us to follow-up on. > Regards, > Stephen IEEE have no problem with their articles being made available provided a covering copyright document is included (electronically!), available from their website. Xilinx's IEEE documents would be very useful in a centralised location. The website might also provide the names of Xilinx's research interests/projects/topics, even if it does not provide exact details... obviously you dont want to give the game away, but it would be nice to know what Xilinx is interested in, in general. Cheers PorterboyArticle: 92834
<reidek@gmail.com> schrieb im Newsbeitrag news:1133978811.647548.193560@g43g2000cwa.googlegroups.com... > All, > > Is it possible to run programs on the embedded PowerPC in the Xilinx > chips without external RAM and/or operating system? The PPC will only > be doing some minor work and it would be much better if we can get away > with not putting any RAM on the boards. The ideal would be to store > the instructions in block RAM on the FPGA and then trigger the PPC to > run. Is this possible? > > Thanks! > > Eric > sure, look at the ultracontroller II at xilinx website ! AnttiArticle: 92835
Hello, I am trying to use PLX9056 as an interface between PCI bus and local bus, in manner as simple as possible. I would fill some SRAM on the local bus with certain amount of data (256 or 8K or 32K or 64K words) from uP or FPGA and then tell PLX to take that data and transfer it to PCI bus. The transfer may also need to go in the opposite direction, i.e. PLX filling the SRAM and telling my uP/FPGA that the data is ready. Arbitration may be handled on local bus side by an FPGA, but I do not know how to establish the communication between uP/FPGA and PLX. Is there a group of registers where size of data for burst transfer can be defined? How to tell PLX that the data is ready for transfer? How does the PLX tell uP/FPGA on local bus that data has arrived from PCI bus? Help would be greatly appreciated. Regards, AlexArticle: 92836
most PCIe PHY datasheets are still under NDA, but Marco Groeneveld has already made freely available the schematic of the SENDERO board that includes the PX1011A chip with its connection - downloadable from http://www.fpga.nl/ and PLX tech just announced PCIe to generic local bus bridge PEX8311, it looks like having 4 GPIOs so those could be used to bootstrap FPGA ? AnttiArticle: 92837
damir wrote: > I'm looking for simple VGA (XGA up to 800x600) controller for displaying > simple images on the LCD pannel - any suggestion for available ASIC (LCD > controller) or FPGA (VHDL core) design will do. Thanks, > > Damir http://www.dontronics.com/micro-vga.html is one solution Don... -- Don McKenzie E-Mail Contact Page: http://www.dontronics.com/e-mail.html Micro,TTL,USB to 1.5" color LCD http://www.dontronics.com/micro-lcd.html USB,RS232 or TTL to VGA Monitor http://www.dontronics.com/micro-vga.html World's smallest USB 2 TTL Conv http://www.dontronics.com/micro-usb.htmlArticle: 92838
Ultracontroller II runs code out of the processor cache and not the Block RAMs. You can easily create PPC405 systems using only BRAMs using Base System Builder. However, If you are looking to do something simple with the PPC405, Antti's suggestion (Ultracontroller II) is best. Besides the appnote, there is a video demonstration of Ultracontroller I at http://www.demosondemand.com/dod/proddemos/vendors/pd_xilinx.aspx by Glenn Steiner. Kunal Antti Lukats wrote: > <reidek@gmail.com> schrieb im Newsbeitrag > news:1133978811.647548.193560@g43g2000cwa.googlegroups.com... > >>All, >> >>Is it possible to run programs on the embedded PowerPC in the Xilinx >>chips without external RAM and/or operating system? The PPC will only >>be doing some minor work and it would be much better if we can get away >>with not putting any RAM on the boards. The ideal would be to store >>the instructions in block RAM on the FPGA and then trigger the PPC to >>run. Is this possible? >> >>Thanks! >> >>Eric >> > > > sure, look at the ultracontroller II at xilinx website ! > > Antti > >Article: 92839
Alex wrote: > I am trying to use PLX9056 as an interface between PCI bus and local bus I like the PLX chips. I have used the 9060 and the 9054. > Is there a group of registers where size of data for burst transfer can be > defined? Use the dma engine on the plx chip. The chip has registers to set up source, destination and size. > How to tell PLX that the data is ready for transfer? Set the register to start the dma. > How does the PLX tell uP/FPGA on local bus that data has arrived from PCI bus? You have many options: 1. Use the mailboxes in the plx chip. Interrupt or polled. 2. Use a register in the fpga. Interrupt or polled. 3. Set the dma to write a location in memory when done and poll that. 4. Poll the dma registers to see when dma is done. 5. Set the dma to interrupt when done. 6. Use EOT# end of transfer pin. PLX has an sdk so you don't even have to write a windows driver. Alan NishiokaArticle: 92840
It is the first entry under "embedded processor solutions" . UltraController is mentioned in the text, but not in the title. http://www.demosondemand.com/dod/proddemos/vendors/pd_xilinx.aspx Peter AlfkeArticle: 92841
svasus@gmail.com wrote: > Hi all, > > I am needed to talk with a microcontroller through an I2C interface > from my FPGA. I dont want to write a code for it as well not use an > opensource core. This is partly due to space constraints and testing. > Speed and cost are not constraints. > So I was hoping to find a chip which would sandwich between the FPGA > and I2C interface. > Searched on the net but could not find any. If anyone has suggestions > please let me know. Look at i2c BUS controllers from Philips http://www.semiconductors.philips.com/similar/PCF8584.html and the PCA9564 is a candidate. These take a parallel uC BUS and connect to i2c - so you will need to load some config registers, from the FPGA, but not many. This device goes to ~400KHz You could also look at any small uC that has separate SPI and i2c HW - eg Philips LPC916 in TSSOP16, or most Silabs C8051F3xx devices and are about the same price as the 9564- and you get ADC/DAC and proper buffering, for free... -jgArticle: 92842
Excellent, thanks for the suggestions. I should be getting my eval board in the next couple of days, so this will get me going in the right direction. While I'm waiting, I do have another quick question. Can I write to BRAM when using the Ultracontroller? Part of the working I'm hoping to have the PPC do is calculating calibration data that the FPGA will use. Will I have to use the Base System Builder to do something like this? Thanks again! EricArticle: 92843
<svasus@gmail.com> wrote in message news:1133949644.536667.201480@z14g2000cwz.googlegroups.com... > So I was hoping to find a chip which would sandwich between the FPGA > and I2C interface. > Searched on the net but could not find any. That should tell you something then. Like nobody does it that way, for good reasons. There are some controller chips but you have to write code to use them. And if you can do that, you might just as well write the code to bit-bash the I2C interface. Come on, it isn't that hard to do.Article: 92844
Eric, The Ultracontroller II runs on a small c-program that you write, and then compile, and gets placed in the cache. If you also use less than 16 kbytes of memory space for some data (in the form of an data array), then if you can fit the program in 16 kbytes, and the data in 16 kbytes (the space alloted by the Ultracontroller II caches), it should work fine. There is a fixed 32 bit input/output port (one) associated with the Ultracontroller, so the I/O is pretty thin as well. The intent was to be able to use the PPC for simple tasks that didn't require a lot of code space, I/O space, or data space without using up FPGA resources. Ultracontroller I (the original) used BRAM for code and data, which meant that the 18 Kbit memory when used 32 bits wide held very little code (data) without piling up a lot of BRAMs. http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=UltraController Austin reidek@gmail.com wrote: > Excellent, thanks for the suggestions. I should be getting my eval > board in the next couple of days, so this will get me going in the > right direction. > > While I'm waiting, I do have another quick question. Can I write to > BRAM when using the Ultracontroller? Part of the working I'm hoping to > have the PPC do is calculating calibration data that the FPGA will use. > Will I have to use the Base System Builder to do something like this? > > Thanks again! > > Eric >Article: 92845
Austin, If it's not obvious, I'm new to this, so bear with me. :) One of the things that I need to be able to do is create a calibration table. The PPC would read a few values from the FPGA, and create a 8K or so table, which seems to be within the limits of the ultracontroller II. What I'm not sure of is whether the FPGA has access to the caches, or whether I can write to some other block RAM with the PPC that the FPGA would have access to. Sorry if this isn't quite making sense. I'm a software guy and haven't worked with this stuff in a few years. Eventually, another team member will be writing the VHDL/firmware and I'll be writing the software that runs on the PPC. I've been tasked with figuring out how to program the PPC and interface it with the firmware. No one at the company has done this type of thing before, so I'm breaking "new ground". EricArticle: 92846
Kryten wrote: > <svasus@gmail.com> wrote in message > news:1133949644.536667.201480@z14g2000cwz.googlegroups.com... > >>So I was hoping to find a chip which would sandwich between the FPGA >>and I2C interface. >>Searched on the net but could not find any. > > > That should tell you something then. > > Like nobody does it that way, for good reasons. > > There are some controller chips but you have to write code to use them. > And if you can do that, you might just as well write the code to bit-bash > the I2C interface. Come on, it isn't that hard to do. That depends - if you want to bit-bash, on a FPGA that infers a SoftCPU, and that is resource intensive. First, you need to have this CPU, then you need the time/code resource to service i2c. Also, i2c slave is non trivial, and the external chip does it already ( or, the OP might need 5V compliant i2c, not so easy on FPGAs ! ) Thus a parallel controller could be INIT and serviced with a simple statemachine, but I would favour a small uC as a SPI-i2c buffered bridge, as that can be smarter, and has less pin-cost ( but that does have another development cycle of its own) -jgArticle: 92847
vasudev srinivasan wrote: > I am needed to talk with a microcontroller through an I2C interface > from my FPGA. I dont want to write a code for it as well not use an > opensource core. This is partly due to space constraints and testing. > Speed and cost are not constraints. > So I was hoping to find a chip which would sandwich between the FPGA > and I2C interface. Antti Lukats wrote: > there is no such thing. Certainly there is! Look for the Philips PCF8584 or PCA9564.Article: 92848
I2C is not particularly resource intensive, especially if only a subset of the full spec is used. It can be incorporated in the FPGA fabric without a huge development effort, and with modern FPGAs is going to take but a small corner of the FPGA. For the slave side, which it sounds like you are, the decode and data steering is probably bigger than the shift register and state machine.Article: 92849
Hi, I have a design for a Virtex 4 SX35-10 that is not meeting my timing constraints. The only constraint is set in the ucf file as a clock period of 4.75 ns. Synthesis gives the following: Timing Summary: --------------- Speed Grade: -10 Minimum period: 7.680ns (Maximum Frequency: 130.213MHz) Minimum input arrival time before clock: 1.890ns Maximum output required time after clock: 5.810ns Maximum combinational path delay: 0.000ns Doing a post map static timing analysis gives the following as the first error. (place and route fails) Source: uut1/overlapadd1/fifo1/BU2/U0/ss/memblk/fifo_generator_v2_2_fifo_generator_v2_2_xst_1_coreinst/fifo_generator_v2_2_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst/bm/mem/arch_v2/prim/4/b1/chk0/col/0/b2/mextd/arch_v2/c1/ram1/v2/d4096/by4/newSim8/RAMB16 (RAM) Destination: uut1/overlapadd1/f2_data_in_sig_0_BRB2 (FF) Requirement: 4.750ns Data Path Delay: 5.522ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: fast_clk rising at 0.000ns Destination Clock: fast_clk rising at 4.750ns Clock Uncertainty: 0.060ns Does the post map report include estimates of routing delays? Can I constrain XST to provide better results, if so how? Is 210 MHz too fast for this speed grade FPGA? Running XST with higher effort does not seem to help. thanks
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z