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> Hello John.... > for example... > > ADDRESS =A0 =A0 =A0 =A000 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F > INITIAL DATA =A0 =A012 FF FA DE 32 25 25 17 14 25 DA 11 BC 67 FE A2 > > If I try to write in address 00 , 01, 02, etc > > ADDRESS =A0 =A0 =A0 =A000 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F > DATA WRITTEN 01 23 45 67 89 AB CD EF 11 22 33 44 55 66 77 88 > > If I read the result after writting. > > ADDRESS =A0 =A0 =A0 =A000 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F > DATA WRITTEN 45 67 FA DE CD EF 25 27 33 44 DA 11 77 88 FE A2 > > If you do this all along the memory the effect is the same. > All the timing parameters are correct and I've checked with an > oscilloscope the signals and seems to be correct also. > > Any idea?. > Thanks What are the burst length and burst interleaving parameters for the SDRAM, and do you get the same behavior if you change them? DaveArticle: 135226
The paired MDI signals from the PHY to the magnetics in a GbE application are each terminated by a 50R resistor and then together to a 10nF capacitor to GND. However some applications connect the 2 resistors to Vcc (2.5V) as well. Can anyone explain why some configurations are like this and others aren't? Is it something specific to the magnetics? TIA, Rog.Article: 135227
Eric Smith wrote: > Jon Elson wrote: >> That looks pretty much like a 32-bit CPU to me. The CPUs read out as : > [...] >> model name : Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz > > The Core 2 Duo is a 64-bit CPU. Yes, as you say, I now know it is a 64 bit system. You can install either 32-bit or 64-bit > Linux on it. Do a 'uname -p' to find out whether you are running an > i386 or x86_64 kernel. It IS a 64-bit kernel. > > If you're running x86_64, you can install WebPACK but you'll have to > force it to install the 32-bit version instead of the 64-bit version > (since the latter isn't actually provided in WebPACK). This used to > require either editing one of the Xilinx scripts involved early in > the setup process, or skipping that script and invoking the 32-bit > installer directly. Perhaps in newer versions of WebPACK they may > have come up with a cleaner way to do it. We have a site license for the full ISE, so I'm working on getting that installed, now. Thanks for all the help! JonArticle: 135228
Lorenz Kolb wrote: > Well not exactly, I'd say that if some microphone amplifier etc. is > connected to the FPGA in some way (and no microphone is connected) the > LSB of samples aquired (assuming some reasonable temperature-range) will > be quite random (and equally distributed). > That could be quite a good source for initiallly feeding some shifting > registers... There used to be some fairly simple circuits used in toys, etc. for explosion sounds, using a reverse-biased BE junction (bipolar junction transistors, anyone remember those?) and an op-amp amplifier to produce audio noise. Hooking one of those to an ADC, maybe even a sound card, should produce something that has true randomness. JonArticle: 135229
On 22 sep, 10:27, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > Jaime Andr=E9s Aranguren Cardona wrote: > > > > > > > Hello, > > > I want to make a Virtex-II Pro on the Xilinx XUPV2P (http:// > >www.xilinx.com/univ/xupv2p.html, > >http://www.digilentinc.com/Products/Detail.cfm?Nav1=3DProducts&Nav2=3DPr= o...) > > talk to an Stratix GX on the Altera High-Speed Development Kit, > > Stratix GX Edition (http://www.altera.com/literature/ug/ > > ug_stx_gx_hs_dev_kit.pdf?GSA_pos=3D1&WT.oss_r=3D1&WT.oss=3DHigh-Speed > > %20Development%20Kit,%20Stratix%20GX%20Edition). I want the > > communication be fast, using the gigabit transcievers on those FPGAs. > > > I am aware that Xilinx has Aurora and Altera has SerialLite-II. > > However, are those protocols compatible with each other? Will simply a > > point to point connectio with SMA (connector and cable) work for my > > purpose? Will that communication be bidirectional though the same > > cable, or will it need separate point to point connection in each > > direction? > > > I am a completely newbie to gigabit transceivers, and also rather new > > to Altera brand, wlthough have used Xilinx for many years. I will > > appreciate your advice. > > > Kind regards for your fast reply. > > > -- > > > JaaC > > Aurora and SerialLite-II are not the same protocol so they are not > compatible. =A0You will need to decided what protocol you want to use and > implement it in each device. > > On the connection side you need will 4 coax cables to connect the > TXP/TXN pairs to the RXP/RXN pairs. =A0You should also check to see that > AC coupling is used in each direction to ensure correct signaling levels > for each device. > > Ed McGettigan > -- > Xilinx Inc- Ocultar texto de la cita - > > - Mostrar texto de la cita - Ed, Thanks for the response. Now the issue is how to proceed: Aurora is part of LogiCore and SerialLite-II is part of Megacore, in both of the cases those are out of the box blocks generated through a wizard, and are vendor dependent. How can I make the StratixGX talk to the Virtex-II Pro using the gigabit transceivers on each device? What steps have to be done? Thank you for the advice, -- JaaCArticle: 135230
Hello all,
I'm pleased to announce the release of Avalda FPGA Developer v1.0
beta! It enables one to compile regular F# to RTL with parallel
programming semantics. Our aim is to help make FPGAs available to a
wider group of software programmers who may not have as much
experience with HDLs or FPGAs. Please visit Avalda's site to download
the beta and check out the blog!
cheers,
Stephen Afande
Avalda Corp.
http://www.avalda.com
Article: 135231On Sep 15, 5:24=A0am, michael...@gmx.de (Michael Dreschmann) wrote: > On Fri, 12 Sep 2008 11:12:17 -0700 (PDT), rickman <gnu...@gmail.com> > wrote: ...snip... > > > As said in the other post, we probably have something around 300mW for > the whole system and we want to see whats possible with this amount. > But this also includes Videosensors, some actors (buffered by > capacitors) and so on. I don't know what "actors buffered by capacitors" means. But I assume it means that what ever it is, it does not figure into the power estimates. > >BTW, a manchester encoder/decoder is typically a *very* small design, > >so even at 200 MHz, it won't use much power. > > Also this is not fixed, in the last design we used manchester in a > CPLD but if we have an FPGA we can use more complicated codes. It's > all about "what we can archive at maximum with the given power and > there I thing a low power FPGA can do more than any processor oder > CPLD. Sandby is not important, an MSP controller will disconnect the > PLD vom power if not used. Well, if you want to estimate things, you have to identify what you want to estimate. Otherwise you are asking, "how long is a piece of string?" > >In a nutshell this is what you are likely to find. =A0So can you live > >with around 100 mA active current or do you need to keep looking and/ > >or consider a CPLD? > > 100mA would be to much, Siliconblue stated for one of their smaler > parts around 8mA for a completely with counters filled FPGA at 32 MHz. > This would be an acceptable value. Unfortunately it seems that's > impossible to test their designsoftware without a licence to see what > fits exactly in such a part. The SiBlue parts are based on 4 input LUTs like the other, right? So a design done in any part will be about the same as long as it does not use any special features of the chips. So try the Altera freeware and see what designs will fit in a given number of LUTs. As to power, if you are limited to 300 mW, you *can* use anyone's FPGAs. I said Spartan III's (for example) use around 100 mA idling. That is only 120 mW or maybe a bit more since some of the current is from the 3.3 volt supply. The Lattice XP parts are fairly low power also running around 100 mW idle for the smallest part. You are putting the cart before the horse. You have a first order estimate of power consumption. Now you need to pick a few algorithms and estimate how many LUTs/FFs they will use and from that estimate the power consumption. I know Lattice and Altera provide equations as well as tools for power estimating. The tools are good for detailed analysis and the equations are useful for getting a ballpark figure. > >If you really need to know how low the power is, > >you need to figure out just how large your design is. =A0I don't know > >your constraints working at the University, but in a commercial > >application, if we don't have good info on the FPGA design we want, it > >would be prototyped in an eval board before we would attempt to spec > >any hardware. =A0Is there a reason that you need to spec your hardware > >before you know what it will be hosting? > > Yes, the plattform with the FPGA is powered optically and we have a > given amount of power and want to figure out what we can do with that > power. So the goal is not to solve a given problem with minimum power > but to see what problems can be solved with a given power. > In the last time I heard many times about the Actel Igloo, maybe they > will find their way into our design. Has anyone experience with the > siliconblue parts? SiBlue is very new. I doubt that you will find many with any experience and none with a lot! The Actel parts are very low *standby* power. I have not read the data sheets in detail, but I have not seen any indication that they are any better at active power than parts from the other vendors. RickArticle: 135232
On Sep 21, 6:55=A0pm, hei...@iname.com wrote: > I recently purchased a Xilinx Spartan II development kit fromwww.easyfpga= .com. > My intention is to use the board to generate a BPSK modulated > intermediate frequency. I want to connect an output pin directly to a > lowpass filter (e.g. this one:http://www.mini-circuits.com/pdfs/BLP-10.7+= .pdf > ) that has a 50 ohm input. > > Let's say I generate a sequence of 1's and 0's at a sample rate of 20 > MHz. If I consider this an analog signal it is a 10 MHz square wave. > This square wave has frequency components at 10, 30, 50, 70 etc. MHz. > If the output voltage is +3.3 VDC for a 1, and 0 for VDC for a 0 then > there is also a DC bias. If I lowpass filter this signal I should end > up with a 10 MHz sine wave plus the DC bias. If I then block the DC > with a capacitor I should have a 10 MHz sine wave centered at 0 > volts...right? > > The Xilinx documentation says I can choose from a variety digital > outputs, for example LVTTL. My question is can I just connect the > center pin of my coax to the output pin of the FPGA board, and ground > the shield conductor? Do I need some sort of impedence matching? How > do I do that? AS Joseph indicated, the output should be reasonably compatible with a 50 ohm load, but you may want to add a series resistor which will reduce the amplitude. This will be determined by whether you are terminated at the far end with a parallel 50 ohm load. If not, you will want to use the series matching resistor. The low pass filter will not give you a sine wave. It will approximate one, but with 20 MHz components on a 10 MHz signal, you will not be able to fully filter it out. If you pay attention to the signal integrity issues, the signal should at least rise and fall monotonically. RickArticle: 135233
Kevin Neilson <kevin_neilson@removethiscomcast.net> writes: > thutt wrote: > > Hello everyone, > > I'm tired of using the Xilinx ISE to look at RTL schematics, mainly > > because it's so slow and cumbersome to use. What I'd like to do is > > output a netlist and use another script to process that netlist into > > input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html). > > I have figured out how to get the Xilinx tools to output a netlist, > > but it appears they output a 'technology' version and not an 'RTL' > > version of the netlist. > > Is there any way to get the tools to output a netlist that is in the > > more useful (to me) 'RTL' format? > > My desire is to be able to write VHDL code, build it with my build > > process and check the RTL without ever having to enter Xilinx's IDE. > > I'd also like to be able to easily extract schematics for inclusion > > into the chronicle of my personal project at > > http://www.harp-project.com/, but the Xilnix tools make this > > incredibly difficult. > > Thanks for any info, > > thutt > > > I think the RTL schematic is in a proprietary format. I don't know if > it's possible to view it in another tool. If you want a better viewer > for the technology schematic, you can import the NGC into PlanAhead, > which now comes with ISE. If you want a better RTL viewer, you > probably have to resynthesize with a different synthesizer and view > the schematic in that tool. -Kevin I don't understand how the RTL can be in a proprietary format, if I'm reading the technology schematic correctly. As far as I can tell, each LUT in the technology schematic represents some level of 'complex' logic which can be viewed in RTL form by double clicking on the LUT in the technology schematic viewer. Each LUT also has an associated initialization value, a 16-bit hexadecimal number; I assume that the initialization value is the key which turns the lock and causes the LUT to implement a certain functionality. If that's the case, has anyone spent the time to figure out the mappings of initialization codes to LUT implementations? Or, does Xilinx publish this information? (I seem to recall a post in either this newsgroup or comp.lang.vhdl which described how this was derived, but I don't recall if it went into any specificity with regards to Xilinx initialization values). If there were a lookup table of initialization values to the standard 'and / or / xor'-type logic that each represents, then it would be quite possible to write a script to make an external RTL viewer based on the technology netlist output by the Xilinx tools. Anyone game for a little sleuthing to determine all the LUT init codes? thutt -- I have never met a beet which I like.Article: 135234
On Sep 22, 10:23=A0am, Rob <BertyBoos...@googlemail.com> wrote: > On Sep 20, 7:43=A0pm, m <martin.use...@gmail.com> wrote: > > > I've been told that Altera has patented I/O technology that makes DDR3 > > interfacing "better" (in quotes because that could mean anything). =A0I > > received this answer when I asked about DDR3 support since we are > > considering migrating from Xilinx to Altera. =A0The answer was that > > Altera, due to this technology, is able to support DDR3 at 533MHz > > clock rate while Xilinx seems to be tentative about 400MHz support. > > > What's the real story? > > > -Martin The two features that are new in Stratix III and Stratix IV devices to make DDR3 interfacing easier/possible are: 1. Read and write leveling circuitry. As Rob said, this makes interfacing to DDR3 DIMMs feasible. It compensates for the fact that the clocks on DDR3 dimms are routed in a "fly-by" topology rather than as a tree. This means there is a different clock delay to each memory chip (which is a pain), but it helps signal integrity because you can terminate this line properly (while you can't terminate a tree well). To deal with the fact that each memory chip has a different clock delay, you need "read leveling" circuitry in your I/Os to get all the data from various DQS groups (which came from different memory chips) lined up on a single clock edge so you can send it in to your design. You also need "write leveling" circuitry to skew the write data from the FPGA to meet the tDQSS spec of the memory chip. 2. Dynamic on-chip termination. For the best signal integrity, you really want to have your FPGA I/O act as a resistor when it is reading from the memory chip. But you don't want a parallel resistor when the FPGA is writing to the memory chip or sending commands; that just wastes power, and hurts signal integrity. Dynamic on-chip termination solves this -- it make the I/O behave like a resistor to Vtt during a read, and makes it an impedence matched driver when it is writing to the memory. See http://www.altera.com/literature/wp/wp-01034-Utilizing-Leveling-Techniq= ues-in-DDR3-SDRAM.pdf for more detail. Hope this helps. Vaughn Betz Altera [v b e t z (at) altera.com]Article: 135235
I am new to this area and trying to learn the baics. I understand what duty cycle is but really want to know it's significance in digital design. I have designed a clock divider as part of my first project (UART). If the clock divider is set to divide by 10 I have an output clock that is ON for one pulse and OFF for ten pulses so the output duty cycle is 10%. I can modify the HDL to make it ON for five pulses and again OFF for the next five pulses and achieve 50% duty cycle with the same clock rate. In either cases I would like to know the impact (not necesarily for UART but in general to the digital systems) and what is the significance of duty cycle and what difference does it make make to digital systems?Article: 135236
First, your 10% duty cycle example isn't correct, you gave a duty cycle of 1/11. The impact duty cycle has depends on the edge rate of the clock signal and the frequency of the clock signal. You want to even-out your duty cycle so that pulses are "easier to detect". I am sure there are other important issues, especially as transmission lines are concerned, but I don't have the knowledge to accurately describe the effects. ---Matthew Hicks > I am new to this area and trying to learn the baics. I understand what > duty cycle is but really want to know it's significance in digital > design. I have designed a clock divider as part of my first project > (UART). If the clock divider is set to divide by 10 I have an output > clock that is ON for one pulse and OFF for ten pulses so the output > duty cycle is 10%. I can modify the HDL to make it ON for five pulses > and again OFF for the next five pulses and achieve 50% duty cycle with > the same clock rate. In either cases I would like to know the impact > (not necesarily for UART but in general to the digital systems) and > what is the significance of duty cycle and what difference does it > make make to digital systems? >Article: 135237
On 22 sep, 17:02, Jaime Andr=E9s Aranguren Cardona <jaime.arangu...@gmail.com> wrote: > On 22 sep, 10:27, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > Jaime Andr=E9s Aranguren Cardona wrote: > > > > Hello, > > > > I want to make a Virtex-II Pro on the Xilinx XUPV2P (http:// > > >www.xilinx.com/univ/xupv2p.html, > > >http://www.digilentinc.com/Products/Detail.cfm?Nav1=3DProducts&Nav2=3D= Pro...) > > > talk to an Stratix GX on the Altera High-Speed Development Kit, > > > Stratix GX Edition (http://www.altera.com/literature/ug/ > > > ug_stx_gx_hs_dev_kit.pdf?GSA_pos=3D1&WT.oss_r=3D1&WT.oss=3DHigh-Speed > > > %20Development%20Kit,%20Stratix%20GX%20Edition). I want the > > > communication be fast, using the gigabit transcievers on those FPGAs. > > > > I am aware that Xilinx has Aurora and Altera has SerialLite-II. > > > However, are those protocols compatible with each other? Will simply = a > > > point to point connectio with SMA (connector and cable) work for my > > > purpose? Will that communication be bidirectional though the same > > > cable, or will it need separate point to point connection in each > > > direction? > > > > I am a completely newbie to gigabit transceivers, and also rather new > > > to Altera brand, wlthough have used Xilinx for many years. I will > > > appreciate your advice. > > > > Kind regards for your fast reply. > > > > -- > > > > JaaC > > > Aurora and SerialLite-II are not the same protocol so they are not > > compatible. =A0You will need to decided what protocol you want to use a= nd > > implement it in each device. > > > On the connection side you need will 4 coax cables to connect the > > TXP/TXN pairs to the RXP/RXN pairs. =A0You should also check to see tha= t > > AC coupling is used in each direction to ensure correct signaling level= s > > for each device. > > > Ed McGettigan > > -- > > Xilinx Inc- Ocultar texto de la cita - > > > - Mostrar texto de la cita - > > Ed, > > Thanks for the response. Now the issue is how to proceed: Aurora is > part of LogiCore and SerialLite-II is part of Megacore, in both of the > cases those are out of the box blocks generated through a wizard, and > are vendor dependent. > > How can I make the StratixGX talk to the Virtex-II Pro using the > gigabit transceivers on each device? What steps have to be done? > > Thank you for the advice, > > -- > JaaC- Ocultar texto de la cita - > > - Mostrar texto de la cita - Hi guys, After reading a bit the documentation from both vendors, it seems that using the RapidIO Megacore (A) and LogiCore (X) will be the way to communicate both boards. My concern now is about the physical connections: - How many cables will I need? - How should they be connected? - What is the maximum length they can have for reliable communication at 1.25 Gbps? Regards, -- JaaCArticle: 135238
On Sep 23, 2:03=A0am, vaughnb...@gmail.com wrote: > On Sep 22, 10:23=A0am, Rob <BertyBoos...@googlemail.com> wrote: > > > On Sep 20, 7:43=A0pm, m <martin.use...@gmail.com> wrote: > > > > I've been told that Altera has patented I/O technology that makes DDR= 3 > > > interfacing "better" (in quotes because that could mean anything). = =A0I > > > received this answer when I asked about DDR3 support since we are > > > considering migrating from Xilinx to Altera. =A0The answer was that > > > Altera, due to this technology, is able to support DDR3 at 533MHz > > > clock rate while Xilinx seems to be tentative about 400MHz support. > > > > What's the real story? > > > > -Martin > > The two features that are new in Stratix III and Stratix IV devices to > make DDR3 interfacing easier/possible are: > > 1. =A0Read and write leveling circuitry. =A0As Rob said, this makes > interfacing to DDR3 DIMMs feasible. =A0It compensates for the fact that > the clocks on DDR3 dimms are routed in a "fly-by" topology rather than > as a tree. =A0This means there is a different clock delay to each memory > chip (which is a pain), but it helps signal integrity because you can > terminate this line properly (while you can't terminate a tree well). > To deal with the fact that each memory chip has a different clock > delay, you need "read leveling" circuitry in your I/Os to get all the > data from various DQS groups (which came from different memory chips) > lined up on a single clock edge so you can send it in to your design. > You also need "write leveling" circuitry to skew the write data from > the FPGA to meet the tDQSS spec of the memory chip. > > 2. =A0Dynamic on-chip termination. =A0For the best signal integrity, you > really want to have your FPGA I/O act as a resistor when it is reading > from the memory chip. =A0But you don't want a parallel resistor when the > FPGA is writing to the memory chip or sending commands; that just > wastes power, and hurts signal integrity. =A0Dynamic on-chip termination > solves this -- it make the I/O behave like a resistor to Vtt during a > read, and makes it an impedence matched driver when it is writing to > the memory. > > Seehttp://www.altera.com/literature/wp/wp-01034-Utilizing-Leveling-Techn.= .. > for more detail. > > Hope this helps. > > Vaughn Betz > Altera > [v b e t z (at) altera.com] OK, well I was half right ;-) Interestingly, Xilinx do appear to have some kind of implementation for dynamic termination. SSTL18_II_T_DCI appeared in the user guide recently and removes the parallel termination when tri-stated. I've tried to use this, but unfortunately it couldn't be mixed with DIFF_SSTL18_II_DCI nets I had on the same bank.Article: 135239
thutt wrote: > Kevin Neilson <kevin_neilson@removethiscomcast.net> writes: > >> thutt wrote: >>> Hello everyone, >>> I'm tired of using the Xilinx ISE to look at RTL schematics, mainly >>> because it's so slow and cumbersome to use. What I'd like to do is >>> output a netlist and use another script to process that netlist into >>> input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html). >>> I have figured out how to get the Xilinx tools to output a netlist, >>> but it appears they output a 'technology' version and not an 'RTL' >>> version of the netlist. >>> Is there any way to get the tools to output a netlist that is in the >>> more useful (to me) 'RTL' format? >>> My desire is to be able to write VHDL code, build it with my build >>> process and check the RTL without ever having to enter Xilinx's IDE. >>> I'd also like to be able to easily extract schematics for inclusion >>> into the chronicle of my personal project at >>> http://www.harp-project.com/, but the Xilnix tools make this >>> incredibly difficult. >>> Thanks for any info, >>> thutt >>> >> I think the RTL schematic is in a proprietary format. I don't know if >> it's possible to view it in another tool. If you want a better viewer >> for the technology schematic, you can import the NGC into PlanAhead, >> which now comes with ISE. If you want a better RTL viewer, you >> probably have to resynthesize with a different synthesizer and view >> the schematic in that tool. -Kevin > > I don't understand how the RTL can be in a proprietary format, if I'm > reading the technology schematic correctly. As far as I can tell, > each LUT in the technology schematic represents some level of > 'complex' logic which can be viewed in RTL form by double clicking on > the LUT in the technology schematic viewer. > > Each LUT also has an associated initialization value, a 16-bit > hexadecimal number; I assume that the initialization value is the key > which turns the lock and causes the LUT to implement a certain > functionality. > > If that's the case, has anyone spent the time to figure out the > mappings of initialization codes to LUT implementations? Or, does > Xilinx publish this information? (I seem to recall a post in either > this newsgroup or comp.lang.vhdl which described how this was derived, > but I don't recall if it went into any specificity with regards to > Xilinx initialization values). > > If there were a lookup table of initialization values to the standard > 'and / or / xor'-type logic that each represents, then it would be > quite possible to write a script to make an external RTL viewer based > on the technology netlist output by the Xilinx tools. > > Anyone game for a little sleuthing to determine all the LUT init > codes? > It's a bit harder than that. Assume a LUT has 4 inputs (it varies with different FPGA families). The synthesiser (eg XST) will look for a piece of combinatorial logic with 4 inputs & 1 output. It then simulates that logic, evaluating its output for all 16 possible input combinations. The initialisation string is simply the map of those 16 outputs, written out in hex. So there really isn't an underlying logic representation: the designer might have specified any Boolean function whatever (adder, parity tree, etc): the synthesiser doesn't care.Article: 135240
On Sep 22, 9:32=A0pm, Dave <dhsch...@gmail.com> wrote: > > Hello John.... > > for example... > > > ADDRESS =A0 =A0 =A0 =A000 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F > > INITIAL DATA =A0 =A012 FF FA DE 32 25 25 17 14 25 DA 11 BC 67 FE A2 > > > If I try to write in address 00 , 01, 02, etc > > > ADDRESS =A0 =A0 =A0 =A000 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F > > DATA WRITTEN 01 23 45 67 89 AB CD EF 11 22 33 44 55 66 77 88 > > > If I read the result after writting. > > > ADDRESS =A0 =A0 =A0 =A000 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F > > DATA WRITTEN 45 67 FA DE CD EF 25 27 33 44 DA 11 77 88 FE A2 > > > If you do this all along the memory the effect is the same. > > All the timing parameters are correct and I've checked with an > > oscilloscope the signals and seems to be correct also. > > > Any idea?. > > Thanks > > What are the burst length and burst interleaving parameters for the > SDRAM, and do you get the same behavior if you change them? > > Dave- Hide quoted text - > > - Show quoted text - Hi... I make a mistake with the description ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F INITIAL DATA 12 58 FF FF 32 25 FF FF 14 25 FF FF BC 67 FF FF If I try to write in address 00 , 01, 02, etc ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DATA WRITTEN 01 23 45 67 89 AB CD EF 11 22 33 44 55 66 77 88 If I read the result after writting. ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DATA WRITTEN 45 67 FF FF CD EF FF FF 33 44 FF FF 77 88 FF FF The burst length is 2 ThanksArticle: 135241
On Mon, 22 Sep 2008 21:44:19 -0700 (PDT), mkr <mahenreddy@gmail.com> wrote: >I am new to this area and trying to learn the baics. I understand what >duty cycle is but really want to know it's significance in digital >design. I have designed a clock divider as part of my first project >(UART). If the clock divider is set to divide by 10 I have an output >clock that is ON for one pulse and OFF for ten pulses so the output >duty cycle is 10%. I can modify the HDL to make it ON for five pulses >and again OFF for the next five pulses and achieve 50% duty cycle with >the same clock rate. In either cases I would like to know the impact >(not necesarily for UART but in general to the digital systems) and >what is the significance of duty cycle and what difference does it >make make to digital systems? In a strictly digital system where the duty cycle distorted clock is the output of a divider, there is probably no adverse consequence of such a clock. This assumes that the divider functions correctly with the main input high speed clock. This should work even if the output of the divider gets used as a negative edge clock later. In general the problem with duty cycle distortion in digital systems is that, actually there are no real edge-sensitive digital circuits. All digital gates are abstractions and a DFF is no exception as it uses high and low levels of the clock signals as opposed to edges of it. Internally a DFF expects each high and low levels of the clock pulse to have a minimum duration and even if you meet the minimum period of the clock pulse, if your duty cycle is distorted enough the DFF will not function correctly. In addition to setup and hold, the high/low pulse width of the clock are also times one needs to meet for timing closure.Article: 135242
Hi,
coming from ASIC I have probably a lot to learn about FPGA clocking.
While total control/responsibility for clock trees in an ASIC, it
seems that the synthesiser (in my case ISE 10.1) does a lot of magic
without me knowing about it. I have read some threads here that tells
me to use global clock and clock enable for modules running at lower
speeds than global clock.
My current scheme was:
divby2 : process(clk) is
sclk_int <= not sclk_int;
end process divby2;
usedivby2 : process(sclk_int) is
if rising_edge(sclk_int) then
-- do something with the divided clock
end if;
end process usedivby2;
After adding several of these entities in my design, ISE starts
complaining about problems with clock routing. When looking into the
synthesiser report, I see that all those sclk_int signals are assigned
to BUFGs and I am presuming that my derived clocks are using up all
the clocking ressources in the spartan3A DSP that I am using. In ASIC
this was never an issue as clocks are just signals (though I have to
care about my clock tree).
I guess the fact that sclk_int is in the sensivity list of the process
and that rising_edge(sclk_int) identifies sclk_int as a clock to the
synthesiser.
I have a hard time to find a section in the xilinx documentation
telling me what is actually happening in this case, but I presume I
will have to rewrite my code to use sclk_int as a clock enable signal.
I did actually to this in one module, but that generated flip-flops
clocked with global clock on the signals to store the value. I thought
that looked ugly and unnescessary, but maybe it isn't in FPGA design.
I presume it is not possible to tell the synthesiser that "sclk_int is
just another signal, but please use it as a clock for these LUTs" in
order to save me some recoding.
--
Svenn
Article: 135243On Sep 22, 8:17=A0pm, Rob <BertyBoos...@googlemail.com> wrote: > Hi all, > > I'm having problems with ISE seemingly ignoring timing constraints set > in the UCF file. One of the constraints ignored comes from Xilinx's > MIG tool and looks like this: > > INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM =3D > "TNM_PHY_INIT_DATA_SEL"; > TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" =3D FROM "TNM_PHY_INIT_DATA_SEL" TO > FFS > "TS_SYS_CLK" * 4; > > I'm not getting any errors, such as unable to locate nets, rather the > constraint seems ignored and looking in the timing report it is these > very paths that are failing (by a long way). I thought that if the > target nets don't exist then you get a translate error. > > I am using partitions in the design. I've tried to do a build after a > "clean up project files" and the constraint is still ignored. > > Any ideas? > > Rob Is this the only consrtaint in your design? If there are many, one of them migth be covering these paths. So its better to run the TSI report and check the path coverage.Article: 135244
Hi, I have implemented a system OFDM 2K with band of 8 MHz, style DVB-T. Using a system clock of 64 MHz everything works perfectly. Now I should be able to decrease the band OFDM to 7/6/5 MHz using the same 64 MHz clock. To get the bandwidth of 8 MHz in 2K (1705 active portant), simply clock output data from a IFFT at period of 7/64e6 = 109.375 nS. In that way or with that technique can reduce the clock out for obtain 7/6/5 MHz of band ? Without necessarily changing the clock 64 MHz ? Any idea ? Thanks. Kappa.Article: 135245
On Sep 23, 8:38=A0am, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> wrote: > Hi, > > coming from ASIC I have probably a lot to learn about FPGA clocking. > While total control/responsibility for clock trees in an ASIC, it > seems that the synthesiser (in my case ISE 10.1) does a lot of magic > without me knowing about it. I have read some threads here that tells > me to use global clock and clock enable for modules running at lower > speeds than global clock. > > My current scheme was: > divby2 : process(clk) is > =A0 sclk_int <=3D not sclk_int; > end process divby2; > > usedivby2 : process(sclk_int) is > =A0 if rising_edge(sclk_int) then > =A0 =A0 -- do something with the divided clock > =A0 end if; > end process usedivby2; > > After adding several of these entities in my design, ISE starts > complaining about problems with clock routing. When looking into the > synthesiser report, I see that all those sclk_int signals are assigned > to BUFGs and I am presuming that my derived clocks are using up all > the clocking ressources in the spartan3A DSP that I am using. In ASIC > this was never an issue as clocks are just signals (though I have to > care about my clock tree). > > I guess the fact that sclk_int is in the sensivity list of the process > and that rising_edge(sclk_int) identifies sclk_int as a clock to the > synthesiser. > > I have a hard time to find a section in the xilinx documentation > telling me what is actually happening in this case, but I presume I > will have to rewrite my code to use sclk_int as a clock enable signal. > I did actually to this in one module, but that generated flip-flops > clocked with global clock on the signals to store the value. I thought > that looked ugly and unnescessary, but maybe it isn't in FPGA design. > > I presume it is not possible to tell the synthesiser that "sclk_int is > just another signal, but please use it as a clock for these LUTs" in > order to save me some recoding. > > -- > Svenn Hi Svenn, In ISE, if you right click on the "synthesize -XST" process and then select the "Xilinx Specific Options" category there's a "Number of clock buffers" option. I think that if you reduce this to zero then XST will not automatically add any global buffers. This might fix your problem. I'm not sure exactly what you are trying to do, but it possible that your ASIC methodology doesn't fit FPGA methodology very well (i know nothing about ASIC design). If you want to generate an in phase div 2 clock then this can be easily achieved with the DCM modules. Alternately you could clock all logic with the same clock and use the clock enable signal to load the register every other clock cycle. If necessary you can also define multi-cycle paths to ease the timing requirements. You can clock registers with general routing in FPGAs, but I would say that you should definitely avoid this unless it is absolutely necessary. Cheers, RobArticle: 135246
On Mon, 22 Sep 2008 11:51:29 -0700 (PDT), osquillar <ogm101274@hotmail.com> wrote: >> > > > Hello all, I'm working with an microblaze system and I'm trying to >> > > > work with a Micron MT48LC16M16 memory and something strange happens, >> > > > It seem than I can read positions all position but if I try to write >> > > > in positions 00 and 01 nothing changes and if I write something in >> > > > positions 02 and 03 they seems to be written in position 00 and 01. It >> > > > happens the same with the rest of the memory. >ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F >DATA WRITTEN 01 23 45 67 89 AB CD EF 11 22 33 44 55 66 77 88 > >If I read the result after writting. > >ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F >DATA WRITTEN 45 67 FA DE CD EF 25 27 33 44 DA 11 77 88 FE A2 What result did you get in simulation? - BrianArticle: 135247
On 20 Sep 2008 09:48:58 -0700, thutt <thutt151@comcast.net> wrote: > >Hello everyone, > >I'm tired of using the Xilinx ISE to look at RTL schematics, mainly >because it's so slow and cumbersome to use. What I'd like to do is >output a netlist and use another script to process that netlist into >input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html). > >I have figured out how to get the Xilinx tools to output a netlist, >but it appears they output a 'technology' version and not an 'RTL' >version of the netlist. >Is there any way to get the tools to output a netlist that is in the >more useful (to me) 'RTL' format? Have you looked at the post-synthesis simulation model (in VHDL)? - BrianArticle: 135248
Brian Drummond <brian_drummond@btconnect.com> writes: > On 20 Sep 2008 09:48:58 -0700, thutt <thutt151@comcast.net> wrote: > > > > >Hello everyone, > > > >I'm tired of using the Xilinx ISE to look at RTL schematics, mainly > >because it's so slow and cumbersome to use. What I'd like to do is > >output a netlist and use another script to process that netlist into > >input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html). > > > >I have figured out how to get the Xilinx tools to output a netlist, > >but it appears they output a 'technology' version and not an 'RTL' > >version of the netlist. > > >Is there any way to get the tools to output a netlist that is in the > >more useful (to me) 'RTL' format? > > Have you looked at the post-synthesis simulation model (in VHDL)? > > - Brian No. Why? I don't understand; I'm not looking to simulate, I'm looking to view a schematic outside of ISE. -- Hot glass looks just like cold glass.Article: 135249
On Tue, 23 Sep 2008 01:38:24 -0700 (PDT), Svenn Are Bjerkem
<svenn.bjerkem@googlemail.com> wrote:
>Hi,
>
>coming from ASIC I have probably a lot to learn about FPGA clocking.
>While total control/responsibility for clock trees in an ASIC, it
>seems that the synthesiser (in my case ISE 10.1) does a lot of magic
>without me knowing about it. I have read some threads here that tells
>me to use global clock and clock enable for modules running at lower
>speeds than global clock.
>
>My current scheme was:
>divby2 : process(clk) is
> sclk_int <= not sclk_int;
>end process divby2;
>
>usedivby2 : process(sclk_int) is
> if rising_edge(sclk_int) then
> -- do something with the divided clock
> end if;
>end process usedivby2;
>After adding several of these entities in my design, ISE starts
>complaining about problems with clock routing.
You are thinking along the right lines. This form of "usedivby2" does
generate another clock. Which is not entirely wrong, but definitely
discouraged, in an FPGA.
A GOOD use for it could be to clock the majority of your logic off a
lower frequency clock, and (a) save power, and (b) relax the timing
constraints WITHIN that lower frequency clock domain.
The drawbacks are twofold;
(1) since the divided clock is delayed wrt the original, you have to pay
special attention to signals originating in one clock domain and
terminating in the other. This is probably a bigger problem in FPGA than
in ASIC because routing delays tend to dominate (aside from the simple
headache of creating and verifying cross-domain timing constraints).
(2) as you found, each clock consumes a limited resource - a clock tree
spanning typically either the whole FPGA or a single quadrant. You may
have only 4 or 8 to play with.
For most purposes use the clock enable form:
usedivby2_better : process(clk) is
if rising_edge(clk) then
if sclk_int = '1' then
-- do something with the divided clock as an enable
end if;
end if;
end process usedivby2_better;
Use it everywhere to keep the entire design synchronous to clk;
timing constraints are very simple and reliable.
Use divided clocks sparingly, if you have a compelling need for them.
And if you must use them; consider instantiating a DCM or PLL to
generate them; these modules can adjust their internal delays to cancel
out the clock skew that would result from a simple division.
Two warnings;
(a) you have about the same number of these as clock trees; typically 4
or 8, and
(b) Don't cascade DCMs if you can avoid it; beyond 2 DCMs the clock
jitter will prevent the downstream ones locking.
It seems likely to me that ASIC tools have a much more sophisticated
approach to static timing verification where multiple clocks and clock
domain crossings are involved. (I'd hope so, given their price!)
In FPGA the tools are almost free; you can't expect the same level of
sophistication at the price. Nor do you need it if you design within the
FPGA paradigm: ideally a single clock, with enables where you need them.
Failing that, few large clock domains, and get paranoid about the
crossing points.
In many cases, the high static power consumption of an FPGA will make it
pointless to try saving power from divided clocks.
- Brian
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