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On Wed, 24 Sep 2008 08:10:30 -0700 (PDT), Benjamin Couillard <benjamin.couillard@gmail.com> wrote: >Hi, I'm currently developping a FPGA application where I implemented a >SDRAM controller with a DCM to remove external skew. > >So basically, I checked the XAPP462 application note, and I designed >the deskew circuit with 1X feedback instead of 2X feedback. When I >program the FPGA using the JTAG cable, the DCM locks and everything >works fine (i.e. I can read and write the SDRAM correctly). However, >when I program the FPGA with the onboard MPU, the DCM doesn't lock at >all. It seems to me that it's probably some kind of timing issue with >the DCM. What is the clock source for the deskew DCM? If it has already been through more than one DCM, the accumulation of jitter may prevent the last one locking. One DCM ahead of the de-skew DCM should be OK, provided the original clock is a high quality source. - BrianArticle: 135301
the clock source is the output of another DCM, so there's one problem, my reset circuit didn't take that in account. I changed the reset connection so that the reset input of the deskew DCM (the 2nd one in the chain) is "FIRST_DCM_LOCKED" not. However, even with that change, I still get the same behavior. The 2nd DCM locks when I program the FPGA with the platform cable and it doesn't when I program it with the MPU. But I still gotta check some other things like the MPU code. ThanksArticle: 135302
Hi Jerzy Gbur. Thanks for your replay. > You can design new OFDM symbol, without part of carriers. I did not > understand it anyway as achieve it. you might be more accurate ? I sincerely not thought I had at this solution. I have an IFFT of 2048 point. Mapping pilot at input of IFFT for +/-DC offset, [0 - 852 Data pilot] [853 - 1194 Null pilot] [1195 - 2047 Data pilot]. Process IFFT and i obtain a time domain data, with sample time of 7/64e6 I obtain 8 MHz band. Keeping the same IFFT point to 2048 as carriers can remove ? Regards, Kappasm.Article: 135303
I ma trying to make my first design (UART) wishbone compliant and looked at wishbone specification and several examples with source code on the net. Though I understand there are some restrictions on multiplexing of address and data bus, tri-state bus etc.. in many cases I hardly see any additional logic in the wishhbone compliant designs other than naming the external signals as per the wishbone standard and some additional documentation like wishbone datasheet etc.. Is that all about Wishbone compliance? TIA mkrArticle: 135304
On 2008-09-25, Steve Knapp <steveD.O.TknappA.Tprevailing-technologyD.O.Tcom> wrote: > Peter, thank you again for being "progressive" and championing the "old" > customer-centric Xilinx ways. > > Informed customer + responsive, communicative vendor = Long-time > customer and successful vendor. Agreed. Another point that is not immediately obvious is the fact that a posting from comp.arch.fpga is often the first hit you get when you search for some kind of FPGA related issue. So many people beside Usenet readers will benefit from vendor participation on comp.arch.fpga. While I understand that Peter have other things to do with his time, I hope that at least some people from Xilinx will continue their presence here. The response from Xilinx here is probably the biggest issue why I landed in Xilinx-land and haven't yet bothered to look deeply at Altera, Actel or Lattice. Although I must admit that I'm probably not the biggest customer that Xilinx have :) /AndreasArticle: 135305
mkr wrote: > I ma trying to make my first design (UART) wishbone compliant and > looked at wishbone specification and several examples with source code > on the net. Though I understand there are some restrictions on > multiplexing of address and data bus, tri-state bus etc.. in many > cases I hardly see any additional logic in the wishhbone compliant > designs other than naming the external signals as per the wishbone > standard and some additional documentation like wishbone datasheet > etc.. Is that all about Wishbone compliance? > Hi, I suggest you take a closer look at the "Simple 8-bit SLAVE Output Port" example in the Tutorial appendix of the WISHBONE specification. For simple slave modules, that's pretty much all there is to it. HTH RGArticle: 135306
On Sep 24, 10:22=A0am, emeb <ebromba...@gmail.com> wrote: > On Sep 24, 5:45=A0am, Andy <jonesa...@comcast.net> wrote: > > > On Sep 23, 5:54=A0pm, "Steve Knapp" <steveD.O.TknappA.Tprevailing- > > > technologyD.O.Tcom> wrote: > > > IIRC, JTAG is always functional, even if using Master Serial configur= ation > > > mode. =A0 > > > Normal JTAG functions are always available. JTAG configuration > > functions (on some devices, including at least V2) are not available > > unless the mode pins are set to JTAG, or a valid configuration has > > already been completed. Don't ask me how I know... ;^) > > Yeow! Does anyone know if this is true for V5? I've got a board going > to layout with the mode pins grounded for master serial, but I want to > be able to do JTAG as well just in case. This is on a BGA part, so if > I need to tweak these pins, I'll have to route them out or be screwed. > > Eric JTAG certainly works for ChipScope with mode pins grounded. I am doing that right now.Article: 135307
On Sep 25, 8:05=A0am, Barry <barry...@gmail.com> wrote: > On Sep 24, 10:22=A0am, emeb <ebromba...@gmail.com> wrote: > > > > > On Sep 24, 5:45=A0am, Andy <jonesa...@comcast.net> wrote: > > > > On Sep 23, 5:54=A0pm, "Steve Knapp" <steveD.O.TknappA.Tprevailing- > > > > technologyD.O.Tcom> wrote: > > > > IIRC, JTAG is always functional, even if using Master Serial config= uration > > > > mode. =A0 > > > > Normal JTAG functions are always available. JTAG configuration > > > functions (on some devices, including at least V2) are not available > > > unless the mode pins are set to JTAG, or a valid configuration has > > > already been completed. Don't ask me how I know... ;^) > > > Yeow! Does anyone know if this is true for V5? I've got a board going > > to layout with the mode pins grounded for master serial, but I want to > > be able to do JTAG as well just in case. This is on a BGA part, so if > > I need to tweak these pins, I'll have to route them out or be screwed. > > > Eric > > JTAG certainly works for ChipScope with mode pins grounded. =A0I am > doing that right now. Ben, Barry, Yes - I have several systems with mode pins grounded that work both in Master Serial and JTAG modes. I believe that Andy's point was that if for some reason the Master Serial configuration fails, then JTAG doesn't work as a backup on systems up to & including V2. My question is this: for V5 systems, if Master Serial fails, will JTAG work as a backup? Have either of you tried JTAG when there isn't a valid configuration loaded into the config ROM? EricArticle: 135308
No PayPal ordering method? What a shame. Some interesting stuff - thanks for making it available.Article: 135309
Benjamin Couillard wrote: > the clock source is the output of another DCM, so there's one problem, > my reset circuit didn't take that in account. I changed the reset > connection so that the reset input of the deskew DCM (the 2nd one in > the chain) is "FIRST_DCM_LOCKED" not. However, even with that change, > I still get the same behavior. The 2nd DCM locks when I program the > FPGA with the platform cable and it doesn't when I program it with the > MPU. > > But I still gotta check some other things like the MPU code. Are you using any BUFGMUX cells? Which family is the design in? Ed McGettigan -- Xilinx Inc.Article: 135310
"przemek klosowski" <przemek.klosowski@gmail.nospam> wrote in message
news:gYiCk.957$Jw.827@nwrddc02.gnilink.net...
<snip>
> Xilinx should understand that accumulated influence of people like you
> and Austin may be more important than a legion of marketeers. They should
> make you an editor, and give you a bunch of them to ghost-write the docs
> as you see fit.
Agreed. This isn't just a Xilinx issue. I've been amazed by the number of
companies with similar thinking, with a thought process that goes something
like this.
* <insert name> is too valuable (or expensive) to waste <his/her> time
communicating with customers. <He/She> has more important things to do.
* <insert name> doesn't always use the "politically correct" marketing terms
or is sometimes too open and honest about product issues.
* We already know what is best for our customers. Participating in an open
forum doesn't provide much return on investment. A glossy four-page
brochure is far more important.
Peter, thank you again for being "progressive" and championing the "old"
customer-centric Xilinx ways.
Informed customer + responsive, communicative vendor = Long-time
customer and successful vendor.
===============================================
Steven K. Knapp
Prevailing Technology, Inc.
Web: www.prevailing-technology.com
Article: 135311On 25 sep, 12:32, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > Benjamin Couillard wrote: > > the clock source is the output of another DCM, so there's one problem, > > my reset circuit didn't take that in account. I changed the reset > > connection so that the reset input of the deskew DCM (the 2nd one in > > the chain) is "FIRST_DCM_LOCKED" not. However, even with that change, > > I still get the same behavior. The 2nd DCM locks when I program the > > FPGA with the platform cable and it doesn't when I program it with the > > MPU. > > > But I still gotta check some other things like the MPU code. > > Are you using any BUFGMUX cells? =A0Which family is the design in? > > Ed McGettigan > -- > Xilinx Inc. I solved the problem, the first DCM in the chain wasn't properly configured. The expected input frequency was set to 29 MHz instead of 49 MHz. Now everything works fine.Article: 135312
jack.harvard@googlemail.com wrote: > what's the best way to transform decimal numbers to 32bits wide ieee > 754 single precision floating point numbers? possibly using perl or > verilog. i did some searching, there are converters like this > http://babbage.cs.qc.edu/IEEE-754/Decimal.html, but not for large > amount of data. thanks, -j I've never had cause to use it, but there are Verilog functions $bitstoreal and $realtobits which convert reals to the IEEE-754 format and vice versa. (Note: these use the 64-bit double format, not single-precision.) One main use of these is to allow a user to pass reals as vectors through 64-bit ports (since a port can't have a real format). If you have Matlab, you can also use "format hex". -KevinArticle: 135313
Hello everyone. The first thing I need to do is programming the data transfer between CPU and PCI based FPGA. OS is Linux. For now, I don't know how to approach this. Is there anyone who recommend the useful textbook and technical report for this kind of project? Useful links also would be very appreciated.Article: 135314
Thanks for the hint. I tried with a different design/programming, this time declaring a FSM, and now it is working properly, without the LEDs blinking. I never knew what was not working properly of last design. Oh and I found the LCD's datasheet (Sitronix ST7066U) http://www.sitronix.com.tw/sitronix/product.nsf/Doc/ST7066U?OpenDocument I honestly have not checked it completely. I am now working with other phase. Thank you, m m _s __________________________ On Sep 19, 5:51=A0pm, "Steve Knapp" <steveD.O.TknappA.Tprevailing- technologyD.O.Tcom> wrote: > I looked at the Spartan-3A Starter Kit board schematic, but it does not > appear that the character LCD pins are shared with the LEDs.http://www.xi= linx.com/support/documentation/boards_and_kits/ug334.pdf > > Do you have other outputs in the design? =A0Are those output pins defined= a > LOCation in the UCF file? =A0It could be that output pins with an unassig= ned > pin location are landing on the LED pins. > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > Steven K. Knapp > Prevailing Technology, Inc. > Web: =A0www.prevailing-technology.comArticle: 135315
On 2008-09-26, Mark McDougall <markm@vl.com.au> wrote: > You probably should read O'Reilly's "Linux Device Drivers". IIRC there is > some way to map PCI memory into user space without writing a driver, but > it's been a long time... I wrote a post about this on comp.arch.fpga some time ago: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/5171491963302b63/daf1deb1296c46eb?lnk=st&q=group%3Acomp.arch.fpga+linux+ehliar#daf1deb1296c46eb Essentially what you do is that you open /dev/mem and mmap it at the appropriate location. /AndreasArticle: 135316
KJ wrote: > The first thing I need to do is programming the data transfer between > CPU and PCI based FPGA. > OS is Linux. For now, I don't know how to approach this. PCI-based FPGA? Do you need to implemented PCI in the FPGA, or is there already a PCI slave on the FPGA board? > Is there anyone who recommend the useful textbook and technical report > for this kind of project? > Useful links also would be very appreciated. Depends on your answer to the above question. You probably should read O'Reilly's "Linux Device Drivers". IIRC there is some way to map PCI memory into user space without writing a driver, but it's been a long time... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 135317
Hi, I am using EDK10.1, and I have Atmel 32MB flash on my board, (AT49BV322D). But whenever I try to program the flash through the Device configuration, Program Flash tab it says, Unable to query part layout using CFI. I have checked all the connections and even probed the signals, they all seem to be fine. Is there anything special that I have to do? -- GoliArticle: 135318
Andreas Ehliar wrote: (I wrote) >>The Intel 8086 and 8088 use a 33% duty cycle clock for maximum >>clock speed. Something strange in that design. > My guess would be that this is caused by a latch based design. That would do it, but it might also be related to dynamic logic. Unlike many others, Intel processors such as the 8080 and 8086 used dynamic logic, somewhat like DRAM. (It might just be that registers are DRAM, or it might be much more.) The 8080 has a two phase clock with different times for each phase. (That is, two clock input pins.) The 8086 has a minimum clock frequency of 2MHz due to the use of dynamic logic. -- glenArticle: 135319
RG, thanks. I looked at the 8-bit slave o/p port and 16X8 bit slave memory given in the appendix of the spec. The 16X8 bit slave memory has only one AND gate besides the required two 16X4 bit SRAM modules. Even if you don't need it to make wb compliant you pretty much need to have everything (data in , data out , address in, Clock in , ack , write enable and associated logic) and design it the same way whther you want it wb compatible or not. The only obvious difference is naming of interface signals as per wb spec. I know I am missing something but not able to figure out. I designed a simple UART as my first project and trying it to make it wb compliant. I read the wb spec but I don't see the need for any changes, to make it wb compliant other than changing the interface signal names. On the system side UART has clk,_in rst_in, Data in/out, reg address in and write enable signals and the logic is obvious from signal names. As far as the interface is concerned I don't find any difference between my current non wb UART and the example 16x8 memory in the spec except the signal names. I am stuck here and not able to move forward to the next design. - mkr On Sep 25, 7:10=A0pm, argee <n...@nope.com> wrote: > mkr wrote: > > I ma trying to make my first design (UART) wishbone compliant and > > looked at wishbone specification and several examples with source code > > on the net. Though I understand there are some restrictions on > > multiplexing of address and data bus, tri-state bus etc.. in many > > cases I hardly see any additional logic in the wishhbone compliant > > designs other than naming the external signals as per the wishbone > > standard and some additional documentation like wishbone datasheet > > etc.. Is that all about Wishbone compliance? > > Hi, > > I suggest you take a closer look at the "Simple 8-bit SLAVE Output Port" > example in the Tutorial appendix of the WISHBONE specification. For > simple slave modules, that's pretty much all there is to it. > > HTH > > RGArticle: 135320
mkr <mahenreddy@gmail.com> writes: > RG, thanks. > > I looked at the 8-bit slave o/p port and 16X8 bit slave memory given > in the appendix of the spec. The 16X8 bit slave memory has only one > AND gate besides the required two 16X4 bit SRAM modules. Even if you > don't need it to make wb compliant you pretty much need to have > everything (data in , data out , address in, Clock in , ack , write > enable and associated logic) and design it the same way whther you > want it wb compatible or not. The only obvious difference is naming of > interface signals as per wb spec. I know I am missing something but > not able to figure out. > I'm not sure you are missing anything. For simple slaves, it really is that simple. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 135321
I have recently developed a MicroBlaze SMP system for FPGAs and want to share it with the community. The system can be used as an example of how to build SMP systems on FPGA and how to write applications for it. In the software side, a modified version of xilkernel I have developed is used to write multi-threaded applications that run on the SMP system. If you want to take a look at the system or to the modified xilkernel version, you can download it from http://www.escet.urjc.es/~phuerta/SMP_project.htm The system has 2 Microblazes and is for use on the XUP V2P board, but there will be demos for other boards and with more processors soon. Any comments, suggestions and questions are welcomed ! Regards, Pablo HArticle: 135322
On 25 Wrz, 09:06, "Kappasm" <_NOSPAM_78kappa78_NO_S...@virgilio.it> wrote: > Hi Jerzy Gbur. > > Thanks for your replay. > > > You can design new OFDM symbol, without part of carriers. I did not > > understand it anyway as achieve it. you might be more accurate ? > > I sincerely not thought I had at this solution. > > I have an IFFT of 2048 point. Mapping pilot at input of IFFT for +/-DC > offset, [0 - 852 Data pilot] [853 - 1194 Null pilot] [1195 - 2047 Data > pilot]. Process IFFT and i obtain a time domain data, with sample time of > 7/64e6 I obtain 8 MHz band. > > Keeping the same IFFT point to 2048 as carriers can remove ? I'm not sure I understood. But what I propose is, for narrow band set, for example [0 - 511 Data] [512 - 1535 Nul] [1536 - 2047 Data], It depend what band you exactly want. Lenght of IFFT transform should stay the same. IMHO it's most simple way to filfull your requirements. Best Regards, Jerzy GburArticle: 135323
Andy wrote: > On Sep 23, 11:42 am, Gael Paul <gael.p...@gmail.com> wrote: >> 5. Once you have converted your generated clock, you will probably >> need to add multi-cycle paths constraints to avoid false critical >> paths. > > Avoid using multi-cycle path constraints unless you absolutely have to > use them, or are getting unacceptably long run-times trying to meet > single cycle timing on those paths. The reason is that multi-cycle and > false path constraints can be tricky to specify correctly, and make > sure that only those paths that are truly multi-cycle or false are > constrained (actually relaxed) as such. > > Andy Hi Andy, I've noticed that a lot of people on this newsgroup have a morbid fear of mutli-cycle clock constraints. Personally, I use them all the time and have few problems; certainly fewer problems than I would have if I tried to do the same thing with multiple clocks. In a situation where a block of logic can run at (say) half the clock rate, I give it an enable and set the constraints accordingly using the NET "clock_enable_signal*" TNM=TS1; thing in the Xilinx tools. (BTW, The asterisk is useful if the enable gets replicated by the synthesis tools) This lets the P&R tools concentrate effort where it's needed. Of course, avoiding multi-cycle constraints by using a divided clock would be bad. Can you give an example where you've run into problems? Thanks, Symon.Article: 135324
On Sep 25, 5:32=A0pm, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:
> jack.harv...@googlemail.com wrote:
> > what's the best way to transform decimal numbers to 32bits wide ieee
> > 754 single precision floating point numbers? possibly using perl or
> > verilog. i did some searching, there are converters like this
> >http://babbage.cs.qc.edu/IEEE-754/Decimal.html, but not for large
> > amount of data. thanks, -j
>
> I've never had cause to use it, but there are Verilog functions
> $bitstoreal and $realtobits which convert reals to the IEEE-754 format
> and vice versa. =A0(Note: these use the 64-bit double format, not
> single-precision.) =A0One main use of these is to allow a user to pass
> reals as vectors through 64-bit ports (since a port can't have a real
> format). =A0If you have Matlab, you can also use "format hex".
> -Kevin
If you have a C compiler you can write a simple program that
includes your data file as a comma-delimited list like:
float foo[] =3D {
#include numberlist.csv
};
and then write some simple code to coerce the values to unsigned int
and print them out.
Just a thought....
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