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> Nico Coesel wrote: > >> BERTEn <= BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel; > > > This construction wouldn't be very clear for people that are > > relatively new to a programming language. I'd try to avoid it. > > > How about: > > > process ( BERTSel, SyncPOSSel, GenEn, GenPOSSel) begin > > if (BETRSel and Genen)='0' then > > BERTEn <= not SyncPOSSel > > else > > BERTEn <= not GenPOSSel; > > end if; > > end process; One other point. I don't write code for beginners to understand. I write for a typical programmer or sometimes just for myself. I do want the code to be readable, but I don't feel a need to "dumb" it down for others. RickArticle: 134201
Symon wrote:
> Guys,
> Using ISE10.1 my design's timing fails, whereas it used to be fine. Here's
> the problem:-
>
> In ISE8.2 the P&R tools had the sense to use the topcyf path to get onto the
> carry chain which takes 1.162ns
>
> file:///C:/Xilinx/10.1/ISE/doc/usenglish/help/delay_types/html/web_ds_sp3/ta_topcyf.htm
>
> In ISE10.1 the P&R tools seem intent on using the tbxcy path to get onto the
> carry chain which, although it saves a LUT, takes 1.882ns adding 720ps
> delay.
>
> file:///C:/Xilinx/10.1/ISE/doc/usenglish/help/delay_types/html/web_ds_sp3/ta_tbxcy.htm
>
> I tried messing about with the ISE10.1 Map and P&R properties, with no luck.
> In MAP, I changed 'Optimization strategy' to speed. I set the tick box for
> 'Perform timing-driven packing and placement'.
>
> Any clues?
>
> Thanks, Symon.
If you can't change the source or the constraints file, you probably
don't have recourse. If you can't change the source, you might still
have the chance for a "keep" constraint in the right place specified
in the ucf. If you can change the source, you have a decent chance.
I tend to change the source in the logic at the bottom of the carry
chain. A "keep" in the right place or exchanging the LSbits between
two vectors that are added ({a[9:1],b[0]}+{b[9:1],a[0]}) or even
sometimes b+a instead of a+b coding is enough to make a synthesizer
"think" differently. Even adding an unused LSbit in a manner that
doesn't get optimized away can push the synthesis to produce a
"better" result though at the cost of one Tbyp.
It's probably the synthesizer and not the map/p&r tools giving you the
troubles; if you have an edif flow or a technology view that is true
to the synthesis output, see if there are hints on whether you succeed
before p&r.
- John_H
Article: 134202
"John_H" <newsgroup@johnhandwork.com> wrote in message
news:ea726f91-b088-47bf-8b29-d2f4cda81d3a@m44g2000hsc.googlegroups.com...
>
> I tend to change the source in the logic at the bottom of the carry
> chain. A "keep" in the right place or exchanging the LSbits between
> two vectors that are added ({a[9:1],b[0]}+{b[9:1],a[0]}) or even
> sometimes b+a instead of a+b coding is enough to make a synthesizer
> "think" differently. Even adding an unused LSbit in a manner that
> doesn't get optimized away can push the synthesis to produce a
> "better" result though at the cost of one Tbyp.
>
> It's probably the synthesizer and not the map/p&r tools giving you the
> troubles; if you have an edif flow or a technology view that is true
> to the synthesis output, see if there are hints on whether you succeed
> before p&r.
>
> - John_H
Hi John,
Thanks for your reply! You're correct it's the Synplify synthesis tool that
yields the 'bad' mode with tbxcy. Remarkably, it would appear that ISE8.2
was clever enough to change the EDIF circuit to give better timing results,
but ISE10.1 doesn't bother. So, I'll fix the source code. Thanks for your
suggestions, I'll try them out. Maybe there are some synthesis options to
try also.
I wonder, did you ever try instantiating the first MUXCY of the chain to
force the correct behaviour? Gives, horrible looking source code though, I
suppose!
Cheers, Syms.
Article: 134203Symon wrote: > Hi John, > Thanks for your reply! You're correct it's the Synplify synthesis tool that > yields the 'bad' mode with tbxcy. Remarkably, it would appear that ISE8.2 > was clever enough to change the EDIF circuit to give better timing results, > but ISE10.1 doesn't bother. So, I'll fix the source code. Thanks for your > suggestions, I'll try them out. Maybe there are some synthesis options to > try also. > I wonder, did you ever try instantiating the first MUXCY of the chain to > force the correct behaviour? Gives, horrible looking source code though, I > suppose! > Cheers, Syms. I've used the instantiated MUXCY trick before; I hate to do it. You're right that it's not too pretty. I can usually push the rope pretty well with Synplify (Verilog) so I have strong hopes for your success. - John_HArticle: 134204
On Wed, 30 Jul 2008 08:23:03 -0700, Mike Treseler wrote: > Attitude is what keeps things interesting. > Everybody's got one. Well I guess that's borne out by the Big Brother TV show here in the UK. It basically consists of, well attitude - take that out of the show and there's nothing left :-) and a lot do find it interesting. Regards, Paul.Article: 134205
Scott Gravenhorst wrote: I've read comments here and elsewhere that the Digilent > Parallel III cable is a clone of the Xilinx cable. Does anyone know > if Will this cable (Digilent Parallel III) works with this board and > iMPACT or any other Windows based FPGA programmer software? Or is > there a better solution? Xilinx's parallel cable III is a 74HC125, a diode and a couple resistors. You could build one of these in half an hour. The schematic is published somewhere on the Xilinx web site. JonArticle: 134206
On Wed, 30 Jul 2008 08:23:11 -0700, rickman wrote: > I don't really want to write in C. I would just like to see VHDL de- > verbosed in some cases. You get used to it - I can now type downto faster than my name ;-) Paul.Article: 134207
> Does anyone know of a way to modify which VHDL libraries ISE > automatically uses in VHDL files created by the new file wizard? It I asked the same question about the horrendous header that's automatically added in verilog. Nope. No way to change that, when using verilog. At least some time ago. That's seems pretty silly to me. Do no put anything, or, if you want to do it, just think 2 seconds and do it sensibly... just append a verbatim copy an ascii file on disk. Bah.Article: 134208
Il 30/07/2008 17.23, rickman ha scritto: > points. If the logic is involved and requires state analysis, then I > would use a flow chart or design the state machine. But how would a > flow chart be used to design the data path? Well said! (even for FSMs, I found good and clean code even easier to read than an huge bubble diagram...) Especially for long chains of pipelined stages... keeping track of how many delays I need to put for that long forgotten control signal.. I tried in excel (even "simulating" the design) with mixed results, but I have a feeling that someone more skilled than me must have solved this with a better notation years ago... Just didn't find any "practical" and easy notation...Article: 134209
"Matthias Alles" <REMOVEallesCAPITALS@NOeit.SPAMuni-kl.de> wrote in message news:g6choh$qot$1@news.uni-kl.de... > Hi again! > >> stfd f30, 1760(r1) with r1 = 0x0111ed1a >> >> The resulting address is not aligned to an 8-byte boundary which causes >> the exception. It seems that the stack for the thread is not aligned to >> an 8-byte boundary. Looks like a xilkernel bug. > > OK, I was able to fix this issue by myself in the xilkernel. My guess > was right. > The stack for all threads is created in mem.c line 63 like this: > > char thread_stack_mem[PTHREAD_STACK_MSIZE]; > > By replacing the line with > > char thread_stack_mem[PTHREAD_STACK_MSIZE] __attribute__ ((aligned (8))); > > the problems are gone. So the programmers of the xilkernel just never > thought of 64bit types that some applications might use. > > The issue is a bit more basic -- Xilkernel does not support the APU FPU; It does not save/restore the floating point registers on context switches, does not distinguish between single precision/double precision and so on. Unless you plan to use floating point in just a single thread, you will end up with a corrupted system. Documentation is missing for this lack of support. We will get it added in. VasanthArticle: 134210
On Wed, 30 Jul 2008 21:06:42 +0200, Antonio Pasini wrote: > (even for FSMs, I found good and clean code even easier to read than an > huge bubble diagram...) I guess someone must find state-machine diagram software useful, that will auto-generate code from a diagram for you. > Especially for long chains of pipelined stages... keeping track of how > many delays I need to put for that long forgotten control signal.. That's why FPGA design is really harder than writing C programs, because all your signals have to come out at the right time in relation to each other. Even if your had a perfect HDL, FPGA design would still be difficult compared to software. VHDL's verbose, but on a file by file basis, the verbosity I don't think obscures the intention of the code - the verbosity is just tedious. The other thing that makes FPGA design hard is that the tools implement different parts of the VHDL standard. Like recently when I had to take variables out of a process, and convert them to signals, because XST didn't like them, but the simulator did - pain in the arse. Paul.Article: 134211
On Jul 30, 10:25 am, rickman <gnu...@gmail.com> wrote: > > One other point. I don't write code for beginners to understand. I > write for a typical programmer or sometimes just for myself. I do > want the code to be readable, but I don't feel a need to "dumb" it > down for others. > > Rick I think that's one of the points some of us are trying to get at. The verilog syntax you seek is not well understood by a vhdl audience.. Write your code where only you can read it, and you will have to maintain it, because no one else can (that may be a goal, but not for me). Many of us work in environments which require peer reviews, where making the code more easily readable by others (programmers, but maybe not experts) pays dividends. I prefer to write code that expresses the behavior more clearly, if not necessarily the implemented structure. Different synthesis tools, target architectures or optimization goals may result in different implementations, which is fine as long as they meet timing/resource requirements and match the RTL behavior. When they do not meet timing or resource requirements, then (and only then) I revert to trying to coax the implementation I have in mind out of the synthesis tool, by modifying the code structure to get the implementation I want. AndyArticle: 134212
Hi, Does anybody have any experience in using the mex file provided by xilinx core-generator for xfft_v5 to model the characteristics of the bit-accurate FFT FPGA core in matlab? I put the mex file in the same directory as where i am running matlab. and follow the instructions closely on how to call the mex function this is the error i get. ?? invalid mex file C:\xfft_v5_0_bitacc_cmodel_mex.mexw32. the specified module could not be found Error in use_mex 11 [output, blkexpm, overflow] = xfft_v5_0_bitacc_mex(generics, 10, input, scaling_sch,1 ); I have merely copied the matlab contents from page 19 of the pdf user guide. It can be downloaded from here. http://www.xilinx.com/products/ipcenter/FFT.htm I am using the same matlab 7.3 version as described and have put the mex file in the directory which i am running the command. ChrisArticle: 134213
Am using the free ISE Webpack, and wanted to know if it's possible just to use the command line and code/config files...that counts for things like package assignments and simulator stuff...can it be done at all, or easily? Thanks for your insights...Article: 134214
Thanks for the information. That's good to know! I didn't think about that at all.. Are there any plans to include FPU support into xilkernel for a future release? Matthias > The issue is a bit more basic -- Xilkernel does not support the APU FPU; It > does not save/restore the floating point registers on context switches, does > not distinguish between single precision/double precision and so on. > > Unless you plan to use floating point in just a single thread, you will end > up with a corrupted system. > > Documentation is missing for this lack of support. We will get it added in. > > VasanthArticle: 134215
On Jul 31, 8:31 am, andersod2 <thechrisander...@gmail.com> wrote: > Am using the free ISE Webpack, and wanted to know if it's possible > just to use the command line and code/config files...that counts for > things like package assignments and simulator stuff...can it be done > at all, or easily? > > Thanks for your insights... Hi, There is a nice command line flow, to get the bit file from your source files and config files. You could also get the command log file of your project, from the ISE interface itself. In design utilities, you have the option of view Command line log file. Also you could set up a simple Make environment for the same. I have build a simple Make environment and for me that works the best. It is much simpler and easy to use. But I have not used command line much for simulation or for assigning pins, floor planner and so on. I guess for that you need GUI. Hope this helps. -- GoliArticle: 134216
This is what I have in mind:
1. Counter counts to zero, issues an IRQ, and reloads.
2. The CPU gets the IRQ and writes the new 'reload' value,
which should remove the IRQ.
signal counter, reload : STD_LOGIC_VECTOR (15 downto 0);
if falling_edge(clock) then
if counter = 0 then
counter <= reload;
irq <= '1';
else
counter <= counter - 1;
-- irq <= '0'; -- AUTO
EOI
end if;
end if;
if rising_edge(write) then
reload <= dbus; -- reload
value
irq <= '0'; --
acknowledge IRQ, EOI
end if;
If I use one process, webpack is giving me an error:
Multi-source in Unit <test> on signal <irq>; this signal is connected
to multiple drivers
If I use two processes: Signal irq cannot be synthesized.
Something like, irq is bound to two clocks.
AUTO EOI works (in simulation, dont even have the chip yet),
but the clock can be as low as 30Hz, which is too slow.
How should I ACK an IRQ with the CPU?
Article: 134217if write = '1' then irq <=0; reload <= dbus; elsif falling_edge(clock) then if counter = 0 then counter <= reload; irq <= '1'; else counter <= counter - 1; irq <= '0'; -- AUTO EOI end if; end if; I know I shouldn't do homework for people but what the hey. Use the write signal as an asynchronous reset. Also, use numeric.std . It's lovely. http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf HTH, Syms.Article: 134218
On Wed, 30 Jul 2008 06:41:15 -0700 (PDT), Dave <dhschetz@gmail.com> wrote: >Does anyone know of a way to modify which VHDL libraries ISE >automatically uses in VHDL files created by the new file wizard? It >seems to always use std_logic_arith and std_logic_unsigned, and I >can't find a setting anywhere to modify this. I remember from my days >of using Quartus that there was a text are in the settings menus where >this could be changed. There's got to be something similar in ISE, >right? If enouch people raise WebCases on this, Xilinx might eventually do something about it. - BrianArticle: 134219
On Jun 24, 9:49 pm, explore <chethanzm...@gmail.com> wrote:
> Hello Austin,
> Thanks for responding.
>
> This is for a Virtex 5 LX110t device on a Avnet PCIE board AES-XLX-
> V5LXT-PCIE110-G. I am trying a near-end PMA serial-loopback just
> because the xaui core came with this default setting. For now I have
> been following the instructions provided in UG196 about loopback modes
> (chapter 9 in UG 196). Mainly, my task here is to control the
> loopback externally (through the device driver). The verilog code that
> controls the loopback as it came with xaui v7.2 is as follows.
>
> assign loopback_int = mgt_loopback ? 3'b010 : 3'b000;
>
> mgt_loopback is an output from the xaui core (the 'blackbox'). The
> near-end PMA loopback("010") is enabled if mgt_loopback is high. The
> mgt_loopback can be set high through the DRP or the MDIO interface as
> suggested in the user-guides (UG196 and UG150). My issue specifically
> is to know how these DRP ports can be configured in order to setup an
> internal loopback and control it through my device driver.
>
> I would be happy to know your suggestions on this.
>
> Thanks,
> Chethan
>
> On Jun 23, 6:08 pm, austin <aus...@xilinx.com> wrote:> Chetan,
>
> > What device family? V2P, V4, or V5?
>
> > Also, there is a serial loopback, and a parallel loopback. And, if that
> > is not enough, are we talking near end, or far end which is looping back?
>
> > Generally, a parallel or digital loopback checks the function and the
> > logic (step one of any testing). Then a near end serial loopback will
> > check the analog side. Often the serial loopback must have a good
> > transmit termination, as reflections may cause errors. In this sense,
> > looping back with nothing connected may fail due to reflections (get out
> > the scope). Following that, looping back the far end on its parallel
> > side will successfully check the analog and digital of the near end, and
> > the analog looped back at the far end. Then the only thing not checked
> > is synchronization (far end clock vs near end clock). For testing the
> > clocking, you need a mode at the far end to use either the local clock,
> > or to re-use the received clock. If you use the far end local clock,
> > then you also need a loopback at the far end after the receive FIFO,
> > before the transmit FIFO so that all of the design is tested.]
>
> > Loopback testing can be a major task:
>
> >http://www.juniper.net/techpubs/software/junos/junos76/swconfig76-net...
>
> >http://www.credence.com/technical-library/open-docs/test-trends_loopb...
>
> > Austin
hey dude.though it is difficult but you need not to suffer in
loopback using DRP use the coregen create ur own top module with the
generated GTP rocketIO instantiation file.In that file modify the
value of the parameter called loopback to 001 for pcs loopback ,010
for pma loopback and 000 for normal operation.( these are all near end
loopbacks).i already finished these things and tested them.Now i am
working on the far end loopbacks.
Article: 134220On Jul 31, 11:20=A0am, "Symon" <symon_bre...@hotmail.com> wrote: > =A0if write =3D '1' then > =A0 irq <=3D0; > =A0 reload <=3D dbus; > =A0elsif falling_edge(clock) then > =A0 if counter =3D 0 then > =A0 =A0counter <=3D reload; > =A0 =A0irq <=3D '1'; > =A0 else > =A0 =A0counter <=3D counter - 1; > =A0 =A0irq <=3D '0'; -- AUTO EOI > =A0 end if; > =A0end if; > > I know I shouldn't do homework for people but what the hey. Use the write > signal as an asynchronous reset. Also, use numeric.std . It's lovely. > > http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf > > HTH, Syms. Yes, it definately helps, thank you! I'll see about that numeric.std This isn't homework, I'm learning on my own, more or less from scratch. If I was a student, I would say so.Article: 134221
I often look through waveform views with many screens worth of signals, so I like to re-arrange the signals to have those of interest at the top of the view. With ModelSim PE 5.7, I could find the signals I wanted, select them, then cut (Ctrl+X), go to the top of the window (Ctrl +Home) and paste (Ctrl+V) these signals at the top of the window. Now with ModelSim 6.3, I find that this trick doesn't work with multi-bit vectors anymore. I get errors like: # Paste insertion failed: sim:/tst_brd_test/uut/app_af_addr: The "- min" and "-max" options can only be used with analog formats. I have no clue what this error message means, but my only work- around is to painfully drag the vector to the top of the window, waiting for an annoyingly slow scroll when the signal needs to move more than a screen's height. Is there a better way to do this? Regards, GaborArticle: 134222
On 31 Jul, 11:13, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Wed, 30 Jul 2008 06:41:15 -0700 (PDT), Dave <dhsch...@gmail.com> > wrote: > > >Does anyone know of a way to modify which VHDL libraries ISE > >automatically uses in VHDL files created by the new file wizard? It > >seems to always use std_logic_arith and std_logic_unsigned, and I > >can't find a setting anywhere to modify this. I remember from my days > >of using Quartus that there was a text are in the settings menus where > >this could be changed. There's got to be something similar in ISE, > >right? > > If enouch people raise WebCases on this, Xilinx might eventually do > something about it. > > - Brian I raised a webcase on this back in 2006, and was told a change request (CR # 425340) has already been filed and is scheduled to be fixed in a later software release. I was running 8.2 at the time, so we've already gone through a couple of software releases and still no fix. Maybe one of the Xilinx people here could chase up the CR and give us an idea of when it will be fixed. Neill.Article: 134223
On Jul 30, 5:57 pm, Andy <jonesa...@comcast.net> wrote: > On Jul 30, 10:25 am, rickman <gnu...@gmail.com> wrote: > > > > > One other point. I don't write code for beginners to understand. I > > write for a typical programmer or sometimes just for myself. I do > > want the code to be readable, but I don't feel a need to "dumb" it > > down for others. > > > Rick > > I think that's one of the points some of us are trying to get at. I understand the point, very well. I just don't agree. No one has made any significant argument to support that point. I just see a lot of hand waving and overstatement. > The > verilog syntax you seek is not well understood by a vhdl audience.. Duh! It is not part of VHDL. I am suggesting that it become part of VHDL. Then no one would have the excuse that it is not VHDL so I don't know it. > Write your code where only you can read it, and you will have to > maintain it, because no one else can (that may be a goal, but not for > me). Many of us work in environments which require peer reviews, where > making the code more easily readable by others (programmers, but maybe > not experts) pays dividends. Here is an example of overstatement. Are you really suggesting that the code we are discussing would be so obtuse that "only you can read it"??? I think that is overstated to the point of absurdity. Yes, it may take someone a few seconds or possibly even minutes the first time to look up the command. But if they have to look it up more than once or can't remember it, then the problem is not due to my use of the command... > I prefer to write code that expresses the behavior more clearly, if > not necessarily the implemented structure. Different synthesis tools, > target architectures or optimization goals may result in different > implementations, which is fine as long as they meet timing/resource > requirements and match the RTL behavior. When they do not meet timing > or resource requirements, then (and only then) I revert to trying to > coax the implementation I have in mind out of the synthesis tool, by > modifying the code structure to get the implementation I want. I agree. The behavior I wanted to describe was a mux feeding an AND gate. Obviously this was not an implementation since these constructs don't exist in the FPGA. I just want the simplest and concise description that is easy to read and I think that the sel?a:b construct fits that need. RickArticle: 134224
Although not the focus of the tutorial, the MultiBoot tutorial for the Avnet Spartan-3A Evaluation board uses command-line batch files to build the example designs. Go to www.em.avnet.com/spartan3a-evl then click on Support Files & Downloads, then underneath the App Notes/Ref Designs, download the tutorial called "MultiBoot in Serial and Parallel Flash." Besides the batch file and source HDL and UCF, there are two other files used in the example, both related to calling XST on the command- line. The .ifn file contains the synthesis options and references the .prj file which has the list of HDL sources. Like Goli, I have not used command-line to do simulations. Bryan
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