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Dear I am looking for documnet about initilization of IP core. For example, for following JPEG IP (or DCT IP), I am interested in detailed steps and time "from RESET IP to ACTUAL OPERATION". http://www.xilinx.com/products/logicore/alliance/cast/cast_jpeg_decoder.pdf If someone knows how long does it take, or if there is document, please let us know. Thank you in advanceArticle: 134151
Zhane wrote: >> >> You can not connect directly to the PADs but instead you should >> connect to the signals on the fabric side of the IBUFs and OBUFs. >> HTH., Syms. > > ??? > Sorry I dont know what you mean by "the signals on the fabric side of > the IBUFs and OBUFs" > > can explain to me? When you use the inserter, don't make connections to the greyed out signals. The ones with 'Base Type' described as PORT. These signals only attach to the fabric through IBUFs and OBUFs. So, you can't connect them to Chipscope. Only connect to blacked signals. (You see what they've done there?) HTH., Syms.Article: 134152
"RCIngham" <robert.ingham@gmail.com> ha scritto nel messaggio news:5omdnbYYqdJYBRDVRVn_vwA@giganews.com... > > >>"John_H" <newsgroup@johnhandwork.com> ha scritto nel messaggio >>news:MM6dnaCHurSKUhTVnZ2dnUVZ_oPinZ2d@comcast.com... >>> Here's a shot in the dark: >>> >>> Are you certain the clock edge is where you want it relative to the > data >>> setup and hold time requirements? >> >>The spi driver runs concurrently with the card controller >>logic, in its own state machine. So it has the chance to >>drive clock and data with the right phase according to >>cpol = 0, cpha = 0. Simulation shows a 90 degrees >>phase shift between sck and mosi. >> > > That is probably not optimal. For *most* SPI interfaces, you want SCK > rising edge in the middle of the MOSI and MISO periods. > That's what i meant. The clock rises in the middle of MOSI "bit pulse". Anyway since i'm still fixing a bug in the application part of the project, i've just run a simulation again and i actually see that MOSI changes on every falling edge of SCK. When SCK rises MOSI is stable. Considering the 0xFE/0xFC mismatch as i said before and the corrupted data i got as well,. it seems wierd to me that on every test that failed, i ALWAYS got 0xFC followed by the SAME corrupted data. I'm not sure whether reflections and friends would alter data in different ways on every run. Just a thought.Article: 134153
On Sat, 26 Jul 2008 06:04:01 -0700 (PDT), rickman <gnuarm@gmail.com>
wrote:
>On Jul 26, 7:56 am, Brian Drummond <brian_drumm...@btconnect.com>
>wrote:
>> On Sat, 26 Jul 2008 10:31:32 +0100, Jonathan Bromley
>>
>> It may be personal preference, but I find if-then-else MUCH easier to
>> read in somebody else's code.
>>
>> ?: does save a few of those precious characters though.
>>
>> - Brian
>
>The problem is not so much reading the code, but is writing. I think
>in the terms of the logic, usually a schematic/block diagram. Then I
>try to express that logic in the language.
This may be a cheap shot, but I think it's telling that, even in the
presence of a clear text specification ...
>Example: A data mux controlled by the output of an AND of a signal and
>the output of a mux.
and a correct VHDL description...
> BERTEn <= '0' when BERTSel = '0' else
> not SyncPOSSel when GenEn = '0' else
> not GenPOSSel;
>Compare the two examples to this code...
> BERTEn <= BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;
... the one-line Verilog implementation is either wrong, or confusing to
several industry experts! (I don't know which; I'm definitely not cut
out for Verilog)
I don't believe this was a deliberate plot on Jonathan's or Mike's part
to diss Verilog, but YMMV.
>This is what I expect a concurrent statement to look like, not to
>mention that it represents exactly the image I had in my head and on
>the whiteboard, making it much easier to write.
If you mean the brevity rather than the form, I actually agree, though
as written I couldn't tell you what it does. (Rewritten with
parentheses, I could figure it out eventually)
But I don't see what's wrong with
BERTEn <= BERTSel and ( not SyncPOSSel when GenEn = '1'
else not GenPOSSel);
which I believe does the same thing.
- Brian
Article: 134154On Mon, 28 Jul 2008 12:40:09 +0100, Brian Drummond <brian_drummond@btconnect.com> wrote: >On Sat, 26 Jul 2008 06:04:01 -0700 (PDT), rickman <gnuarm@gmail.com> >wrote: >>Compare the two examples to this code... >> BERTEn <= BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel; > >... the one-line Verilog implementation is either wrong, or confusing to >several industry experts! (I don't know which; I'm definitely not cut >out for Verilog) > >I don't believe this was a deliberate plot on Jonathan's or Mike's part >to diss Verilog, but YMMV. ... double apology required; sorry Jonathan, re-reading the thread, I see I took your name in vain here, and.. ... it would of course be perfectly _possible_ to implement the same bug in VHDL. It is my opinion that the "when" clause calls out to be bracketed so it is less likely to happen, but that is merely opinion. Of course, someone who conditioned themselves to bracketing ?: clauses would also have avoided the ambiguity. But I feel that VHDL's emphasis on expressing something precisely, reduces the likelihood of getting it wrong; (worked in this case!) and that saves time overall. Yes, >> BERTEn <= BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel; is faster to write; but when you factor in the debugging time, which comes out ahead? - BrianArticle: 134155
On Mon, 28 Jul 2008 02:36:57 -0700 (PDT), Zhane <me75@hotmail.com> wrote: >On Jul 28, 4:42 pm, "Symon" <symon_bre...@hotmail.com> wrote: >> "Zhane" <m...@hotmail.com> wrote in message >> >> news:a0d26059-8dae-4527-a877-8f7a29aa391c@p10g2000prf.googlegroups.com... >> >> > Checking expanded design ... >> > ERROR:NgdBuild:924 - bidirect pad net 'sender_BUS<4>' is driving non- >> > buffer >> > primitives: >> >> > what can I do? >> >> You can not connect directly to the PADs but instead you should connect to >> the signals on the fabric side of the IBUFs and OBUFs. >> HTH., Syms. > >??? >Sorry I dont know what you mean by "the signals on the fabric side of >the IBUFs and OBUFs" > >can explain to me? If all else fails, you can instantiate an IBUF primitive in your VHDL code, connect its input to sender_BUS<4>, and its output to a new net, which you connect to the Chipscope core. More likely the IBUF is already there, and its output is on a new net, whose name you need to use when connecting Chipscope. One way to find that net is to look for "sender_BUS<4>" in the RTL viewer; see if it connects to the 'I' pin of an IBUF block, and find the net connected to the 'O' pin. (Another way is to search the post-synthesis simulation VHDL file in a text editor for the same information. If the viewer is too slow or keeps crashing :-) - BrianArticle: 134156
Hi Scott,
Scott Gravenhorst wrote:
> I have a Spartan-3A DSP 1800A development board which comes with no
...
> Does anyone know
> if Will this cable (Digilent Parallel III) works with this board and
> iMPACT or any other Windows based FPGA programmer software?
I've 'upgraded' from a Spartan-3 starter kit to the 3A DSP 1800 board a
while back. And I'm using the Parallel -> JTAG cable (from Digilent)
that came with the first, without trouble. I don't know about Windows,
but I'm using IMPACT under Linux and it programs the 1800A fine every time.
The cable that I have officially works at 2.8V (and above) whereas the
3A DSP 1800 kit runs its JTAG at 2.5V, but this has not been a problem
for me. Newer models of the Digilent Parallel cable are specified from
1.8V and up ('JTAG3 cable') but I haven't tried those.
Given all the hassle with proprietary USB drivers, firmwares etc. I'm
staying away from USB based programmers for now.
Regards, Paul Boven.
Article: 134157the only grey ones are sender_clk, sender_button and sender_GO. I havent made any connection with these three.... NET NAME SOURCE INSTANCE SOURCE COMPONENT BASE TYPE ========================================================================= sender_CLK_BUFGP sender_CLK_BUFGP BUFGP BUFGP sending_send sending_send FDE FDE Inst_sending/sending_sent Inst_sending/sending_sent FDE FDE sending_STS sending_STS FDE FDE Inst_reading/reading_DATARDY Inst_reading/reading_DATARDY FDE FDE reading_STS reading_STS FDE FDE reading_READ reading_READ FDE FDE Inst_reading/reading_DONE Inst_reading/reading_DONE FDE FDE reading_BURSTCOUNT reading_BURSTCOUNT FDE FDE prior_read_status_FFd1 prior_read_status_FFd1 FDE FDE mode_state_FFd1 mode_state_FFd1 FDE FDE mode_state_FFd6 mode_state_FFd6 FDE FDE mode_state_FFd5 mode_state_FFd5 FDE FDE mode_state_FFd3 mode_state_FFd3 FDE FDE mode_state_FFd2 mode_state_FFd2 FDE FDE sending_tpmGO sending_tpmGO FDE FDE mode_state_FFd4 mode_state_FFd4 FDE FDE burstCount burstCount_15 FDE FDE burstCount burstCount_14 FDE FDE burstCount burstCount_13 FDE FDE burstCount burstCount_12 FDE FDE burstCount burstCount_11 FDE FDE burstCount burstCount_10 FDE FDE burstCount burstCount_9 FDE FDE burstCount burstCount_8 FDE FDE burstCount burstCount_7 FDE FDE burstCount burstCount_6 FDE FDE burstCount burstCount_5 FDE FDE burstCount burstCount_4 FDE FDE burstCount burstCount_3 FDE FDE burstCount burstCount_2 FDE FDE burstCount burstCount_1 FDE FDE burstCount burstCount_0 FDE FDE prev_state prev_state_4 FDE FDE prev_state prev_state_3 FDE FDE prev_state prev_state_1 FDE FDE prev_state prev_state_0 FDE FDE readLength readLength_31 FDE FDE readLength readLength_30 FDE FDE readLength readLength_29 FDE FDE readLength readLength_28 FDE FDE readLength readLength_27 FDE FDE readLength readLength_26 FDE FDE readLength readLength_25 FDE FDE readLength readLength_24 FDE FDE readLength readLength_23 FDE FDE readLength readLength_22 FDE FDE readLength readLength_21 FDE FDE readLength readLength_20 FDE FDE readLength readLength_19 FDE FDE readLength readLength_18 FDE FDE readLength readLength_17 FDE FDE readLength readLength_16 FDE FDE readLength readLength_15 FDE FDE readLength readLength_14 FDE FDE readLength readLength_13 FDE FDE readLength readLength_12 FDE FDE readLength readLength_11 FDE FDE readLength readLength_10 FDE FDE readLength readLength_9 FDE FDE readLength readLength_8 FDE FDE readLength readLength_7 FDE FDE readLength readLength_6 FDE FDE readLength readLength_5 FDE FDE readLength readLength_4 FDE FDE readLength readLength_3 FDE FDE readLength readLength_2 FDE FDE readLength readLength_1 FDE FDE readLength readLength_0 FDE FDE Inst_reading/reading_DATAOUT Inst_reading/reading_DATAOUT_3 FDE FDE Inst_reading/reading_DATAOUT Inst_reading/reading_DATAOUT_2 FDE FDE Inst_reading/reading_DATAOUT Inst_reading/reading_DATAOUT_1 FDE FDE Inst_reading/reading_DATAOUT Inst_reading/reading_DATAOUT_0 FDE FDE sendLength sendLength_31 FDE FDE sendLength sendLength_30 FDE FDE sendLength sendLength_29 FDE FDE sendLength sendLength_28 FDE FDE sendLength sendLength_27 FDE FDE sendLength sendLength_26 FDE FDE sendLength sendLength_25 FDE FDE sendLength sendLength_24 FDE FDE sendLength sendLength_23 FDE FDE sendLength sendLength_22 FDE FDE sendLength sendLength_21 FDE FDE sendLength sendLength_20 FDE FDE sendLength sendLength_19 FDE FDE sendLength sendLength_18 FDE FDE sendLength sendLength_17 FDE FDE sendLength sendLength_16 FDE FDE sendLength sendLength_15 FDE FDE sendLength sendLength_14 FDE FDE sendLength sendLength_13 FDE FDE sendLength sendLength_12 FDE FDE sendLength sendLength_11 FDE FDE sendLength sendLength_10 FDE FDE sendLength sendLength_9 FDE FDE sendLength sendLength_8 FDE FDE sendLength sendLength_7 FDE FDE sendLength sendLength_6 FDE FDE sendLength sendLength_5 FDE FDE sendLength sendLength_4 FDE FDE sendLength sendLength_3 FDE FDE sendLength sendLength_2 FDE FDE sendLength sendLength_1 FDE FDE sendLength sendLength_0 FDE FDE PCRcount PCRcount_5 FDE FDE PCRcount PCRcount_4 FDE FDE PCRcount PCRcount_3 FDE FDE PCRcount PCRcount_2 FDE FDE PCRcount PCRcount_1 FDE FDE PCRcount PCRcount_0 FDE FDE sending_datain sending_datain_6 FDE FDE sending_datain sending_datain_5 FDE FDE sending_datain sending_datain_4 FDE FDE sending_datain sending_datain_3 FDE FDE sending_datain sending_datain_2 FDE FDE sending_datain sending_datain_1 FDE FDE sending_datain sending_datain_0 FDE FDE prior_send_status_FFd2 prior_send_status_FFd2 FDE FDE prior_send_status_FFd1 prior_send_status_FFd1 FDE FDE mode_check_count mode_check_count_0 FDE FDE mode_check_count mode_check_count_1 FDE FDE mode_check_count mode_check_count_2 FDE FDE Inst_sending/Mtridata_out_bus Inst_sending/Mtridata_out_bus_0 FDE FDE Inst_sending/Mtridata_out_bus Inst_sending/Mtridata_out_bus_1 FDE FDE Inst_sending/Mtridata_out_bus Inst_sending/Mtridata_out_bus_2 FDE FDE Inst_sending/Mtridata_out_bus Inst_sending/Mtridata_out_bus_3 FDE FDE Inst_sending/Mtridata_out_bus Inst_sending/Mtridata_out_bus_4 FDE FDE Inst_sending/Mtrien_out_bus Inst_sending/Mtrien_out_bus FDE FDE Inst_sending/WREN Inst_sending/WREN FDE FDE Inst_reading/STSstate_FFd1 Inst_reading/STSstate_FFd1 FDE FDE Inst_reading/STSstate_FFd2 Inst_reading/STSstate_FFd2 FDE FDE Inst_reading/Mtridata_out_bus Inst_reading/Mtridata_out_bus_0 FDE FDE Inst_reading/Mtridata_out_bus Inst_reading/Mtridata_out_bus_1 FDE FDE Inst_reading/Mtridata_out_bus Inst_reading/Mtridata_out_bus_2 FDE FDE Inst_reading/Mtridata_out_bus Inst_reading/Mtridata_out_bus_3 FDE FDE Inst_reading/Mtridata_out_bus Inst_reading/Mtridata_out_bus_4 FDE FDE Inst_reading/bursted Inst_reading/bursted FDE FDE Inst_reading/Mtrien_out_bus Inst_reading/Mtrien_out_bus FDE FDE Inst_reading/WREN Inst_reading/WREN FDE FDE Inst_reading/LPCstate_FFd4 Inst_reading/LPCstate_FFd4 FDE FDE Inst_reading/LPCstate_FFd3 Inst_reading/LPCstate_FFd3 FDE FDE Inst_reading/LPCstate_FFd2 Inst_reading/LPCstate_FFd2 FDE FDE Inst_reading/LPCstate_FFd1 Inst_reading/LPCstate_FFd1 FDE FDE Inst_sending/LPCstate_FFd4 Inst_sending/LPCstate_FFd4 FDE FDE Inst_sending/LPCstate_FFd3 Inst_sending/LPCstate_FFd3 FDE FDE Inst_sending/LPCstate_FFd2 Inst_sending/LPCstate_FFd2 FDE FDE Inst_sending/LPCstate_FFd1 Inst_sending/LPCstate_FFd1 FDE FDE Madd_mode_check_count_addsub00006 XST_GND GND GND sender_BUTTON_IBUF sender_BUTTON_IBUF IBUF IBUF sender_GO_IBUF sender_GO_IBUF IBUF IBUF sending_STS_mux0000 sending_STS_mux00001_INV_0 INV INV N43 Msub_sendLength_addsub0000_lut_INV_0 INV INV N44 Msub_sendLength_addsub0000_lut_INV_0 INV INV N45 Msub_sendLength_addsub0000_lut_INV_0 INV INV N46 Msub_sendLength_addsub0000_lut_INV_0 INV INV N47 Msub_sendLength_addsub0000_lut_INV_0 INV INV N48 Msub_sendLength_addsub0000_lut_INV_0 INV INV N49 Msub_sendLength_addsub0000_lut_INV_0 INV INV N50 Msub_sendLength_addsub0000_lut_INV_0 INV INV N51 Msub_sendLength_addsub0000_lut_INV_0 INV INV N52 Msub_sendLength_addsub0000_lut_INV_0 INV INV N53 Msub_sendLength_addsub0000_lut_INV_0 INV INV N54 Msub_sendLength_addsub0000_lut_INV_0 INV INV N55 Msub_sendLength_addsub0000_lut_INV_0 INV INV N56 Msub_sendLength_addsub0000_lut_INV_0 INV INV N57 Msub_sendLength_addsub0000_lut_INV_0 INV INV N58 Msub_sendLength_addsub0000_lut_INV_0 INV INV N59 Msub_sendLength_addsub0000_lut_INV_0 INV INV N60 Msub_sendLength_addsub0000_lut_INV_0 INV INV N61 Msub_sendLength_addsub0000_lut_INV_0 INV INV N62 Msub_sendLength_addsub0000_lut_INV_0 INV INV N63 Msub_sendLength_addsub0000_lut_INV_0 INV INV N64 Msub_sendLength_addsub0000_lut_INV_0 INV INV N65 Msub_sendLength_addsub0000_lut_INV_0 INV INV N66 Msub_sendLength_addsub0000_lut_INV_0 INV INV N67 Msub_sendLength_addsub0000_lut_INV_0 INV INV N68 Msub_sendLength_addsub0000_lut_INV_0 INV INV N69 Msub_sendLength_addsub0000_lut_INV_0 INV INV N70 Msub_sendLength_addsub0000_lut_INV_0 INV INV N71 Msub_sendLength_addsub0000_lut_INV_0 INV INV N72 Msub_sendLength_addsub0000_lut_INV_0 INV INV N73 Msub_sendLength_addsub0000_lut_INV_0 INV INV N74 Mcount_readLength_lut_INV_0 INV INV N75 Mcount_readLength_lut_INV_0 INV INV N76 Mcount_readLength_lut_INV_0 INV INV N77 Mcount_readLength_lut_INV_0 INV INV N78 Mcount_readLength_lut_INV_0 INV INV N79 Mcount_readLength_lut_INV_0 INV INV N80 Mcount_readLength_lut_INV_0 INV INV N81 Mcount_readLength_lut_INV_0 INV INV N82 Mcount_readLength_lut_INV_0 INV INV N83 Mcount_readLength_lut_INV_0 INV INV N84 Mcount_readLength_lut_INV_0 INV INV N85 Mcount_readLength_lut_INV_0 INV INV N86 Mcount_readLength_lut_INV_0 INV INV N87 Mcount_readLength_lut_INV_0 INV INV N88 Mcount_readLength_lut_INV_0 INV INV N89 Mcount_readLength_lut_INV_0 INV INV N90 Mcount_readLength_lut_INV_0 INV INV N91 Mcount_readLength_lut_INV_0 INV INV N92 Mcount_readLength_lut_INV_0 INV INV N93 Mcount_readLength_lut_INV_0 INV INV N94 Mcount_readLength_lut_INV_0 INV INV N95 Mcount_readLength_lut_INV_0 INV INV N96 Mcount_readLength_lut_INV_0 INV INV N97 Mcount_readLength_lut_INV_0 INV INV N98 Mcount_readLength_lut_INV_0 INV INV N99 Mcount_readLength_lut_INV_0 INV INV N100 Mcount_readLength_lut_INV_0 INV INV N101 Mcount_readLength_lut_INV_0 INV INV N102 Mcount_readLength_lut_INV_0 INV INV N103 Mcount_readLength_lut_INV_0 INV INV N104 Mcount_readLength_lut_INV_0 INV INV N1250 sender_BUS_4_IOBUF IOBUF IOBUF N1251 sender_BUS_3_IOBUF IOBUF IOBUF N1252 sender_BUS_2_IOBUF IOBUF IOBUF N1253 sender_BUS_1_IOBUF IOBUF IOBUF N1254 sender_BUS_0_IOBUF IOBUF IOBUF Msub_sendLength_addsub0000_cy_rt Msub_sendLength_addsub0000_cy_rt LUT1 LUT1 Mcount_readLength_cy_rt Mcount_readLength_cy_rt LUT1 LUT1 prior_read_status_not0001 prior_read_status_not00011 LUT2 LUT2 sending_datain_cmp_eq0020 sending_datain_cmp_eq00201 LUT2 LUT2 sending_datain_cmp_eq0028 sending_datain_cmp_eq00281 LUT2 LUT2 prior_send_status_not0001 prior_send_status_not00011 LUT2 LUT2 Mcount_readLength_eqn_0 Mcount_readLength_eqn_01 LUT2 LUT2 Mcount_readLength_eqn_1 Mcount_readLength_eqn_110 LUT2 LUT2 Mcount_readLength_eqn_2 Mcount_readLength_eqn_210 LUT2 LUT2 Mcount_readLength_eqn_3 Mcount_readLength_eqn_32 LUT2 LUT2 Mcount_readLength_eqn_4 Mcount_readLength_eqn_41 LUT2 LUT2 Mcount_readLength_eqn_5 Mcount_readLength_eqn_51 LUT2 LUT2 Mcount_readLength_eqn_6 Mcount_readLength_eqn_61 LUT2 LUT2 Mcount_readLength_eqn_7 Mcount_readLength_eqn_71 LUT2 LUT2 Mcount_readLength_eqn_8 Mcount_readLength_eqn_81 LUT2 LUT2 Mcount_readLength_eqn_9 Mcount_readLength_eqn_91 LUT2 LUT2 Mcount_readLength_eqn_10 Mcount_readLength_eqn_101 LUT2 LUT2 Mcount_readLength_eqn_11 Mcount_readLength_eqn_111 LUT2 LUT2 Mcount_readLength_eqn_12 Mcount_readLength_eqn_121 LUT2 LUT2 Mcount_readLength_eqn_13 Mcount_readLength_eqn_131 LUT2 LUT2 Mcount_readLength_eqn_14 Mcount_readLength_eqn_141 LUT2 LUT2 Mcount_readLength_eqn_15 Mcount_readLength_eqn_151 LUT2 LUT2 Mcount_readLength_eqn_16 Mcount_readLength_eqn_161 LUT2 LUT2 Mcount_readLength_eqn_17 Mcount_readLength_eqn_171 LUT2 LUT2 Mcount_readLength_eqn_18 Mcount_readLength_eqn_181 LUT2 LUT2 Mcount_readLength_eqn_19 Mcount_readLength_eqn_191 LUT2 LUT2 Mcount_readLength_eqn_20 Mcount_readLength_eqn_201 LUT2 LUT2 Mcount_readLength_eqn_21 Mcount_readLength_eqn_211 LUT2 LUT2 Mcount_readLength_eqn_22 Mcount_readLength_eqn_221 LUT2 LUT2 Mcount_readLength_eqn_23 Mcount_readLength_eqn_231 LUT2 LUT2 Mcount_readLength_eqn_24 Mcount_readLength_eqn_241 LUT2 LUT2 Mcount_readLength_eqn_25 Mcount_readLength_eqn_251 LUT2 LUT2 Mcount_readLength_eqn_26 Mcount_readLength_eqn_261 LUT2 LUT2 Mcount_readLength_eqn_27 Mcount_readLength_eqn_271 LUT2 LUT2 Mcount_readLength_eqn_28 Mcount_readLength_eqn_281 LUT2 LUT2 Mcount_readLength_eqn_29 Mcount_readLength_eqn_291 LUT2 LUT2 Mcount_readLength_eqn_30 Mcount_readLength_eqn_301 LUT2 LUT2 Mcount_readLength_eqn_31 Mcount_readLength_eqn_311 LUT2 LUT2 Inst_reading/Mtridata_out_bus_not0002 Inst_reading/ Mtridata_out_bus_not00021 LUT2 LUT2 N109 N1091 LUT2 LUT2 N147 burstCount_7_mux000171 LUT2 LUT2 N150 burstCount_0_mux000121 LUT2 LUT2 N151 burstCount_11_mux000131 LUT2 LUT2 N149 burstCount_13_mux000131 LUT2 LUT2 N811 Inst_reading/LPCstate_FFd2-In21 LUT2 LUT2 reading_STS_mux0000_map1 reading_STS_mux00002 LUT2 LUT2 N702 sending_datain_mux00001_SW0 LUT2 LUT2 mode_state_FFd4-In_map17 mode_state_FFd4-In42 LUT2 LUT2 mode_state_FFd3-In_map10 mode_state_FFd3-In28 LUT2 LUT2 N694 Inst_sending/LPCstate_FFd3-In1_SW0 LUT2 LUT2 burstCount_6_mux0001_map1 burstCount_6_mux00011 LUT2 LUT2 burstCount_7_mux0001_map11 burstCount_7_mux000138 LUT2 LUT2 burstCount_2_mux00012_map3 burstCount_2_mux000125 LUT2 LUT2 burstCount_1_mux0001_map3 burstCount_1_mux00014 LUT2 LUT2 N1312 burstCount_9_mux000121_SW1 LUT2 LUT2 N1390 sending_datain_mux000024_SW0 LUT2 LUT2 N1429 Inst_reading/reading_DATARDY_mux000012 LUT2 LUT2 N1430 prior_send_status_FFd2-In1 LUT2 LUT2 N152 mode_state_FFd3-In21 LUT2_D LUT2_D N591 burstCount_15_mux0001211 LUT2_D LUT2_D N105 burstCount_11_mux0001211 LUT2_D LUT2_D N153 mode_state_FFd6-In11 LUT2_D LUT2_D N880 burstCount_7_mux00015_SW0 LUT2_D LUT2_D burstCount_8_mux0001_map3 burstCount_15_mux000111 LUT2_D LUT2_D N1445 burstCount_15_mux000111 LUT2_D LUT2_D N1448 mode_state_FFd6-In11 LUT2_D LUT2_D N1449 mode_state_FFd3-In21 LUT2_D LUT2_D N1451 burstCount_11_mux0001211 LUT2_D LUT2_D N1452 burstCount_7_mux00015_SW0 LUT2_D LUT2_D N1456 burstCount_15_mux0001211 LUT2_D LUT2_D N5721 burstCount_1_mux000111_SW0 LUT2_L LUT2_L N599 burstCount_12_mux000113_SW0 LUT2_L LUT2_L mode_check_count_not0002 mode_check_count_not00021 LUT3 LUT3 prev_state_mux0000 prev_state_mux00001 LUT3 LUT3 prev_state_mux0000 prev_state_mux00002 LUT3 LUT3 mode_check_count_mux0002 mode_check_count_mux00021 LUT3 LUT3 sending_datain_mux0000 sending_datain_mux00002 LUT3 LUT3 sending_datain_mux0000 sending_datain_mux0000 LUT3 LUT3 sending_datain_mux0000 sending_datain_mux000043 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux000011 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000121 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000231 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000261 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000271 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000281 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000291 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000301 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000311 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000321 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux000021 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux000033 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux000041 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux000051 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux000061 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux000071 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux000081 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux000091 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000101 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000111 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000131 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000141 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000151 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000161 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000171 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000181 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000191 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000201 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000211 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000221 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000241 LUT3 LUT3 sendLength_mux0000 Mmux_sendLength_mux0000251 LUT3 LUT3 prior_read_status_FFd1-In prior_read_status_FFd1-In1 LUT3 LUT3 N2 Mcount_PCRcount_lut LUT3 LUT3 N3 Mcount_PCRcount_lut LUT3 LUT3 N4 Mcount_PCRcount_lut LUT3 LUT3 N5 Mcount_PCRcount_lut LUT3 LUT3 N6 Mcount_PCRcount_lut LUT3 LUT3 N7 Mcount_PCRcount_lut LUT3 LUT3 Inst_reading/STSstate_FFd1-In Inst_reading/STSstate_FFd1-In35 LUT3 LUT3 Inst_reading/bursted_mux0000 Inst_reading/bursted_mux000035 LUT3 LUT3 N40 burstCount_9_mux00011 LUT3 LUT3 N142 Inst_reading/STSstate_FFd1-In121 LUT3 LUT3 N551 Inst_reading/STSstate_FFd2-In11 LUT3 LUT3 N641 sending_datain_mux000021 LUT3 LUT3 reading_STS_mux0000_map5 reading_STS_mux000010 LUT3 LUT3 Inst_sending/Mtridata_out_bus_mux0000_map3 Inst_sending/ Mtridata_out_bus_mux00007 LUT3 LUT3 N1481 Inst_reading/Mtridata_out_bus_mux0000_SW0 LUT3 LUT3 Inst_sending/Mtridata_out_bus_mux0000_map7 Inst_sending/ Mtridata_out_bus_mux000015 LUT3 LUT3 Inst_sending/Mtridata_out_bus_mux0000_map11 Inst_sending/ Mtridata_out_bus_mux000023 LUT3 LUT3 Inst_sending/Mtridata_out_bus_mux0000_map27 Inst_sending/ Mtridata_out_bus_mux000086 LUT3 LUT3 mode_state_FFd4-In_map22 mode_state_FFd4-In65 LUT3 LUT3 reading_READ_mux0001_map13 reading_READ_mux000143 LUT3 LUT3 N808 sender_BUS_MLTSRCEDGELogicTrst_SW0 LUT3 LUT3 N8111 sender_BUS_MLTSRCEDGELogicTrst_SW0 LUT3 LUT3 N814 sender_BUS_MLTSRCEDGELogicTrst_SW0 LUT3 LUT3 N882 burstCount_9_mux0001_SW0 LUT3 LUT3 burstCount_6_mux0001_map0 burstCount_6_mux00010 LUT3 LUT3 burstCount_7_mux0001_map0 burstCount_7_mux00010 LUT3 LUT3 burstCount_2_mux00012_map2 burstCount_2_mux000124 LUT3 LUT3 burstCount_13_mux0001_map0 burstCount_13_mux00010 LUT3 LUT3 burstCount_14_mux0001_map0 burstCount_14_mux00010 LUT3 LUT3 burstCount_15_mux0001_map11 burstCount_15_mux000131 LUT3 LUT3 burstCount_2_mux0001_map5 burstCount_2_mux00019 LUT3 LUT3 burstCount_4_mux0001_map6 burstCount_4_mux000111 LUT3 LUT3 burstCount_4_mux0001_map7 burstCount_4_mux000113 LUT3 LUT3 N1270 burstCount_12_mux000112_SW1 LUT3 LUT3 N1280 burstCount_7_mux00015_SW1 LUT3 LUT3 N1314 burstCount_9_mux000121_SW2 LUT3 LUT3 N1321 mode_state_cmp_eq000419_SW0 LUT3 LUT3 N1359 burstCount_9_mux00011_SW0_SW0_F LUT3 LUT3 N1408 Inst_reading/Mtridata_out_bus_mux0000_F LUT3 LUT3 N1409 Inst_reading/Mtridata_out_bus_mux0000_G LUT3 LUT3 N1412 Inst_sending/Mtridata_out_bus_mux000074_F LUT3 LUT3 N1413 Inst_sending/Mtridata_out_bus_mux000074_G LUT3 LUT3 N1419 Inst_sending/LPCstate_FFd4-In_G LUT3 LUT3 N1420 Inst_sending/Mtridata_out_bus_mux0000120_F LUT3 LUT3 N1421 Inst_sending/Mtridata_out_bus_mux0000120_G LUT3 LUT3 N1422 Inst_reading/Mtridata_out_bus_mux000053_SW0_F LUT3 LUT3 N1423 Inst_reading/Mtridata_out_bus_mux000053_SW0_G LUT3 LUT3 N1424 Inst_reading/LPCstate_FFd3-In_F LUT3 LUT3 N1427 Inst_sending/Mtridata_out_bus_mux000075_G LUT3 LUT3 N1437 Inst_reading/LPCstate_FFd4-In1 LUT3 LUT3 N1440 Inst_reading/Mtridata_out_bus_mux0000531 LUT3 LUT3 N841 burstCount_5_mux00011111 LUT3_D LUT3_D sending_send_mux0003_map3 sending_send_mux00036 LUT3_D LUT3_D N1282 burstCount_9_mux000121_SW0 LUT3_D LUT3_D N1450 sending_send_mux00036 LUT3_D LUT3_D N1453 burstCount_5_mux00011111 LUT3_D LUT3_D N1458 burstCount_9_mux000121_SW0 LUT3_D LUT3_D N134 burstCount_9_mux000121 LUT3_L LUT3_L burstCount_11_mux0001_map0 burstCount_11_mux00010 LUT3_L LUT3_L burstCount_10_mux0001_map0 burstCount_10_mux00010 LUT3_L LUT3_L burstCount_13_mux000121_map1 burstCount_13_mux0001212 LUT3_L LUT3_L N1355 burstCount_13_mux0001221_SW0 LUT3_L LUT3_L N1401 burstCount_14_mux00013_SW0 LUT3_L LUT3_L sending_tpmGO_not0001 sending_tpmGO_not0001 LUT4 LUT4 sending_STS_not0001 sending_STS_not00011 LUT4 LUT4 burstCount_15_mux0001 burstCount_15_mux000139 LUT4 LUT4 burstCount_14_mux0001 burstCount_14_mux000126 LUT4 LUT4 burstCount_13_mux0001 burstCount_13_mux000118 LUT4 LUT4 burstCount_12_mux0001 burstCount_12_mux000124 LUT4 LUT4 sending_datain_cmp_eq0024 sending_datain_mux000011 LUT4 LUT4 sending_datain_cmp_eq0032 sending_datain_cmp_eq00321 LUT4 LUT4 burstCount_11_mux0001 burstCount_11_mux000121 LUT4 LUT4 burstCount_10_mux0001 burstCount_10_mux000121 LUT4 LUT4 sending_send_mux0003 sending_send_mux000355 LUT4 LUT4 burstCount_9_mux0001 burstCount_9_mux0001 LUT4 LUT4 burstCount_8_mux0001 burstCount_8_mux000122 LUT4 LUT4 burstCount_7_mux0001 burstCount_7_mux000144 LUT4 LUT4 PCRcount_not0001 PCRcount_not00011 LUT4 LUT4 burstCount_6_mux0001 burstCount_6_mux000141 LUT4 LUT4 burstCount_5_mux0001 burstCount_5_mux000129 LUT4 LUT4 reading_STS_mux0000 reading_STS_mux000029 LUT4 LUT4 reading_BURSTCOUNT_mux0005 reading_BURSTCOUNT_mux000524 LUT4 LUT4 burstCount_4_mux0001 burstCount_4_mux000129 LUT4 LUT4 reading_READ_mux0001 reading_READ_mux000157 LUT4 LUT4 burstCount_3_mux0001 burstCount_3_mux0001 LUT4 LUT4 burstCount_2_mux0001 burstCount_2_mux000134 LUT4 LUT4 burstCount_1_mux0001 burstCount_1_mux000121 LUT4 LUT4 burstCount_0_mux0001 burstCount_0_mux0001 LUT4 LUT4 sendLength_not0002 sendLength_not00021 LUT4 LUT4 sending_datain_not0002 sending_datain_not00021 LUT4 LUT4 readLength_not0003 readLength_not00031 LUT4 LUT4 prev_state_mux0000 prev_state_mux0000 LUT4 LUT4 prev_state_mux0000 prev_state_mux0000 LUT4 LUT4 mode_check_count_mux0002 mode_check_count_mux00021 LUT4 LUT4 mode_check_count_mux0002 mode_check_count_mux00022 LUT4 LUT4 prior_send_status_FFd1-In prior_send_status_FFd1-In2 LUT4 LUT4 Inst_sending/Mtridata_out_bus_mux0000 Inst_sending/ Mtridata_out_bus_mux000051 LUT4 LUT4 Inst_sending/Mtridata_out_bus_mux0000 Inst_sending/ Mtridata_out_bus_mux00001 LUT4 LUT4 Inst_sending/WREN_mux0000 Inst_sending/WREN_mux00001 LUT4 LUT4 Inst_sending/_mux0001 Inst_sending/LPCstate_Out231 LUT4 LUT4 Inst_sending/Mtridata_out_bus_not0002 Inst_sending/ Mtridata_out_bus_not00021 LUT4 LUT4 Inst_reading/STSstate_FFd2-In Inst_reading/STSstate_FFd2-In53 LUT4 LUT4 Inst_reading/Mtridata_out_bus_mux0000 Inst_reading/ Mtridata_out_bus_mux0000 LUT4 LUT4 Inst_reading/Mtridata_out_bus_mux0000 Inst_reading/ Mtridata_out_bus_mux00001 LUT4 LUT4 Inst_reading/Mtridata_out_bus_mux0000 Inst_reading/ Mtridata_out_bus_mux00001 LUT4 LUT4 Inst_reading/reading_DATAOUT_mux0000 Inst_reading/ reading_DATAOUT_mux00001 LUT4 LUT4 Inst_reading/reading_DATAOUT_mux0000 Inst_reading/ reading_DATAOUT_mux00001 LUT4 LUT4 Inst_reading/reading_DATAOUT_mux0000 Inst_reading/ reading_DATAOUT_mux00001 LUT4 LUT4 Inst_reading/reading_DATAOUT_mux0000 Inst_reading/ reading_DATAOUT_mux00001 LUT4 LUT4 Inst_reading/WREN_mux0000 Inst_reading/WREN_mux00001 LUT4 LUT4 Inst_reading/_mux0001 Inst_reading/LPCstate_Out211 LUT4 LUT4 Inst_reading/reading_DONE_mux0000 Inst_reading/reading_DONE_mux0000 LUT4 LUT4 mode_state_FFd6-In mode_state_FFd6-In2 LUT4 LUT4 mode_state_FFd5-In mode_state_FFd5-In LUT4 LUT4 mode_state_FFd4-In mode_state_FFd4-In96 LUT4 LUT4 mode_state_FFd3-In mode_state_FFd3-In40 LUT4 LUT4 mode_state_FFd2-In mode_state_FFd2-In16 LUT4 LUT4 mode_state_FFd1-In mode_state_FFd1-In LUT4 LUT4 Inst_reading/LPCstate_FFd2-In Inst_reading/LPCstate_FFd2-In1 LUT4 LUT4 Inst_sending/LPCstate_FFd3-In Inst_sending/LPCstate_FFd3-In2 LUT4 LUT4 sender_BUS_MLTSRCEDGE sender_BUS_MLTSRCEDGELogicTrst LUT4 LUT4 sender_BUS_MLTSRCEDGE sender_BUS_MLTSRCEDGELogicTrst LUT4 LUT4 sender_BUS_MLTSRCEDGE sender_BUS_MLTSRCEDGELogicTrst LUT4 LUT4 sender_BUS_MLTSRCEDGE sender_BUS_MLTSRCEDGELogicTrst LUT4 LUT4 sender_BUS_MLTSRCEDGE sender_BUS_MLTSRCEDGELogicTrst LUT4 LUT4 N135 burstCount_7_mux000161 LUT4 LUT4 N148 burstCount_1_mux000111 LUT4 LUT4 result_8_or0001 result_8_or00011 LUT4 LUT4 N25 burstCount_11_mux000111 LUT4 LUT4 N441 burstCount_12_mux0001112 LUT4 LUT4 N501 burstCount_13_mux00012123 LUT4 LUT4 N116 burstCount_12_mux000113 LUT4 LUT4 N130 burstCount_13_mux0001221 LUT4 LUT4 N311 burstCount_13_mux000111 LUT4 LUT4 N701 burstCount_12_mux000112 LUT4 LUT4 mode_state_cmp_eq0004 mode_state_cmp_eq000452 LUT4 LUT4 N143 Inst_reading/bursted_mux000022 LUT4 LUT4 N31 Inst_sending/LPCstate_FFd3-In1 LUT4 LUT4 Inst_reading/LPCstate_cmp_eq0001 Inst_reading/LPCstate_cmp_eq0001 LUT4 LUT4 N21 prior_send_status_FFd1-In11 LUT4 LUT4 N541 sending_datain_mux00001 LUT4 LUT4 N571 mode_check_count_mux000211 LUT4 LUT4 N01 mode_state_cmp_eq0005_wg_lut LUT4 LUT4 N11 mode_state_cmp_eq0005_wg_lut LUT4 LUT4 N22 mode_state_cmp_eq0005_wg_lut LUT4 LUT4 N32 mode_state_cmp_eq0005_wg_lut LUT4 LUT4 N41 mode_state_cmp_eq0005_wg_lut LUT4 LUT4 N510 mode_state_cmp_eq0005_wg_lut LUT4 LUT4 N610 mode_state_cmp_eq0005_wg_lut LUT4 LUT4 N710 mode_state_cmp_eq0005_wg_lut LUT4 LUT4 N8 mode_state_cmp_eq0014_wg_lut LUT4 LUT4 N9 mode_state_cmp_eq0014_wg_lut LUT4 LUT4 N10 mode_state_cmp_eq0014_wg_lut LUT4 LUT4 N111 mode_state_cmp_eq0014_wg_lut LUT4 LUT4 N12 mode_state_cmp_eq0014_wg_lut LUT4 LUT4 N13 mode_state_cmp_eq0014_wg_lut LUT4 LUT4 N14 mode_state_cmp_eq0014_wg_lut LUT4 LUT4 N15 mode_state_cmp_eq0014_wg_lut LUT4 LUT4 N37 sending_datain_mux0000_SW0 LUT4 LUT4 reading_STS_mux0000_map9 reading_STS_mux000022 LUT4 LUT4 N751 mode_state_FFd5-In_SW0 LUT4 LUT4 Inst_sending/Mtridata_out_bus_mux0000_map14 Inst_sending/ Mtridata_out_bus_mux000036 LUT4 LUT4 reading_BURSTCOUNT_mux0005_map3 reading_BURSTCOUNT_mux00055 LUT4 LUT4 reading_BURSTCOUNT_mux0005_map6 reading_BURSTCOUNT_mux00059 LUT4 LUT4 Inst_sending/Mtridata_out_bus_mux0000_map3 Inst_sending/ Mtridata_out_bus_mux00007 LUT4 LUT4 Inst_reading/bursted_mux0000_map6 Inst_reading/bursted_mux000012 LUT4 LUT4 Inst_reading/bursted_mux0000_map11 Inst_reading/bursted_mux000026 LUT4 LUT4 Inst_reading/STSstate_FFd1-In_map5 Inst_reading/STSstate_FFd1-In13 LUT4 LUT4 Inst_reading/STSstate_FFd1-In_map10 Inst_reading/STSstate_FFd1-In33 LUT4 LUT4 Inst_sending/Mtridata_out_bus_mux0000_map6 Inst_sending/ Mtridata_out_bus_mux000017 LUT4 LUT4 sending_datain_mux0000_map9 sending_datain_mux000024 LUT4 LUT4 Inst_sending/Mtridata_out_bus_mux0000_map3 Inst_sending/ Mtridata_out_bus_mux00009 LUT4 LUT4 Inst_sending/Mtridata_out_bus_mux0000_map9 Inst_sending/ Mtridata_out_bus_mux000021 LUT4 LUT4 Inst_sending/Mtridata_out_bus_mux0000_map21 Inst_sending/ Mtridata_out_bus_mux000067 LUT4 LUT4 Inst_reading/STSstate_FFd2-In_map3 Inst_reading/STSstate_FFd2-In8 LUT4 LUT4 Inst_reading/STSstate_FFd2-In_map15 Inst_reading/STSstate_FFd2-In42 LUT4 LUT4 mode_state_FFd4-In_map6 mode_state_FFd4-In12 LUT4 LUT4 mode_state_FFd2-In_map1 mode_state_FFd2-In2 LUT4 LUT4 mode_state_FFd3-In_map4 mode_state_FFd3-In8 LUT4 LUT4 mode_state_FFd3-In_map9 mode_state_FFd3-In211 LUT4 LUT4 sending_send_mux0003_map9 sending_send_mux000319 LUT4 LUT4 sending_send_mux0003_map14 sending_send_mux000338 LUT4 LUT4 reading_READ_mux0001_map7 reading_READ_mux000116 LUT4 LUT4 reading_READ_mux0001_map8 reading_READ_mux000117 LUT4 LUT4 N809 sender_BUS_MLTSRCEDGELogicTrst_SW1 LUT4 LUT4 N812 sender_BUS_MLTSRCEDGELogicTrst_SW1 LUT4 LUT4 N815 sender_BUS_MLTSRCEDGELogicTrst_SW1 LUT4 LUT4 N827 sender_BUS_MLTSRCEDGELogicTrst_SW0 LUT4 LUT4 N828 sender_BUS_MLTSRCEDGELogicTrst_SW1 LUT4 LUT4 N830 sender_BUS_MLTSRCEDGELogicTrst_SW0 LUT4 LUT4 N831 sender_BUS_MLTSRCEDGELogicTrst_SW1 LUT4 LUT4 mode_state_cmp_eq0004_map6 mode_state_cmp_eq000412 LUT4 LUT4 mode_state_cmp_eq0004_map15 mode_state_cmp_eq000433 LUT4 LUT4 burstCount_6_mux0001_map4 burstCount_6_mux00016 LUT4 LUT4 burstCount_7_mux0001_map4 burstCount_7_mux00017 LUT4 LUT4 N971 burstCount_9_mux00011_SW0 LUT4 LUT4 burstCount_14_mux0001_map2 burstCount_14_mux00013 LUT4 LUT4 burstCount_12_mux0001_map5 burstCount_12_mux0001121 LUT4 LUT4 burstCount_15_mux0001_map3 burstCount_15_mux00016 LUT4 LUT4 burstCount_5_mux0001_map5 burstCount_5_mux00018 LUT4 LUT4 N1260 burstCount_13_mux00012123_SW0 LUT4 LUT4 N1268 burstCount_5_mux0001111_SW0 LUT4 LUT4 N1272 burstCount_11_mux000115_SW0 LUT4 LUT4 N1273 burstCount_11_mux000115_SW1 LUT4 LUT4 N1275 burstCount_10_mux000115_SW0 LUT4 LUT4 N1276 burstCount_10_mux000115_SW1 LUT4 LUT4 N1284 burstCount_5_mux00012_SW0 LUT4 LUT4 N1285 burstCount_5_mux00012_SW1 LUT4 LUT4 N1287 burstCount_7_mux00015_SW2 LUT4 LUT4 N1289 burstCount_7_mux00015_SW3 LUT4 LUT4 N1291 burstCount_12_mux000112_SW0_SW0 LUT4 LUT4 N1293 burstCount_8_mux00012_SW0 LUT4 LUT4 N1294 burstCount_8_mux00012_SW1 LUT4 LUT4 N1296 burstCount_15_mux0001101_SW0 LUT4 LUT4 N1298 burstCount_15_mux0001101_SW1 LUT4 LUT4 N1301 burstCount_9_mux0001_SW2 LUT4 LUT4 N1306 burstCount_0_mux000111_SW2 LUT4 LUT4 N1308 burstCount_0_mux000111_SW3 LUT4 LUT4 N1323 mode_state_cmp_eq000419_SW1 LUT4 LUT4 N1348 mode_state_cmp_eq000452_SW6 LUT4 LUT4 N1360 burstCount_9_mux00011_SW0_SW0_G LUT4 LUT4 N1364 mode_state_cmp_eq000452_SW0_G LUT4 LUT4 N1367 mode_state_cmp_eq000452_SW5_F LUT4 LUT4 N1370 mode_state_cmp_eq000452_SW7_G LUT4 LUT4 N1371 Inst_reading/STSstate_FFd2-In42_SW0 LUT4 LUT4 N1373 Inst_reading/reading_DONE_mux0000_SW2 LUT4 LUT4 N1379 Inst_sending/Mtridata_out_bus_mux000051_SW0 LUT4 LUT4 N1381 mode_state_FFd1-In_SW1 LUT4 LUT4 N1392 Inst_reading/STSstate_FFd1-In13_SW0 LUT4 LUT4 N1394 burstCount_13_mux000111_SW1_SW0 LUT4 LUT4 N1399 burstCount_0_mux0001_SW2 LUT4 LUT4 N1410 mode_state_FFd4-In67_F LUT4 LUT4 N1411 mode_state_FFd4-In67_G LUT4 LUT4 N1414 Inst_sending/LPCstate_FFd2-In_F LUT4 LUT4 N1415 Inst_sending/LPCstate_FFd2-In_G LUT4 LUT4 N1416 Inst_sending/sending_sent_mux0000_F LUT4 LUT4 N1417 Inst_sending/sending_sent_mux0000_G LUT4 LUT4 N1418 Inst_sending/LPCstate_FFd4-In_F LUT4 LUT4 N1425 Inst_reading/LPCstate_FFd3-In_G LUT4 LUT4 N1426 Inst_sending/Mtridata_out_bus_mux000075_F LUT4 LUT4 N1428 Inst_reading/reading_DATARDY_mux000011 LUT4 LUT4 N1431 prior_send_status_FFd2-In2 LUT4 LUT4 N1432 Inst_sending/LPCstate_FFd1-In1 LUT4 LUT4 N1433 Inst_sending/LPCstate_FFd1-In2 LUT4 LUT4 N1434 Inst_reading/LPCstate_FFd1-In1 LUT4 LUT4 N1435 Inst_reading/LPCstate_FFd1-In2 LUT4 LUT4 N1436 Inst_reading/LPCstate_FFd4-In211 LUT4 LUT4 N1438 Inst_reading/LPCstate_FFd4-In2 LUT4 LUT4 N1441 Inst_reading/Mtridata_out_bus_mux0000532 LUT4 LUT4 N20 prev_state_mux000011 LUT4_D LUT4_D N23 burstCount_7_mux000111 LUT4_D LUT4_D N511 burstCount_5_mux0001111 LUT4_D LUT4_D N521 burstCount_7_mux000141 LUT4_D LUT4_D N671 burstCount_2_mux0001222 LUT4_D LUT4_D N531 burstCount_15_mux000181 LUT4_D LUT4_D N681 burstCount_15_mux0001101 LUT4_D LUT4_D N581 mode_state_cmp_eq000419 LUT4_D LUT4_D N964 burstCount_12_mux000112_SW0 LUT4_D LUT4_D N1443 burstCount_7_mux000141 LUT4_D LUT4_D N1444 burstCount_15_mux000181 LUT4_D LUT4_D N1446 burstCount_7_mux000111 LUT4_D LUT4_D N1447 prev_state_mux000011 LUT4_D LUT4_D N1454 mode_state_cmp_eq000419 LUT4_D LUT4_D N1455 burstCount_2_mux0001222 LUT4_D LUT4_D N1457 burstCount_5_mux0001111 LUT4_D LUT4_D N1459 burstCount_15_mux0001101 LUT4_D LUT4_D N1460 burstCount_12_mux000112_SW0 LUT4_D LUT4_D N700 prev_state_mux0000_SW0 LUT4_L LUT4_L N7021 prev_state_mux0000_SW0 LUT4_L LUT4_L sending_send_mux0003_map17 sending_send_mux000348 LUT4_L LUT4_L reading_READ_mux0001_map16 reading_READ_mux000151 LUT4_L LUT4_L burstCount_6_mux0001_map6 burstCount_6_mux000113 LUT4_L LUT4_L burstCount_7_mux0001_map7 burstCount_7_mux000121 LUT4_L LUT4_L burstCount_11_mux0001_map4 burstCount_11_mux00017 LUT4_L LUT4_L burstCount_10_mux0001_map4 burstCount_10_mux00017 LUT4_L LUT4_L burstCount_1_mux0001_map5 burstCount_1_mux000110 LUT4_L LUT4_L burstCount_2_mux0001_map7 burstCount_2_mux000117 LUT4_L LUT4_L burstCount_4_mux0001_map3 burstCount_4_mux00017 LUT4_L LUT4_L N1262 burstCount_14_mux00018_SW0 LUT4_L LUT4_L N1264 burstCount_15_mux000112_SW0 LUT4_L LUT4_L N1266 burstCount_3_mux0001_SW0_SW0 LUT4_L LUT4_L N1278 burstCount_13_mux00016_SW0 LUT4_L LUT4_L N1300 burstCount_9_mux0001_SW1 LUT4_L LUT4_L N1310 burstCount_12_mux0001121_SW0 LUT4_L LUT4_L N1316 burstCount_12_mux0001112_SW0 LUT4_L LUT4_L N1325 mode_state_cmp_eq000419_SW2 LUT4_L LUT4_L N1328 burstCount_9_mux00011_SW0_SW1 LUT4_L LUT4_L N1330 burstCount_13_mux000111_SW0 LUT4_L LUT4_L N1340 mode_state_cmp_eq000452_SW1 LUT4_L LUT4_L N1342 mode_state_cmp_eq000452_SW2 LUT4_L LUT4_L N1345 mode_state_cmp_eq000452_SW4 LUT4_L LUT4_L N1353 burstCount_8_mux00012_SW0_SW0 LUT4_L LUT4_L N1377 burstCount_5_mux00012_SW0_SW0 LUT4_L LUT4_L N1396 mode_state_FFd4-In96_SW0 LUT4_L LUT4_L N1398 burstCount_0_mux0001_SW1 LUT4_L LUT4_L mode_state_cmp_eq0005 mode_state_cmp_eq0005_wg_cy MUXCY MUXCY Mcount_PCRcount_cy Mcount_PCRcount_cy MUXCY MUXCY Mcount_PCRcount_cy Mcount_PCRcount_cy MUXCY MUXCY Mcount_PCRcount_cy Mcount_PCRcount_cy MUXCY MUXCY Mcount_PCRcount_cy Mcount_PCRcount_cy MUXCY MUXCY Mcount_PCRcount_cy Mcount_PCRcount_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Msub_sendLength_addsub0000_cy Msub_sendLength_addsub0000_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY Mcount_readLength_cy Mcount_readLength_cy MUXCY MUXCY mode_state_cmp_eq0005_wg_cy mode_state_cmp_eq0005_wg_cy MUXCY MUXCY mode_state_cmp_eq0005_wg_cy mode_state_cmp_eq0005_wg_cy MUXCY MUXCY mode_state_cmp_eq0005_wg_cy mode_state_cmp_eq0005_wg_cy MUXCY MUXCY mode_state_cmp_eq0005_wg_cy mode_state_cmp_eq0005_wg_cy MUXCY MUXCY mode_state_cmp_eq0005_wg_cy mode_state_cmp_eq0005_wg_cy MUXCY MUXCY mode_state_cmp_eq0005_wg_cy mode_state_cmp_eq0005_wg_cy MUXCY MUXCY mode_state_cmp_eq0005_wg_cy mode_state_cmp_eq0005_wg_cy MUXCY MUXCY mode_state_cmp_eq0014_wg_cy mode_state_cmp_eq0014_wg_cy MUXCY MUXCY mode_state_cmp_eq0014_wg_cy mode_state_cmp_eq0014_wg_cy MUXCY MUXCY mode_state_cmp_eq0014_wg_cy mode_state_cmp_eq0014_wg_cy MUXCY MUXCY mode_state_cmp_eq0014_wg_cy mode_state_cmp_eq0014_wg_cy MUXCY MUXCY mode_state_cmp_eq0014_wg_cy mode_state_cmp_eq0014_wg_cy MUXCY MUXCY mode_state_cmp_eq0014_wg_cy mode_state_cmp_eq0014_wg_cy MUXCY MUXCY mode_state_cmp_eq0014_wg_cy mode_state_cmp_eq0014_wg_cy MUXCY MUXCY mode_state_cmp_eq0014_wg_cy mode_state_cmp_eq0014_wg_cy MUXCY MUXCY prior_send_status_FFd2-In prior_send_status_FFd2-In_f5 MUXF5 MUXF5 Inst_sending/Mtridata_out_bus_mux0000 Inst_sending/ Mtridata_out_bus_mux0000120 MUXF5 MUXF5 Inst_sending/Mtridata_out_bus_mux0000 Inst_sending/ Mtridata_out_bus_mux000075 MUXF5 MUXF5 Inst_sending/Mtridata_out_bus_mux0000 Inst_sending/ Mtridata_out_bus_mux000074 MUXF5 MUXF5 Inst_sending/sending_sent_mux0000 Inst_sending/sending_sent_mux0000 MUXF5 MUXF5 Inst_reading/Mtridata_out_bus_mux0000 Inst_reading/ Mtridata_out_bus_mux000053_f5 MUXF5 MUXF5 Inst_reading/Mtridata_out_bus_mux0000 Inst_reading/ Mtridata_out_bus_mux0000 MUXF5 MUXF5 Inst_reading/reading_DATARDY_mux0000 Inst_reading/ reading_DATARDY_mux00001_f5 MUXF5 MUXF5 Inst_reading/LPCstate_FFd4-In Inst_reading/LPCstate_FFd4-In_f5 MUXF5 MUXF5 Inst_reading/LPCstate_FFd3-In Inst_reading/LPCstate_FFd3-In MUXF5 MUXF5 Inst_reading/LPCstate_FFd1-In Inst_reading/LPCstate_FFd1-In_f5 MUXF5 MUXF5 Inst_sending/LPCstate_FFd4-In Inst_sending/LPCstate_FFd4-In MUXF5 MUXF5 Inst_sending/LPCstate_FFd2-In Inst_sending/LPCstate_FFd2-In MUXF5 MUXF5 Inst_sending/LPCstate_FFd1-In Inst_sending/LPCstate_FFd1-In_f5 MUXF5 MUXF5 N136 Inst_reading/LPCstate_FFd4-In21_f5 MUXF5 MUXF5 mode_state_FFd4-In_map23 mode_state_FFd4-In67 MUXF5 MUXF5 N1327 burstCount_9_mux00011_SW0_SW0 MUXF5 MUXF5 N1338 mode_state_cmp_eq000452_SW0 MUXF5 MUXF5 N1347 mode_state_cmp_eq000452_SW5 MUXF5 MUXF5 N1350 mode_state_cmp_eq000452_SW7 MUXF5 MUXF5 N1375 Inst_reading/Mtridata_out_bus_mux000053_SW0 MUXF5 MUXF5 N1 XST_VCC VCC VCC sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY sendLength_addsub0000 Msub_sendLength_addsub0000_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Result Mcount_readLength_xor XORCY XORCY Mcount_PCRcount Mcount_PCRcount_xor XORCY XORCY Mcount_PCRcount1 Mcount_PCRcount_xor XORCY XORCY Mcount_PCRcount2 Mcount_PCRcount_xor XORCY XORCYArticle: 134158
On Jul 28, 4:14 am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> wrote: > > I would prefer to use one tool which supports the language I am using > instead of a preprocessor which supports some of it by replacing > strings by other strings to be given to another tool which tries to > cope with another part of the language. > > Would you suggest that someone who does not want to use such a > preprocessor should write an entire extended language frontend > (perhaps written by reusing code from a full proper BNF-based VHDL > frontend)? Mr. Rickman expressed concern from a language point of view in terms of syntax more directly modeling his ideal representation not being present in VHDL, not whether or not he was willing to use a preprocessor. The BNF for VHDL 93 for instance, isn't semantically complete, nor is it non-ambiguous. You actually have to understand the language to contemplate making changes to it, and the BNF isn't sufficient. It seems a bit overkill to start anew then replicate most of VHDL. A preprocessor sufficient for Mr. Rickman's preferred concurrent assignment statement form could easily be written in a small AWK or Perl script, passing through elements of a source file not affected. You'd probably be well served maintaining line count between the two versions, making VHDL a bit more ugly. You could also conceivably translate to your preferred syntax from VHDL in an editor like emacs or joe, write in your preferred syntax abstraction and store the file in VHDL. It would be embarrassing to stumble over understanding VHDL in printed form. The question is whether or not someone else could read it comfortably if you did the obverse and made the extended version normative. The point being that in Domain Specific Language, no two domains have perfect intersections, and somewhere, someone is making a compromise. The idea of using a preprocessor was meant as a gauge of how serious Mr. Rickman was for his syntax, a way of actually implementing it without breaking anything, using a method shared with the first C++ implementation. -- =93Blindness can take many forms other than the inability to see. Fanatics are often blinded in their thoughts. Leaders are often blinded in their hearts.=94Article: 134159
On Jul 27, 3:51 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > rickman wrote: > > I think whether this code works for you depends on the push button. I > > have some tactile switches that initially showed *no* bouncing. After > > just a week or two of use they bounce so badly that it is impossible > > to debounce them. > > > The best switch to debounce is a double throw switch. The FF stays in > > a given state until the other contact is made. Very simple, but it > > requires two inputs and a more complex switch. > > Yes, a SPCO switch (classic Micro-switch action) is more complex, > as it has an extra contact, but I cannot see > the 'requires two inputs' in any I have used ? > > Wire one end to Vcc, one to GND, and the contact to the Pin, > and enable the Pin-Keep if you like, and you are done. > > Did you mean a SET/RESET action, which needs two pins, and two > resistors (can be pin-pulldowns) ? > > SPCO switches should be the default on demo-boards, as you can > also clock off them... If you don't have the "pin-keep" (bus-hold) enabled (or available) what state is the input in while the switch is in transition? I would think the input would be floating which is not a good idea. In essence, you are asking the capacitance of the input to perform the bus-hold function. To be honest, I had to look up a SPCO switch. It seems to be a three position switch. Why do you need three positions? Wouldn't a SPDT with break before make do what you are describing? RickArticle: 134160
On Mon, 28 Jul 2008 15:03:05 +0200, Paul Boven <boven@jive.nl> wrote:
>Hi Scott,
>
>Scott Gravenhorst wrote:
>> I have a Spartan-3A DSP 1800A development board which comes with no
>...
>> Does anyone know
>> if Will this cable (Digilent Parallel III) works with this board and
>> iMPACT or any other Windows based FPGA programmer software?
>
>I've 'upgraded' from a Spartan-3 starter kit to the 3A DSP 1800 board a
>while back. And I'm using the Parallel -> JTAG cable (from Digilent)
>that came with the first, without trouble. I don't know about Windows,
>but I'm using IMPACT under Linux and it programs the 1800A fine every time.
>
>The cable that I have officially works at 2.8V (and above) whereas the
>3A DSP 1800 kit runs its JTAG at 2.5V, but this has not been a problem
>for me. Newer models of the Digilent Parallel cable are specified from
>1.8V and up ('JTAG3 cable') but I haven't tried those.
>
>Given all the hassle with proprietary USB drivers, firmwares etc. I'm
>staying away from USB based programmers for now.
>
>Regards, Paul Boven.
Thank you Paul, that's good information. I looked at the Digilent
site and I see the JTAG3 cable says 1.8 volts or more as you pointed
out. At $12.00, it's a no-brainer, it's worth a shot. I just ordered
it, so when I get it, I will post my own test results here.
-- ScottG
Article: 134161
On Jul 28, 7:40 am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Sat, 26 Jul 2008 06:04:01 -0700 (PDT), rickman <gnu...@gmail.com>
> wrote:
>
> >On Jul 26, 7:56 am, Brian Drummond <brian_drumm...@btconnect.com>
> >wrote:
> >> On Sat, 26 Jul 2008 10:31:32 +0100, Jonathan Bromley
>
> >> It may be personal preference, but I find if-then-else MUCH easier to
> >> read in somebody else's code.
>
> >> ?: does save a few of those precious characters though.
>
> >> - Brian
>
> >The problem is not so much reading the code, but is writing. I think
> >in the terms of the logic, usually a schematic/block diagram. Then I
> >try to express that logic in the language.
>
> This may be a cheap shot, but I think it's telling that, even in the
> presence of a clear text specification ...>Example: A data mux controlled by the output of an AND of a signal and
> >the output of a mux.
>
> and a correct VHDL description...
>
> > BERTEn <= '0' when BERTSel = '0' else
> > not SyncPOSSel when GenEn = '0' else
> > not GenPOSSel;
> >Compare the two examples to this code...
> > BERTEn <= BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;
>
> ... the one-line Verilog implementation is either wrong, or confusing to
> several industry experts! (I don't know which; I'm definitely not cut
> out for Verilog)
But it is *not* a Verilog implementation. It is VHDL with a new
construct thrown in. The error (btw, who made the error???) is
because this is not a defined function and since I didn't use
parenthesis, it was open to interpretation with no guidelines. If you
really think that the cause of the misinterpretation by one of us
shows it is a poor construct, then you deserve the verbosity of
VHDL.
A language does not need to protect you from yourself if you are any
good. I realized a long time ago that computer tools were initially
designed for computer designers. But there aren't enough good
designers to go around. So the tools were dumbed down so that the
masses could use them. I don't agree that this is even needed. What
is needed is a bit of education in how to write code that is not hard
to debug and then getting people to use those principles as well as
the principles of good test techniques.
The bottom line is that I don't need to turn a one line statement into
a 9 line program in order to make its meaning clear.
> I don't believe this was a deliberate plot on Jonathan's or Mike's part
> to diss Verilog, but YMMV.
>
> >This is what I expect a concurrent statement to look like, not to
> >mention that it represents exactly the image I had in my head and on
> >the whiteboard, making it much easier to write.
>
> If you mean the brevity rather than the form, I actually agree, though
> as written I couldn't tell you what it does. (Rewritten with
> parentheses, I could figure it out eventually)
Eventually??? It has two operators. One maps exactly to a mux and
the other maps exactly to an AND gate. Why would that take more than
a second to understand???
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|\ ---| \
---| \ | |------
| |----------|__/
---| /
|/
Why would it be hard to translate the code into this diagram?
(assuming that you can view the diagram in a non-proportional font)?
> But I don't see what's wrong with
>
> BERTEn <= BERTSel and ( not SyncPOSSel when GenEn = '1'
> else not GenPOSSel);
> which I believe does the same thing.
Are you sure that this is valid syntax? I was under the impression
that a conditional signal assignment was just that, an assignment, not
an expression to be mixed in with other expressions. I can't get the
Active-HDL compiler to accept it. Did I mess it up or does this not
work?
I guess that is the difference between the VHDL construct and the
selection operator. The selection operator is an expression and the
VHDL construct is an assignment not to be mixed with other
expressions.
Rick
Article: 134162If you are using passive serial, like the table ground msel[..0] and you are done. 3.3/2.5V just means CIII parts are OK with those voltage, but use 3.0V(MAX) for all you IO and pull ups where needed On Jul 27, 9:25=A0am, Paul Urbanus <urbpub...@hotmail.com> wrote: > Hi, my name is Paul, and I'm a long-time Xilinx user. =A0(in your best AA > voice, now: "Hi Paul") I'm doing my first Altera design using a Cyclone > III. The design has a very wide video output bus which drives some > ASICs, so the VCCIO voltage is set to 3.0 so the internal series > terminations can be used. > > I believe I understand the interface rules when VCCIO =3D 3.0V, but now > the relationship between the configuration modes and VCCIO for a given > configuration banks is a bit unclear. > > I plan to use one of the Passive Serial configuration modes and Table > 10-1 in the Cyclone III Handbook shows the following. > > =A0 =A0 =A0Config. Scheme =A0 =A0 =A0 | MSEL[3:0] | Config. Voltage Std > -------------------------+-----------+-------------------- > Passive Serial Standard =A0| =A0 =A00000 =A0 | =A03.3/2.5 V > Active Serial Standard =A0 | =A0 =A00010 =A0 | =A03.3 V > Active Parallel =D716 Fast | =A0 =A00101 =A0 | =A03.3 V > Active Parallel =D716 Fast | =A0 =A00110 =A0 | =A01.8 V > Active Parallel =D716 =A0 =A0 =A0| =A0 =A00111 =A0 | =A03.3 V > Active Parallel =D716 =A0 =A0 =A0| =A0 =A01000 =A0 | =A01.8 V > Active Parallel =D716 =A0 =A0 =A0| =A0 =A01011 =A0 | =A03.0/2.5 V > Passive Serial Fast =A0 =A0 =A0| =A0 =A01100 =A0 | =A03.3/2.5 V > Active Serial Fast =A0 =A0 =A0 | =A0 =A01101 =A0 | =A03.3 V > Fast Passive Par. Fast =A0 | =A0 =A01110 =A0 | =A03.3/2.5 V > Fast Passive Par. Fast =A0 | =A0 =A01111 =A0 | =A01.8/1.5 V > JTAG-based configuration | =A0 =A0XXXX =A0 | =A0 =97 > > X =3D Valid low or high level > > =A0From the above table, it appears that the MSEL pins have different > values for the same configuration mode, with the only difference being > the VCCIO level. > > What is unclear (or rather, a potential problem) is that for both > passive serial modes, the configuration voltage standard is 3.3/2.5V. > Note that 3.0V is conspicuously absent for the passive serial modes. In > fact, the only configuration mode which lists 3.0V is Active Parallel. > > Does this mean that I can't use any configuration mode except Active > Parallel (and JTAG) if all of my VCCIO levels are at 3.0V? > > TIA > > PaulArticle: 134163
On Jul 28, 9:41 am, rickman <gnu...@gmail.com> wrote: > A language does not need to protect you from yourself if you are any > good. I realized a long time ago that computer tools were initially > designed for computer designers. But there aren't enough good > designers to go around. So the tools were dumbed down so that the > masses could use them. I don't agree that this is even needed. What > is needed is a bit of education in how to write code that is not hard > to debug and then getting people to use those principles as well as > the principles of good test techniques. > > Rick If you're so in love with Verilog's capabilities, use verilog. The rest of us, who are apparently not any good since we prefer a strong language like VHDL, will continue to use VHDL. BTW, just in case you want to risk taking our inferior advice, if you are dead set on a more concise notation in currently legal vhdl, then create an array type indexed by boolean (or std_logic). Then create a signal/variable and assign the two elements appropriately. Now you can implement your concise expression by indexing the array with your selection expression. AndyArticle: 134164
rickman wrote: > On Jul 26, 9:38 am, Mike Treseler <mtrese...@gmail.com> wrote: >> rickman wrote: >>> BERTEn <= BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel; >> if BERTSel and GenEn then >> BERTEn <= not SyncPOSSel; >> else >> BERTEn <= not GenPOSSel; >> end if; > > One of us doesn't understand the precedence (I'm not sure which > one...). That is always a good reason for not allowing precedence > defaults to define an expression... > > BERTEn <= BERTSel and (GenEn ? not SyncPOSSel : not GenPOSSel); > > Is that more clear? > > Rick As a potential three-line solution: signal BERTEn_mux_n : std_logic; ... BERTEn_mux_n <= SyncPOSSel when (GenEn = '1') else GenPOSSel; BERTEn <= BERTSel and (not BERTEn_mux_n); And trust in your synthesis tools to fold the intermediate signal. It certainly eliminates any ambiguity about what's going on where in what order. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 134165
I also tried the 2.8V Digilent cable. It failed the first time configuring the 1800A with iMPACT 10.1.02, but worked the 2nd time. I also successfully used iMPACT indirect BPI method to program the Intel 28F128J3 parallel Flash. PC3 will not work to program the on-board serial Flash, although you could look at porting the PicoBlaze programmer to this board as a method for serial Flash programming. BryanArticle: 134166
If you have a single-pole double-throw switch with break before make (or a three-position switch) just connect the center to a pin,and the two terminals to Vcc and ground. Then, inside the chip make the input drive the active, non-inverted output on the same pin. That creates a latch, that you can force either way, and it will respond within about a nanosecond, and will ignore all bounce. Use the lowest drive strength setting. Brute-force shortening the output amy be unconventional, but works like a champ. Peter AlfkeArticle: 134167
When you import a pin assignment file in Quartus, pin group names are not read. Quartus assignes its own group names. Does anyone know how to avoid this? Example I have the following line in the assignment file, AF4,,DataCtrlIO[10],Bidir,3.3-V LVTTL,,,,,DEMOD,,PAD433,13, the group name is DEMOD This does not appear in the pin assignment editor. ThanksArticle: 134168
rickman <gnuarm@gmail.com> wrote:
>On Jul 26, 7:56 am, Brian Drummond <brian_drumm...@btconnect.com>
>wrote:
>> On Sat, 26 Jul 2008 10:31:32 +0100, Jonathan Bromley
>>
>>
>>
>> <jonathan.brom...@MYCOMPANY.com> wrote:
>> >On Fri, 25 Jul 2008 22:46:26 -0700 (PDT), rickman wrote:
>>
>> >>In VHDL an operator can be overloaded. But can a new operator be
>> >>created? There is more than once I would like to use the very concise
>> >>notation available in Verilog such as the select operator. Is there a
>> >>way to create the selection operator in VHDL? Looking at the
>> >>structure, I guess it just doesn't fit the mold for VHDL with three
>> >>operands.
>>
>> More dynamic OO languages support arbitrary operator creation; Smalltalk
>> would be an example, or the old Linn Lingo.
>>
>> It's not VERY complicated _in_that_environment_ where static typing is
>> almost non-existent (strong typing can be rigorous, but implemented at
>> runtime) BUT ...
>> (1) you are limited to the creation of binary operators; so ?: is still
>> tricky, to put it mildly, and
>> (2) operator precedence is usually predetermined and deeply embedded in
>> the parser. The above languages solved this problem by allocating
>> precisely one precedence level to all operators - in other words, use
>> brackets.
>>
>> I suspect extensible operator precedence was the main complexity in
>> ALGOL-68.
>>
>> But anyway I suspect you'd have to destroy VHDL to add extensible
>> operators...
>>
>> >>I know I can create a function for this such as select(sel,a,b), but I
>> >>like the form of the notation sel ? a : b, very clear and concise. I
>> >>guess I could always switch to Verilog... :^)
>>
>> It may be personal preference, but I find if-then-else MUCH easier to
>> read in somebody else's code.
>>
>> ?: does save a few of those precious characters though.
>>
>> - Brian
>
>The problem is not so much reading the code, but is writing. I think
>in the terms of the logic, usually a schematic/block diagram. Then I
>try to express that logic in the language. It is not uncommon that it
>is simply impossible to express the logic in the form I have drawn
>it. Then I have to convolute it to come up with something that is
>what I have drawn, or at least I hope so.
I don't think drawing logic is a good way to start. Using flow charts
usually leads to more simple solutions because it is easier for a
human to optimize a flow chart than a bunch of logic symbols.
>Example: A data mux controlled by the output of an AND of a signal and
>the output of a mux. This is four control signals gated together to
>drive the control on the data mux. Here is what I ended up with.
>
> BERTEn <= '0' when BERTSel = '0' else
> not SyncPOSSel when GenEn = '0' else
> not GenPOSSel;
>
>I don't think that the diagram I drew comes to mind when you see this
>code. Maybe a process with an IF statement would be slightly more
>clear, but the verbosity presents an obfuscation of its own from the
>"clutter" created.
>
>process ( BERTSel, SyncPOSSel, GenEn, GenPOSSel) begin
> if (BERTSel = '0') then
> BERTEn <= '0';
> elsif (GenEn = '0') then
> BERTEn <= not SyncPOSSel
> else
> BERTEn <= not GenPOSSel;
> end if;
>end process;
>
>The clutter is from the sheer size of the code. The first three line
>example is a bit obtuse, the 9 line example is large enough to make it
>hard to see the rest of the code and so to see how it fits into the
>big picture. Compare the two examples to this code...
>
> BERTEn <= BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;
This construction wouldn't be very clear for people that are
relatively new to a programming language. I'd try to avoid it.
How about:
process ( BERTSel, SyncPOSSel, GenEn, GenPOSSel) begin
if (BETRSel and Genen)='0' then
BERTEn <= not SyncPOSSel
else
BERTEn <= not GenPOSSel;
end if;
end process;
The code above makes perfectly clear what you are doing. Besides, I
doubt your examples are describing the same logic.
>This is what I expect a concurrent statement to look like, not to
>mention that it represents exactly the image I had in my head and on
>the whiteboard, making it much easier to write.
>
>I am sure there are those who disagree and much prefer the verbose
>process. Maybe I'm just not cut out for the regimen of VHDL.
I see your point and I agree. I would like to write my programmable
logic in C as well. Neither VHDL or Verilog are easy to use.
Yet, you could run your VHDL code through a C pre-processor. This
would allow macro substitution.
--
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)
Article: 134169On Jul 25, 3:22 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > Hi, > > A pcore in EDK contains the HDL files and a set of data files. > All files are in ASCII format. > The hdl files is in pcores/<your module>_vX_XX_a/hdl/vhdl > The data files is in pcores/<your module>_vX_XX_a/data > > There are two data files that you need. > First the .pao file which contains a the list of HDL files that your modu= le > need. > It can contain reference to other pcores libraries if needed > The second is the .mpd files which contains all information XPS needs. > It contains: type of core, what bus interfaces exists, which > parameters/generics, signals,.. > > There is a document in the installation describing these files, the data > files is called PSF files. > When you use "Create and Import Peripheral" it creates the data files for > you. > You can also look in existing pcores to see what they contains. > > The fit_timer in EDK is very simple and should give you a hint how to cre= ate > a pcore for your LCD module. > You don't need any bus interfaces, just pure signals. > > G=F6ran > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > news:61bf0515-e8b9-44fb-9e8f-268ca7ed6bca@i24g2000prf.googlegroups.com... > On Jul 24, 2:44 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > > > > > Hi, > > > You don't need the FSL_bus. > > You can directly take the MicroBlaze signals FSL0_M_Data, FSL0_M_Full, > > FSL0_M_Write and connect them to your module. > > If you want to do this in EDK, you will need to create a pcore for your > > module and manually connect these signal in XPS. > > You can also make these signal external to the EDK project and connect > > them > > in Project Navigator. > > It's depend on how your design look now. > > > G=F6ran > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > >news:0b840fac-04c0-41a6-8ca1-99593fe48018@l64g2000hse.googlegroups.com..= . > > On Jul 23, 3:26 pm, "Ray D." <ray.delvecc...@gmail.com> wrote: > > > > On Jul 22, 2:34 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > > > > > Hi, > > > > > Then it should be a direct match for the FSL interface. > > > > If MicroBlaze executes a 'put' instruction , it will not write unti= l > > > > the > > > > FSL_M_Full flag is '0' and when it write it will set the FSL_M Writ= e > > > > high > > > > for one clock cycle. > > > > MicroBlaze have plenty of options for the FSL instructions, you can > > > > get > > > > all > > > > about them in the reference manual. > > > > > G=F6ran > > > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > > > >news:693f947e-929e-49f6-939d-d834e0048121@27g2000hsf.googlegroups.co= m... > > > > On Jul 21, 2:36 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrot= e: > > > > > > Hi, > > > > > > Depending a little on how your busy signals work, you might just > > > > > hook > > > > > up > > > > > your module to the FSL interface on MicroBlaze. > > > > > Your busy signal needs be high when it can't accept a new word ev= en > > > > > when > > > > > there is no attempt to write to the module. > > > > > MicroBlaze will also just do one cycle write so your module needs= to > > > > > accept > > > > > a new word in one clock cycle when busy is low. > > > > > > Connect: > > > > > din(7 downto 0) -> FSL0_M_Data(24 to 31) > > > > > din_ready -> FSL0_M_Write > > > > > busy -> FSL0_M_Full > > > > > > You need to enable FSL Interfaces to MicroBlaze with the paramete= r > > > > > C_FSL_LINKS (set it to 1) > > > > > You can write to the fsl interface with the function putfslx, you > > > > > can > > > > > read > > > > > more about this function in the document "OS and Libraries Docume= nt > > > > > Collection". > > > > > > G=F6ran > > > > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > > > > >news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups= .com... > > > > > > > Hey all, > > > > > > > I have a Xilinx Spartan-3E starter board, and I'm implementing = a > > > > > > MicroBlaze processor on the FPGA. I would also like to use the > > > > > > LCD > > > > > > which is on board, and I have already developed a hardware modu= le > > > > > > that > > > > > > takes care of initialization and printing to the LCD. The > > > > > > interface > > > > > > is shown below: > > > > > > > entity LCD_top is > > > > > > Port ( > > > > > > clk : in STD_LOGIC; > > > > > > reset : in STD_LOGIC; > > > > > > > din : in STD_LOGIC_VECTOR (7 downto 0); > > > > > > din_ready : in STD_LOGIC; > > > > > > busy : out STD_LOGIC; > > > > > > > LCD_D : out STD_LOGIC_VECTOR (11 downto 8); > > > > > > LCD_E : out STD_LOGIC; > > > > > > LCD_RS : out STD_LOGIC; > > > > > > LCD_RW : out STD_LOGIC > > > > > > > ); > > > > > > end LCD_top; > > > > > > > I really would like to instantiate this module along with the > > > > > > processor core. My question is this - how would I go about > > > > > > interfacing this with the MicroBlaze processor internal to the > > > > > > FPGA? > > > > > > What I would like to do is define a GPIO port on the processor = to > > > > > > connect to the din, din_ready and busy lines of the LCD module, > > > > > > but > > > > > > I > > > > > > keep getting the following error: > > > > > > > ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO > > > > > > CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD > > > > > > \system.mhs line 150 > > > > > > - connection is not connected to an external port! > > > > > > MPD subproperties IOB_STATE=3DBUF|REG or THREE_STATE=3DTRUE r= equire > > > > > > that the port > > > > > > be connected directly to an external port. > > > > > > > Is there any way to work around this? I realize I could just > > > > > > connect > > > > > > the LCD to the GPIO directly and write software drivers, but I'= m > > > > > > trying to avoid that because I already have the hardware module= in > > > > > > place and working smoothly. It will also be nice to have this > > > > > > separate module so that it does the work of printing to the LCD= , > > > > > > and > > > > > > the processor itself can stay busy with other more important jo= bs. > > > > > > > Also, is there an easier way to add another hardware module > > > > > > without > > > > > > manually editing the generated VHDL files for the core? I'm no= t > > > > > > sure > > > > > > if you can do that within Platform Studio. > > > > > > > Any advice would be much appreciated, thanks! > > > > > > > Ray > > > > > That is how the module works so I'll have to try some of these > > > > options! The busy signal is set high the entire time data is being > > > > written to the LCD. Originally I had a module "program.vhd" that > > > > controlled the LCD module along with a keyboard module that we we h= ad > > > > in place for user input. Within program.vhd, I implement a state > > > > machine and check if the busy signal is high before writing to the > > > > LCD. If busy =3D 0, then I set din_ready high and set the 8-bits o= f > > > > data. This is buffered within the LCD module and you only need to > > > > hold din_ready for a single cycle to write to the LCD. The LCD is > > > > connected over a 4-bit interface to the FPGA and this is taken care= of > > > > within the LCD module. When the writing operation begins busy is s= et > > > > to '1' until complete. > > > > > Ray > > > > OK - I'm new to using the EDK and am having trouble implementing this > > > with the FSL bus. I have a few questions: > > > > 1) When I create a custom peripheral, it generates an HDL wrapper - D= o > > > I simply edit this wrapper by instantiating my LCD_top module as a > > > component within the top level design? > > > > 2) Should I check the box "Generate template driver files to help you > > > implement software interface", or will the provided functions to read > > > and write to the FSL bus suffice? > > > > 3) Do you know of any good tutorials on how to implement a custom > > > peripheral on the FSL bus? I've come across a few for adding > > > peripherals to the other buses, but most that I have found do not > > > follow through with how to edit the VHDL files and correctly add the > > > peripheral to the system in Platform Studio (they simply tell you go > > > to 'Create/Import Custom Peripheral'). > > > > Any help/input is appreciated, thanks! > > > > Ray > > > Two more things - > > > 1) the four output ports of the LCD module must be connected to the > > external FPGA pins in order to drive the LCD. What is the best way to > > go about doing this? Is this something that can be edited within > > Platform Studio or do I need to manually edit VHDL/UCF files? I'm > > assuming I will have to add the outputs to the interface shown below. > > > 2) When I choose the master interface for the FSL bus, the ports are > > defined as follows: > > > -- DO NOT EDIT BELOW THIS LINE --------------------- > > -- Bus protocol ports, do not add or delete. > > FSL_Clk : in std_logic; > > FSL_Rst : in std_logic; > > FSL_S_Clk : out std_logic; > > FSL_S_Read : out std_logic; > > FSL_S_Data : in std_logic_vector(0 to 31); > > FSL_S_Control : in std_logic; > > FSL_S_Exists : in std_logic; > > FSL_M_Clk : out std_logic; > > FSL_M_Write : out std_logic; > > FSL_M_Data : out std_logic_vector(0 to 31); > > FSL_M_Control : out std_logic; > > FSL_M_Full : in std_logic > > -- DO NOT EDIT ABOVE THIS LINE --------------------- > > > You mention that my din(7 downto 0) port should be connected to the > > FSL_M_Data port, but the former is an input while the latter is an > > output. Am I missing something? I tried to define this as a slave > > interface, but that also yields an error when I try to generate the > > bitstream. > > > Thanks. > > I think I understand what you are saying, but I'm still unsure of how > to implement it. I went through the 'Create and Import Peripheral' > wizard to create the pcore and HDL wrapper file, but when you go > through this it asks which bus you wish to attach the peripheral to - > this generated HDL file is an interface file for the FSL bus, > correct? I assumed I needed to edit this file and place my LCD module > within this interface file (with the interface shown in my previous > message). Do I need to go through this wizard to directly connect to > the FSL interface or is this the incorrect method? > > When you say directly take the MicroBlaze signal and connect them to > my module, do you mean edit the aforementioned wrapper ... > > read more =BB G=F6ran , I feel as though I'm very close to implementing this, but still have some questions (hopefully my last few questions!) - I'll first document the steps I have taken: - I implemented my module as a pcore by using the 'Create and Import Peripheral' wizard - this generated the HDL wrapper file as an FSL bus interface (is that correct?). I deleted this file and simply imported my two VHDL LCD files (LCD.vhd, LCD_top.vhd - LCD.vhd is an internal component of LCD_top.vhd) into this directory. - I then edited the MPD file to look as shown below. As you can see, I commented out the bus interface specifications since there should be no FSL bus connection and edited the port declarations. I also added, but commented an IO_INTERFACE. BEGIN lcd_core ## Peripheral Options OPTION IPTYPE =3D PERIPHERAL OPTION IMP_NETLIST =3D TRUE OPTION HDL =3D VHDL ## Bus Interfaces ##BUS_INTERFACE BUS=3DSFSL, BUS_STD=3DFSL, BUS_TYPE=3DSLAVE ##BUS_INTERFACE BUS=3DMFSL, BUS_STD=3DFSL, BUS_TYPE=3DMASTER #IO_INTERFACE IO_IF =3D lcd_0 ## Peripheral ports PORT clk =3D "", DIR=3DI, SIGIS=3DClk PORT reset =3D "", DIR=3DI, SIGIS=3DRst PORT din_ready =3D "", DIR=3DI PORT din =3D "", DIR=3DI, VEC=3D[0:7] PORT busy =3D "", DIR=3DO PORT LCD_D =3D "", DIR=3DO, VEC=3D[8:11] PORT LCD_E =3D "", DIR=3DO PORT LCD_RS =3D "", DIR=3DO PORT LCD_RW =3D "", DIR=3DO END - I edited the PAO file to include my two VHDL LCD modules (LCD.vhd and LCD_top.vhd), and removed the wrapper file that was originally there by default when created. - In the 'Project Information Area', I added the user IP module from the 'IP Catalog' tab - In 'System Assembly View', and the 'Ports' tab, I expanded the core and made the four LCD_x outputs external ports. Now I'm assuming this is where you must connect the remaining signals to the FSL interface, but I don't know how. I choose the option 'New Connection', but this simply edits the MHS file port name. I manually made changes as shown below, but to no avail. BEGIN lcd_core PARAMETER INSTANCE =3D lcd_core_0 PARAMETER HW_VER =3D 1.00.a PORT LCD_RW =3D lcd_core_0_LCD_RW PORT LCD_RS =3D lcd_core_0_LCD_RS PORT LCD_E =3D lcd_core_0_LCD_E PORT LCD_D =3D lcd_core_0_LCD_D PORT clk =3D sys_clk_s PORT reset =3D sys_rst_s # PORT din_ready =3D lcd_core_0_din_ready # PORT din =3D lcd_core_0_din # PORT busy =3D lcd_core_0_busy PORT din_ready =3D FSL0_M_Write PORT din =3D FSL0_M_Data (24 to 31) PORT busy =3D FSL0_M_Full END - Lastly, I added the external ports from the LCD module to the UCF file. First, does this seem like the correct process to implement the hardware peripheral? In the MPD file, do I need to uncomment the IO_INTERFACE option for the LCD_x external outputs? How do I make the connections to the FSL interface within Platform Studio? When I try to generate the bitstream, I get the following error - I'm sure I'm missing some type of port declaration, or am not performing the right set of steps: ERROR:MDT - INST:lcd_core_0 PORT:din_ready - C:\EDK_Test_LCD \system.mhs line 187 - port is driven by a sourceless connector Anyway, thanks so much for helping me throughout this process, and I look forward to hearing back from you again! RayArticle: 134170
Nico Coesel wrote:
>> BERTEn <= BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;
>
> This construction wouldn't be very clear for people that are
> relatively new to a programming language. I'd try to avoid it.
>
> How about:
>
> process ( BERTSel, SyncPOSSel, GenEn, GenPOSSel) begin
> if (BETRSel and Genen)='0' then
> BERTEn <= not SyncPOSSel
> else
> BERTEn <= not GenPOSSel;
> end if;
> end process;
Thread recursion has begun,
and there may be no exit condition ;)
-- Mike Treseler
Article: 134171On Mon, 28 Jul 2008 06:45:19 -0700 (PDT), Zhane <me75@hotmail.com> wrote: >the only grey ones are sender_clk, sender_button and sender_GO. >I havent made any connection with these three.... Search the file for the signal name in question... e.g. sender_BUS_4 you find NET NAME SOURCE INSTANCE SOURCE COMPONENT BASE TYPE ========================================================================= ... >N1250 sender_BUS_4_IOBUF IOBUF IOBUF which tells you that your input signal sender_BUS_4 is connected to an IOBUF block which is the source for an internal signal called N1250. So hook chipscope to N1250. And take a note of what you have done. You can rename N1250 to sender_BUS_4 inside the Chipscope Analyzer, and save the renaming with all your settings later. Repeat for all other signals with errors. - BrianArticle: 134172
On Mon, 28 Jul 2008 07:41:25 -0700 (PDT), rickman <gnuarm@gmail.com>
wrote:
>The bottom line is that I don't need to turn a one line statement into
>a 9 line program in order to make its meaning clear.
Absolutely.
>> (Rewritten with parentheses, I could figure it out eventually)
>
>Eventually??? It has two operators. One maps exactly to a mux and
>the other maps exactly to an AND gate. Why would that take more than
>a second to understand???
For the 2-input mux shown, eventually means a second or two (and book
time to determine the precedence versus "and"). But which way round is
the mux, for example, if negative logic is involved? Or a more complex
expression with a lot more than four signals; try extending the example
to a 13 input mux.
>> But I don't see what's wrong with
>>
>> BERTEn <= BERTSel and ( not SyncPOSSel when GenEn = '1'
>> else not GenPOSSel);
>> which I believe does the same thing.
>
>Are you sure that this is valid syntax? I was under the impression
>that a conditional signal assignment was just that, an assignment, not
>an expression to be mixed in with other expressions.
Unfortunately you are right; that is precisely what is wrong with it.
Not enough coffee this morning, obviously. I apologise for not having
run it through a simulator first; I don't have one on this machine.
I suspect Rob's three-line solution (2 lines + declaration) is as close
as VHDL can come. Or, since and is transitive, just push it through into
the expressions, as I think was suggested;
BERTEn <= ( BERTSel and not SyncPOSSel) when GenEn = '1'
else ( BERTSel and not GenPOSSel);
Which is moderately clear; and likely to be so in six months or four or
ten years when you (or your successor) re-visits the design.
If you are doing this a lot, then do it only once; wrap it in a
function.
>I guess that is the difference between the VHDL construct and the
>selection operator. The selection operator is an expression and the
>VHDL construct is an assignment not to be mixed with other
>expressions.
Yes; the selection would have been an expression; unfortunately it would
have been a nasty wart in the syntax and probably broken the parsing
model. For very limited benefit; 2 is a special case of n.
The conditional assignment is a second best for usability, but fits the
big picture better. Assignment can take other characteristics; "after
4ns" or "guarded", so one more doesn't upset the cart, and it is not
limited to 2 inputs.
I think where we differ is that I side with keeping the big picture
simple and consistent; I believe it pays in the long run, despite the
short term cost, such as an occasional extra line (not 9 please!).
Unfortunately that makes VHDL a hard sell, because it doesn't come
across clearly in a little 1-month or 3-month project.
I repeat I don't know Verilog, but if it has ?: selection operator it
probably inherited that from C, where so many useful-looking oddities
break the principle of simplicity, and in such basic ways, I am forever
amazed (and still, occasionally, surprised. Is it the only language that
lets you declare constants but won't let you use them in a constant
expression when you declare an array? Or that will let you perform
single precision FP arithmetic, then makes the the same code deliver
different results when you abstract it into a function, because it
silently changed to double precision?)
I presume (at least sincerely hope) Verilog is better, but the little
time I spent studying it gave me the same uneasy feeling.
Fortunately I get to choose my hardware language; I'm working on
replacing C and C++ for the software side, but it's going to take a
while.
- Brian
Article: 134173On Jul 29, 9:04=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Mon, 28 Jul 2008 06:45:19 -0700 (PDT), Zhane <m...@hotmail.com> > wrote: > > >the only grey ones are sender_clk, sender_button and sender_GO. > >I havent made any connection with these three.... > > Search the file for the signal name in question... e.g. sender_BUS_4 > > you find > NET NAME =A0 =A0 =A0 =A0SOURCE INSTANCE SOURCE COMPONENT =A0 =A0 =A0 =A0B= ASE TYPE > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > ... > > >N1250 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sender_BUS_4_IOBUF =A0 =A0 =A0IOBUF = =A0 =A0 =A0 =A0 =A0 IOBUF > > which tells you that your input signal sender_BUS_4 is connected to an > IOBUF block which is the source for an internal signal called N1250. > > So hook chipscope to N1250. And take a note of what you have done. > You can rename N1250 to sender_BUS_4 inside the Chipscope Analyzer, and > save the renaming with all your settings later. > > Repeat for all other signals with errors. > > - Brian thanks I shall give it a try later on :)Article: 134174
Hi, I am trying to download the code for slipway+abits as explained in the http://research.cs.berkeley.edu/project/slipway/ (slipway and abits webpage) by using the following command: darcs get http://research.cs.berkeley.edu/project/slipway/edu.berkeley.slipway/ However I keep getting the following error: realdarcs.exe: ./src/edu/berkeley/obits/device/.DS_Store: openBinaryFile: does not exist (No such file or directory) I am mostly interested in being able to download the latest slipway pcb file. Does anybody have a clue as to what is causing this error? Should I be getting the code from an alternate site? Thanks for your help, Rafael University of Puerto Rico
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