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Are there any plans to offer an ISE WebPack version that can run under Vista 64 bit ? TIA, Rog.Article: 130726
On Mar 30, 6:45 pm, "pillar2...@gmail.com" <pillar2...@gmail.com> wrote: > I have Suse 10.3 x86_64 and the install worked fine for me. However, > I can not for the life of me find the executable to start up the > webpack. Do you guys know where it is? It is starting to make me go > crazy. When you say "start up webpack", do you mean the ISE gui? I've not used it, but I did note that the settings.sh is now settings32.sh and is located under the ISE/ directory.Article: 130727
On 31 Mrz., 15:50, rickman <gnu...@gmail.com> wrote: > On Mar 21, 3:20 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > On 21 Mrz., 16:13, rickman <gnu...@gmail.com> wrote: [snip] > If this is your definition of "virtually free" then there is *no* > solution. =A0There are always designs that use all practical amount of > some resource in an FPGA and there are always designs that have tons > of free resources. =A0So how can you talk about using "unused" resources > as if this was some guaranteed amount? =A0On the other hand, there are > going to be an incredibly small number of designs that are using an > FPGA and also can't afford an $0.80 CPU. > > If you want to consider a definition of "virtually free", then I > suggest that you consider the increment between FPGA sizes. =A0In the > Spartan 3 the smallest increment is 2300 LUTs after accounting for the > Xilinx "expanding universe" inflation factor. =A0If your feature uses > one fifth of this amount, then adding it is unlikely to cause the > design to be bumped up to the next size of FPGA and so will be > "free". =A0This equates to 460 LUTs/FFs in the *smallest* device, the > 3S50. =A0As the starting chip size gets larger, the increment gets > larger so that even in the lowly 3S400 "virtually free" means 1,638.4 > LUTs. > > I think that for any but most strict applications, a standard, small > soft core processor is "small enough" to be "virtually free".- Zitierten T= ext ausblenden - > hi Rick, sure the no fully free (no resources) possible, but still much better then existing solutions could be possible. as of your 0.80, eh i am using this approuch in several projects, a smallish FPGA + ultra low cost mcu offer much better price/function ration than one single FPGA, but still if you put any soft-core with decent compiler support into S3-50A you are already using more then 50% (thumb guess) what i would not considered small enough. now if you look other vendors then the smallest FPGA is way smaller than S3-50A and there is nothing at all that would fit. extra mcu is in many cases reasonable solution, but not always the best, like lets say you have a design that uses small logic and needs some processing that can be slow. Now this could be implemented COMPLETLY in S3-50AN while the softcore would run form internal serial flash. now the % of that soft-core directly dictates what is left for the user logic. or you want to implement a system with PCB footprint 6 by 6 mm? you could use AGL060 6x6 mm winbond quad outserial flash 6x5 mm so if double mounted the FPGA and serial flash take 6by6 + caps, but there is no softcore that could fit and make sense. adding a 2x3 mm MCU may also be overkill in some times as soon as you can use next largest FPGA it doesnt make sense anymore maybe, but for consumer products the price is of importance AnttiArticle: 130728
"kislo" <kislo02@student.sdu.dk> wrote in message news:dc2684de-3755-41e7-9616-f120a68661d1@e10g2000prf.googlegroups.com... > Hi, is it possible to force a re initialization from within the fpga ? > if I have, for instance. transfered new configuration data to a flash, > and want to reinitialize the fpga without using the external prog_b > pin ? Can you not just drive the PROG_B pin from the FPGA itself by connecting it to an I/O?Article: 130729
"Sharon Hays" <mamahays@cox.net> wrote in message news:rJ5Ij.7769$CO2.2781@newsfe12.phx... > OK. Remain calm. Deep breath. Let it out slowly. Calm now? I'm > putting > my answers below. > > > J.Lef wrote: > >> Good day to all. >> So today, I decided would be the first day on trying to figure >> out >> my spouses new sewing machine. A babylock dc. >> I purchased a spool of red thread from the local target(I know, I >> know) >> but just wanted to get a spool to learn with. >> I got a spool of thread marked from Singer, and it said was for hand >> or >> machine sewing. > > Well, you know it's not the best thread out there. But you do want > multi-purpose thread for most things. And you picked the best available > choice. So you're fine there. Just don't waste more money buying any more > of that brand. I like Mettler best. Gutterman second best. And Coats & > Clark in a pinch. My fave online thread store: > http://www.uncommonthread.com/Merchant2/merchant.mv?Screen=PROD&Store_Code=UT&Product_Code=METTLER-1161&Category_Code=Mettler-All+Purpose > > You can find all those other places. The link is just so you know what > you're looking for. :) > > >> The first thing I do, is follow the instructions on putting the >> thread >> on the bobbin.(I guess you call this winding the bobbin) > > Correct term. Winding the bobbin. It can be tricky when you first learn. > Don't feel bad, you're FAR from the first to do any of this stuff. I even > have moments when I get in a hurry and still do some of these things. No > biggie. We'll get you through. ;) > >> I have had such problems doing this. >> It seems the thread stops going from the cylinder and gets stuck. >> Isnt >> the thread suppossed to continually release easy from the spool? >> I manually took it in my hand, to unwind some thread, and every few >> turns, it seems to be sticking, and you need a good tug to get more >> thread >> out. >> I know this sounds crazy, but please tell me what I am doing wrong. > > > It doesn't sound crazy. (feeling better?) I want you to look at the > thread > spool carefully. You are looking at the edges of the top and bottom. One > end or the other has a notch cut into it. Sometimes it's hard to see. > Take your fingernail and run it around the edge. You will feel a teeny > slit. That's there so you can slide the thread into it, when not in use, > to keep the spool from unwinding when you don't want it to. The trick is > to find that spot and position it properly. Looking at the pictures of > your wife's machine, you want the slit to be on the right side when you > put > the spool on the machine. The thread will be pulling off to the left, > correct? If you had a vertical thread spool, you would put the slit on > the > bottom. What is happening, is the thread is catching in that slit as the > machine is pulling thread off the spool. Usually all you need to do is > put > the spool on the way I say. Sometimes you will get a deformed spool that > has a notch or a lump on the other end too. If it's a lump, a coarse > emery > board will fill it down. > >> 2) And if you dont mind one more question, >> What speed on the machine should I be using to thread the bobbin. >> The book doesnt state anything, but I seem to remember in the shop, >> she >> used high speed. I left it on the middle speed. > > Generally speaking, if you wind the bobbin at a Moderate speed, the thread > will be more evenly distributed on the bobbin. That's a good thing. You > don't want it all on one side or the other. > > >> So far rounds 1 and 2, machine is leading two rounds to none. >> Oh, Oh, also, one time when the bobbin started to wind, at first it >> was doing fine, then the thread went underneath the bobbin, and starting >> wrapping around underneath the bobbin in the machine. >> It took me half an hour, to unwind it off the underneath spindle by >> hand. I was lucky to get it all out. >> HELP ME < HELP ME >> >> Much regards to all. > > Oh this one is one you won't forget again. You have to make sure the > bobbin > is securely snapped into place before you start winding. If it's not all > the way on the spindle, as it spins, it will raise up a little. (It > achieves lift, ala a helicopter's rotor.) Then suddenly, there's room for > the thread to slip down under and whoo!!! What a mess. You want to > hear/feel the click when you put the bobbin on the winder spindle. Give > it > just a little extra push to make sure it's on there securely. > > Hang in there. You will get this. Just takes practice. Remember, you > never > did anything Perfect the first time. ;) > > Sharon What a superb reply, Sharon, I almost wish I had a problem to put to you! MaryArticle: 130730
On 31 Mrz., 15:31, Kolja Sulimma <ksuli...@googlemail.com> wrote: > On 31 Mrz., 10:46, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > > > I just wanted to mention.. > ok, here come my comments too, FIRST TRIAL with 10.1, 4 minutes after first installation "Errorr:Portability:3, please open webcase" it tells me that it has run OUT memory, and that current memory useage is 312200 kb this is brand new PC with 2GB RAM, its FRESH new OS install, no other applications running than ISE so time to first fatal error has decreased from 20 (ISE 9.X) to 4 minutes. Antti is waiting for 10.x service packs.Article: 130731
On 31 Mrz., 16:18, "David Spencer" <davidmspen...@verizon.net> wrote: > "kislo" <kisl...@student.sdu.dk> wrote in message > > news:dc2684de-3755-41e7-9616-f120a68661d1@e10g2000prf.googlegroups.com... > > > Hi, is it possible to force a re initialization from within the fpga ? > > if I have, for instance. transfered new configuration data to a flash, > > and want to reinitialize the fpga without using the external prog_b > > pin ? > > Can you not just drive the PROG_B pin from the FPGA itself by connecting it > to an I/O? this configure same bitstream not the alternative one as the multiboot does. and: OP asked for solution WITHOUT external drive of prog_b AnttiArticle: 130732
http://forums.xilinx.com/xlnx/blog/article?message.uid=7994 Yeah! Peter and I (and Ken) have a new outlet. Just getting started, so please stop by, check it out, and give us some helpful feedback (before we lose the developers, and are unable to change stuff easily). Don't clutter up things hear, just send comments to me directly. Thanks! AustinArticle: 130733
On 31 Mrz., 16:29, Antti <Antti.Luk...@googlemail.com> wrote: > On 31 Mrz., 15:31, Kolja Sulimma <ksuli...@googlemail.com> wrote: > > > On 31 Mrz., 10:46, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > > > > I just wanted to mention.. > > ok, here come my comments too, FIRST TRIAL with 10.1, 4 minutes after > first installation > > "Errorr:Portability:3, please open webcase" > it tells me that it has run OUT memory, and that current memory useage > is 312200 kb > > this is brand new PC with 2GB RAM, its FRESH new OS install, no other > applications running than ISE > > so time to first fatal error has decreased from 20 (ISE 9.X) to 4 > minutes. > > Antti is waiting for 10.x service packs. after terminating the initial msg popups, another did come with "fatal in gui something" then ISE self-terminated. after opening the project again, doing clean and rerun, following comes: FATAL_ERROR:Simulator:Fuse.cpp:164:$Id: Fuse.cpp,v 1.35 2007/11/07 21:25:47 sonals Exp $ - Failed to link the design Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. FATAL_ERROR:Simulator:Fuse.cpp:164:$Id: Fuse.cpp,v 1.35 2007/11/07 21:25:47 sonals Exp $ - Failed to link the design Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. well done Xilinx, I just installed it on new PC to checkout something quick... and all i get quick are fatal errors and self termination and requests to open webcases... AnttiArticle: 130734
sky465nm@trline4.org wrote: > Jungos tools have a history of totally violating any sane programming rules. Yep. > Maybe you could add another usb card to let them install on different > hardware..? I tried different USB cards, without any luck. I put two different ones in that machine before, because I wanted to try to use two Xilinx USB cables in the same machine. That's another thing I never could get to work... Back then I just used one parallel cable and one USB cable, but even that doesn't work with the mixture of Xilinx and Lattice. I tried almost every combination (Xilinx USB, Lattice Parallel; Lattice USB, Xilinx Parallel; Lattice and Xilinx USB), none works. > Or install the lattice programmer, and then use a win32 port of > the linux driver for the xilinx stuff? Is there a win32 port for the libusb-thing? One thing I could try is the drivers they shopped with ISE10.1. I think I read somewhere that at least in the linux release they now ship a driver based on libusb. Maybe they changed the Windows-driver as well... > I don't know the sanity of the lattice drivers, but likely the Jungo drivers > are to blame. Yep. cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 130735
Hi All,
I have custom board with 4 Spartan-3E (XC3S500E-PQ208). For
configuration I have both JTAG and slave serial access. Slave serial
works fine. However, when I try to identify the JTAG chain the first
FPGA always comes back UNKNOWN.
If I'm correct, impact's response to the identify command lists the
devices in reverse order. So the when it reports this:
'1': : Manufacturer's ID =Xilinx xc3s500e, Version : 0
INFO:iMPACT:1777 -
Reading /opt/xilinx-ProgTools-9.1i/spartan3e/data/xc3s500e.bsd...
INFO:iMPACT:501 - '1': Added Device xc3s500e successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
Version is 0000
'2': : Manufacturer's ID =Xilinx xc3s500e, Version : 0
INFO:iMPACT:501 - '1': Added Device xc3s500e successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
Version is 0000
'3': : Manufacturer's ID =Xilinx xc3s500e, Version : 0
INFO:iMPACT:501 - '1': Added Device xc3s500e successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
Version is 1110
INFO:iMPACT:1588 - '4':The part does not appear to be Xilinx Part.
'4': : Manufacturer's ID =Unknown , Version : 14
INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
the unknown device is actually the first in the chain. Slave serial uses
the same device order, so the problem FPGA is also the first in the
slave serial chain.
- I'm using a Platform Cable USB.
- VCCAUX is 2.5V
- All DONE pins are commoned with a 330R to 2.5V (VCCAUX)
- All PROG_B pins are commoned with a 4.7K to 2.5V
- All INIT_B pins are commoned with a 4.7K to 3.3V (VCCO)
- ISE 9.1i under linux
I've tried isolating the problem FPGA and it will not identify. I've
also isolated the last three, these do identify (and configure).
I'm quite sure it is not a faulty FPGA. I've 4 other boards that show
the same behaviour.
Here are the complete schematics:
http://www.elec.york.ac.uk/intsys/users/ajg112/board.pdf
Any suggestions as to what the problem might be would be a great help
Thanks
Andy
Article: 130736On 31 Mrz., 17:25, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote: > Hi All, > > I have custom board with 4 Spartan-3E (XC3S500E-PQ208). For > configuration I have both JTAG and slave serial access. Slave serial > works fine. However, when I try to identify the JTAG chain the first > FPGA always comes back UNKNOWN. > > If I'm correct, impact's response to the identify command lists the > devices in reverse order. So the when it reports this: > > '1': : Manufacturer's ID =Xilinx xc3s500e, Version : 0 > INFO:iMPACT:1777 - > Reading /opt/xilinx-ProgTools-9.1i/spartan3e/data/xc3s500e.bsd... > > INFO:iMPACT:501 - '1': Added Device xc3s500e successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > Version is 0000 > > '2': : Manufacturer's ID =Xilinx xc3s500e, Version : 0 > INFO:iMPACT:501 - '1': Added Device xc3s500e successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > Version is 0000 > > '3': : Manufacturer's ID =Xilinx xc3s500e, Version : 0 > INFO:iMPACT:501 - '1': Added Device xc3s500e successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > Version is 1110 > INFO:iMPACT:1588 - '4':The part does not appear to be Xilinx Part. > '4': : Manufacturer's ID =Unknown , Version : 14 > > INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > done. > > the unknown device is actually the first in the chain. Slave serial uses > the same device order, so the problem FPGA is also the first in the > slave serial chain. > > - I'm using a Platform Cable USB. > - VCCAUX is 2.5V > - All DONE pins are commoned with a 330R to 2.5V (VCCAUX) > - All PROG_B pins are commoned with a 4.7K to 2.5V > - All INIT_B pins are commoned with a 4.7K to 3.3V (VCCO) > - ISE 9.1i under linux > > I've tried isolating the problem FPGA and it will not identify. I've > also isolated the last three, these do identify (and configure). > > I'm quite sure it is not a faulty FPGA. I've 4 other boards that show > the same behaviour. > > Here are the complete schematics:http://www.elec.york.ac.uk/intsys/users/ajg112/board.pdf > > Any suggestions as to what the problem might be would be a great help > > Thanks > Andy impact select chain debug issue TLR create a string of 128 '11111111111111111.. with some text editor, paste it into edit box for dr shift shift it out you should see JTAG ID of all 4 devices in chain scaned back in if there is 32 bit 1'1 at one end of the return string your chain is broken AnttiArticle: 130737
Antti wrote: > impact select chain debug > issue TLR > > create a string of 128 '11111111111111111.. with some text editor, > paste it into edit box for dr shift > shift it out > you should see JTAG ID of all 4 devices in chain scaned back in > > if there is 32 bit 1'1 at one end of the return string your chain is > broken Here is the output (Cut and paste from the impact log) for this operation done 4 times. You can see how the output is slightly different each time, but the changes are only within the first 32 bits (i.e. the first device) // *** BATCH CMD : bsdebug -scandr 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 TDO Capture Data: 11110000011000000010000010010011000000011100001000100000100100110000000111000010001000001001001100000001110000100010000010010011 // *** BATCH CMD : bsdebug -scandr 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 TDO Capture Data: 11110000000110001001000001000011000000011100001000100000100100110000000111000010001000001001001100000001110000100010000010010011 // *** BATCH CMD : bsdebug -scandr 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 TDO Capture Data: 11100000001110000100010000100001000000011100001000100000100100110000000111000010001000001001001100000001110000100010000010010011 // *** BATCH CMD : bsdebug -scandr 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 TDO Capture Data: 11000000011100001000100001001011000000011100001000100000100100110000000111000010001000001001001100000001110000100010000010010011Article: 130738
On Mar 29, 12:18=A0am, John_H <newsgr...@johnhandwork.com> wrote: > Kevin Neilson wrote: > > mk wrote: > >> On Fri, 28 Mar 2008 11:14:23 -0700 (PDT), FPGA > >> <FPGA.unkn...@gmail.com> wrote: > > >>> what does the following code do > >>> output <=3D input[x*(y)-1 -: y]; > > >> That's called an indexed part select. The first expression signifies > >> base and the second expression signifies width. It the sign is + it's > >> an ascending select if it's negative it's a descending select. Your > >> example is equivalent to input[x*(y)-1: x*(y)-y] ie you need to > >> subtract (y-1) from the base to get the lower index. > > > I think your equivalent should be: =A0input[x*(y)-1: x*(y)-y+1] > > > If I remember correctly, the width has to be a constant. =A0In this case= > > that would mean y could be a parameter, but not an integer or register. > > -Kevin > > The y that follows the indexed part select operator is the width. =A0The > vector mk showed has a width of y bits which is accurate. =A0The vector > Kevin showed has a width of y-1 bits which is inaccurate. =A0Use mk's > suggestion. > > Oh, and invest in a Verilog-2001 reference. > > Also - I removed the cross-post to comp.lang.vhdl because this is > VERILOG! =A0The VHDL abbreviations doesn't mean "Verilog Hardware > Description Language." =A0You can go to comp.lang.verilog for Verilog issu= es. > > - John_H- Hide quoted text - > > - Show quoted text - Thanks always for your valuable help.Article: 130739
Hi everyone, My setup: ISE10.1 webpack, Digilent Spartan 3 kit, ExtremeDSP 1800A kit, Digilent parallel JTAG cable, Ubuntu 7.10. With xc3sprog I can write my configuration files to the Spartan-3 kit. As xc3sprog doesn't support the XC3SD1800A, I switched to using Impact with Michael Gernoth's libusb preloaded by LD_PRELOAD. This works fine for the XC3SD1800A kit, but fails for the Spartan-3 kit, 'done' doesn't go high. Hardware-wise, everything seems fine. Does anyone have an idea what could cause ISE10.1 impact not to work with the XC3S200, but work well with the XC3SD1800A ? Regards, Paul Boven.Article: 130740
On Mar 31, 8:57 am, morphiend <morphi...@gmail.com> wrote: > On Mar 30, 9:15 am, louis <y...@ce.et.tudelft.nl> wrote: > > > Hi, All, > > > I built a PowerPC system on Xilinx ML410 board (Virtex4 fx60), the > > system contains 64K OCM instruction memory and 64K PLB data memory. I > > used XMD to debug the system via the jtagppc, when I reset the system, > > the PC register went back to a address like "0Xfffff048". But > > according to the PPC manual, after reset, the PC should be > > "0Xfffffffc". Does anyone met the similar problem before? > > > regards, > > louis > > How did you perform the reset? Do you have a software program that > you're actively trying to debug and have already "downloaded" onto the > FPGA via the JTAGPPC? If so, your debugger may be seeing the start of > the application as 0xfffff048 instead of 0xfffffffc. Hi, morphiend, I downloaded the bit file onto the FGPA, then used XMD to debug the system via the JTAGPPC. The "reset" I said is to type the "rst" command in the XMD. From Xilinx doc, after reset, the PC register should be back to 0xfffffffc, but why is 0xfffff048? Is this correct? Could you please give more hints? Thanks a lot louisArticle: 130741
On 31 Mrz., 18:20, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote: > Antti wrote: > > =A0 > impact select chain debug > > > issue TLR > > > create a string of 128 '11111111111111111.. with some text editor, > > paste it into edit box for dr shift > > shift it out > > you should see JTAG ID of all 4 devices in chain scaned back in > > > if there is 32 bit 1'1 at one end of the return string your chain is > > broken > > Here is the output (Cut and paste from the impact log) for this > operation done 4 times. You can see how the output is slightly different > each time, but the changes are only within the first 32 bits (i.e. the > first device) > > // *** BATCH CMD : bsdebug -scandr > 11111111111111111111111111111111111111111111111111111111111111111111111111= 1=AD11111111111111111111111111111111111111111111111111111 > > TDO Capture Data: > 11110000011000000010000010010011000000011100001000100000100100110000000111= 0=AD00010001000001001001100000001110000100010000010010011 > > // *** BATCH CMD : bsdebug -scandr > 11111111111111111111111111111111111111111111111111111111111111111111111111= 1=AD11111111111111111111111111111111111111111111111111111 > > TDO Capture Data: > 11110000000110001001000001000011000000011100001000100000100100110000000111= 0=AD00010001000001001001100000001110000100010000010010011 > > // *** BATCH CMD : bsdebug -scandr > 11111111111111111111111111111111111111111111111111111111111111111111111111= 1=AD11111111111111111111111111111111111111111111111111111 > > TDO Capture Data: > 11100000001110000100010000100001000000011100001000100000100100110000000111= 0=AD00010001000001001001100000001110000100010000010010011 > > // *** BATCH CMD : bsdebug -scandr > 11111111111111111111111111111111111111111111111111111111111111111111111111= 1=AD11111111111111111111111111111111111111111111111111111 > > TDO Capture Data: > 11000000011100001000100001001011000000011100001000100000100100110000000111= 0=AD00010001000001001001100000001110000100010000010010011 hm chain aint completly broken, weird well i have seen wrong jtag id been returned, it was digged down to have excessive 100mhz noise on VCCINT AnttiArticle: 130742
On 31 Mrz., 18:27, Paul Boven <bo...@jive.nl> wrote: > Hi everyone, > > My setup: ISE10.1 webpack, Digilent Spartan 3 kit, ExtremeDSP 1800A kit, > Digilent parallel JTAG cable, Ubuntu 7.10. > > With xc3sprog I can write my configuration files to the Spartan-3 kit. > As xc3sprog doesn't support the XC3SD1800A, I switched to using Impact > with Michael Gernoth's libusb preloaded by LD_PRELOAD. This works fine > for the XC3SD1800A kit, but fails for the Spartan-3 kit, 'done' doesn't > go high. > > Hardware-wise, everything seems fine. Does anyone have an idea what > could cause ISE10.1 impact not to work with the XC3S200, but work well > with the XC3SD1800A ? > > Regards, Paul Boven. latest impact are known to fail to configure some parts if mode is not set to JTAG also when configuration flash is erased. with earlier versions it was different. so you may need to traverse back the impact versions to find one that works AnttiArticle: 130743
>I tried different USB cards, without any luck. I put two different ones >in that machine before, because I wanted to try to use two Xilinx USB >cables in the same machine. That's another thing I never could get to >work... Back then I just used one parallel cable and one USB cable, but >even that doesn't work with the mixture of Xilinx and Lattice. >I tried almost every combination (Xilinx USB, Lattice Parallel; Lattice >USB, Xilinx Parallel; Lattice and Xilinx USB), none works. Well one option is to go FreeBSD/Linux. Or setup a jtag server on another machine. This seems like a problem that won't go away unless you create something of your own. Or fake the system for the drivers (ie virtualisation). Ping Xilinx ..?, how are you going to make this work?, I don't find this an acceptable situation. I heard from another user that Intel-cpu-jtag + xilinx-jtag also fails on the same issues. >> Or install the lattice programmer, and then use a win32 port of >> the linux driver for the xilinx stuff? > >Is there a win32 port for the libusb-thing? I don't know the status of libusb on win32. But my tip would be to check: http://libusb-win32.sourceforge.net/ Btw,... google :pArticle: 130744
> When you say "start up webpack", do you mean the ISE gui? Yes > I've not > used it, but I did note that the settings.sh is now settings32.sh and > is located under the ISE/ directory. I am already aware of those files. These files do not invoke the gui. In version 9.2i there was an executable called ise which would invoke the program/gui. I still have not figured out where this file (I have even looked for anything that would be renamed etc) is. NewellArticle: 130745
On 31 Mrz., 21:55, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Antti wrote: > > well done Xilinx, I just installed it on new PC to checkout something > > quick... and all i get quick are fatal errors and self termination and > > requests to open webcases... > > > Antti > > Perhaps you triggered the special 'anti-Antti detector' that Xilinx put > in all their software now ;) > > -jg ROTFL no, the first fatal error and self termination was caused by the reasons explained in AR30373 however after using the supposed workaround "scenarion 3" it took only another 20 minutes to cause next fatal failures and forced termination of ISE AnttiArticle: 130746
Dear all:
My target board is the Xilinx ML310, which contains a Virtex-II
Pro XC2VP30 FPGA. I followed the EAPR flow and successfuly generated
my partial bitstreams. My system architecture was created by using the
EDK tool, where the clock signals of all the DPR modules were
transferred through a gloabal buffer (BUFG) and the HWICAP provided by
the EDK was used in my system architecture. My partial bitstreams can
successfully work by using the iMPACT tool over JTAG, but only the
partial bitstreams for the combinational circuits can successfully
work by using the ICAP. My partial bitstreams for the sequence
circuits cannot successfuly be reconfigured by using the ICAP. I am
very confused with the above problem. Is there something that I have
to consider when I use the ICAP? Similar to the general signals
connected to the DPR modules, my reset signal is connected to the DPR
module by using the busmacro provided by Xilinx. Is the connection
method of the DPR modules for clock and reset signals right?
Besides, I used the "ncd2xdl" command to transform my "nmc" file
of busmacro to the "xdl" file, and then transfromed the "xdl" file
back to nmc file ("xdl2ncd" command) without modifying its content.
The original nmc file was 11 KB, but the new nmc file was only 4 KB
and cannot be used like the original busmacro file. My ISE version is
8.2. Is there anything that I have to modify for the ISE tool? Or
which ISE version can work correctly? Here are my questions. Can
someone help me? Thanks very much!
Best Regards,
Huang
Article: 130747Antti wrote: > well done Xilinx, I just installed it on new PC to checkout something > quick... and all i get quick are fatal errors and self termination and > requests to open webcases... > > Antti Perhaps you triggered the special 'anti-Antti detector' that Xilinx put in all their software now ;) -jgArticle: 130748
Hi, please forgive me for any ignorance in this question, but I am really lost. I have tried to get Xilinx ISE Webpack 9.2i to work with modelsim. But it just doesn't seem to work. Now I am not very familiar with these programs, I am using them because I am doing a school course that uses FPGA and they use Xilinx and Modelsim... I have used them in the labs, but here I am just having trouble to install them. I am able to installed Xilinx ISE Webpack 9.2i, but I cannot find Modelsim in it, so I googled for Modelsim, installed it, but it doesn't do anything. I just don't know what's going on or where should I look at... I just want to install the programs!! Does anyone have any guides on how to get it install and running on Linux? (Kernel 2.6) Thanks.Article: 130749
On Mar 31, 6:27 pm, Paul Boven <bo...@jive.nl> wrote: > Hi everyone, > same issue here..., try to reload once again, then twice... try disconnect starter kit after a while, you should have "done" that goes '1'... > My setup: ISE10.1 webpack, Digilent Spartan 3 kit, ExtremeDSP 1800A kit, > Digilent parallel JTAG cable, Ubuntu 7.10. > > With xc3sprog I can write my configuration files to the Spartan-3 kit. > As xc3sprog doesn't support the XC3SD1800A, I switched to using Impact > with Michael Gernoth's libusb preloaded by LD_PRELOAD. This works fine > for the XC3SD1800A kit, but fails for the Spartan-3 kit, 'done' doesn't > go high. > > Hardware-wise, everything seems fine. Does anyone have an idea what > could cause ISE10.1 impact not to work with the XC3S200, but work well > with the XC3SD1800A ? > > Regards, Paul Boven.
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