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Gabor wrote:
> my only work-around is to painfully
> drag the vector to the top of the window,
> waiting for an annoyingly slow scroll
> when the signal needs to move more than
> a screen's height. Is there a better way to do this?
I write a tcl script of add wave commands,
-- a ".do" file in vsim-speak.
If time allows, I close the loop *in* the testbench
so I don't have to look at waves anymore.
-- Mike Treseler
Article: 134226"Gabor" <gabor@alacron.com> wrote in message news:23a70911-0da5-4c72-8e52-dd8bbdb09035@34g2000hsf.googlegroups.com... >I often look through waveform views with many screens worth of > signals, > so I like to re-arrange the signals to have those of interest at the > top of > the view. With ModelSim PE 5.7, I could find the signals I wanted, > select them, then cut (Ctrl+X), go to the top of the window (Ctrl > +Home) > and paste (Ctrl+V) these signals at the top of the window. > > Now with ModelSim 6.3, I find that this trick doesn't work with > multi-bit vectors anymore. I get errors like: > > # Paste insertion failed: sim:/tst_brd_test/uut/app_af_addr: The "- > min" and "-max" options can only be used with analog formats. > > I have no clue what this error message means, but my only work- > around is to painfully drag the vector to the top of the window, > waiting > for an annoyingly slow scroll when the signal needs to move more than > a screen's height. Is there a better way to do this? > > Regards, > Gabor For what it is worth, I just tried it out in 6.4 under XP and it seems to work OK. If you don't want to change to 6.4 try 6.3h, Hans www.ht-lab.comArticle: 134227
aleksa wrote: > > This isn't homework, I'm learning on my own, more or less from > scratch. > If I was a student, I would say so. Please forgive me. Sadly, not all posters here share your honesty of disclosure. Good luck with your project, Syms.Article: 134228
rickman wrote: > <other things in addition to...> > > I agree. The behavior I wanted to describe was a mux feeding an AND > gate. Obviously this was not an implementation since these constructs > don't exist in the FPGA. I just want the simplest and concise > description that is easy to read and I think that the sel?a:b > construct fits that need. > > Rick I think my main problem with the ?: operator is the same as my problem with goto statements and implicit type casting. It's not an inherently problematic device, and can at times be the clearest way of getting the point across, but it lends itself to abuse. I've certainly seen 10x as much C code obfuscated by some "clever" use of ?: than I've seen code clarified by it. It's like a driver notification device that warns you you're going over 70 mph by crescendoing "Ride of the Valkyries". Theoretically it's a fine tool, but practically it's just begging you floor it for maximum effect. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 134229
Hi there,
I already have the fixed point values for the integers and as they're just
5 coefficients, I have just taken them as constants. Do you think it is
alright? Well, then I am giving input(16-bit {1 sign bit and 15 fractional
bits}) from the switches and buttons on the Spartan-3 board. As there are
just 4 1-bit push buttons and an 8-bit switch (12-bits altogether, and then
I am keeping 4 bits constant). Then the output is also 16-bit which
includes 1 sign bit, 4 integer bits and 11 fractional bits. Now, I have
used the 7-segment display to show the output in such a way that the
leftmost digit is showing the hex value of 4 integer bits, and then a dot
to show decimal point and then the next 3 digits for fractional part but
as there are 11-bits in fractional part, so, I have padded a zero at the
end of fractional part just to make it a 4-bit value for the hex-decoder.
And then I am using the last dp (dot/decimal point on 7-seg display to
indicate the sign of the number).
So, I am only giving input from the board and getting the output and not
using any RAM/ROM or multiplier blocks, I have only used constants and the
operators ('+', '-', '*') and left it all to the VHDL to do all the
intermediate arithmetic and use the hardware components as required, will
it be fine?
Do you think it is a good design?
Now, I was wondering what will be the best option if I wanted to
demonstrate the filter operation more clearly. I mean these are just
numbers that I am showing on the 7-seg display. But if I want to give a
sinusoidal input and get a filtered waveform at the output.
1)I have got the code for vhdl sine generator.
2)Showing the ouput on the oscilloscope? it sounds a bit tedious.
3)Do you think interfacing a microphone and speaker would work for this
design (and for Spartan-3)?
4)or any other application/test case you would suggest for IIR filter on
FPGA?
Thanks very much for your help.
Regards,
Kami
>> Kami
>
>if you use modelsim, just vcom the pkg file first then your other
>design files I think is just fine.
>
Article: 134230Goli wrote: > On Jul 31, 8:31 am, andersod2 <thechrisander...@gmail.com> wrote: >> Am using the free ISE Webpack, and wanted to know if it's possible >> just to use the command line and code/config files...that counts for >> things like package assignments and simulator stuff...can it be done >> at all, or easily? >> >> Thanks for your insights... > > Hi, > > There is a nice command line flow, to get the bit file from your > source files and config files. You could also get the command log file > of your project, from the ISE interface itself. In design utilities, > you have the option of view Command line log file. > > Also you could set up a simple Make environment for the same. I have > build a simple Make environment and for me that works the best. It is > much simpler and easy to use. > > But I have not used command line much for simulation or for assigning > pins, floor planner and so on. I guess for that you need GUI. > > Hope this helps. > > -- > Goli I second the use of Make. I switched over after finally becoming far too pissed off that Project Navigator a) hides all of my project settings in non-version controllable, non-documented binary files that keep getting changed with every revision of ISE and b) crashed all the time. Now I just type "make" at the command line and everything does what I want it to. Manual pin assignment via UCF files works quite well in my experience, especially if you've got a Perl script that rips your signal connections directly from your board schematic file and writes them in UCF format. The only problem is, you go to some trouble to sort them nicely, group and comment them, and then if you ever run the Constraints Editor or PACE programs against it, it re-alphabetizes them. Schematic entry, Floorplanning, and FPGA Editor are still GUI tasks. Schematic entry, infuriatingly, has to be done from inside of Project Navigator, there's no stand-alone executable for it. Also, in my experience, when you're hunting for timing problems, the graphical Timing Analyzer is much easier to work with than the command line one. -- Rob -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 134231
Hi there,
I already have the fixed point values for the integers and as they're just
5 coefficients, I have just taken them as constants. Do you think it is
alright? Well, then I am giving input(16-bit {1 sign bit and 15 fractional
bits}) from the switches and buttons on the Spartan-3 board. As there are
just 4 1-bit push buttons and an 8-bit switch (12-bits altogether, and then
I am keeping 4 bits constant). Then the output is also 16-bit which
includes 1 sign bit, 4 integer bits and 11 fractional bits. Now, I have
used the 7-segment display to show the output in such a way that the
leftmost digit is showing the hex value of 4 integer bits, and then a dot
to show decimal point and then the next 3 digits for fractional part but
as there are 11-bits in fractional part, so, I have padded a zero at the
end of fractional part just to make it a 4-bit value for the hex-decoder.
And then I am using the last dp (dot/decimal point on 7-seg display to
indicate the sign of the number).
So, I am only giving input from the board and getting the output and not
using any RAM/ROM or multiplier blocks, I have only used constants and the
operators ('+', '-', '*') and left it all to the VHDL to do all the
intermediate arithmetic and use the hardware components as required, will
it be fine?
Do you think it is a good design?
Now, I was wondering what will be the best option if I wanted to
demonstrate the filter operation more clearly. I mean these are just
numbers that I am showing on the 7-seg display. But if I want to give a
sinusoidal input and get a filtered waveform at the output.
1)I have got the code for vhdl sine generator.
2)Showing the ouput on the oscilloscope? it sounds a bit tedious.
3)Do you think interfacing a microphone and speaker would work for this
design (and for Spartan-3)?
4)Or giving the output back to the simulator and showing the waveform
would do?
5)or any other application/test case you would suggest for IIR filter
implementation on FPGA?
Thanks very much for your help.
Regards,
Kami
Article: 134232
kami wrote:
> I already have the fixed point values for the integers and as they're just
> 5 coefficients, I have just taken them as constants. Do you think it is
> alright?
If I were designing a IIR filter I would start in
the dsp domain and work my way down. See:
http://www.kxcad.net/cae_MATLAB/toolbox/hdlfilter/a1075521372b1.html
I would focus on getting some sample data.
Without expected values for my filter,
what do I have to demonstrate?
> So, I am only giving input from the board and getting the output and not
> using any RAM/ROM or multiplier blocks, I have only used constants and the
> operators ('+', '-', '*') and left it all to the VHDL to do all the
> intermediate arithmetic and use the hardware components as required, will
> it be fine?
+ and - is fine, * will be a problem without using the dsp blocks.
> Do you think it is a good design?
If it works, it will be good.
Keep it simple.
-- Mike Treseler
Article: 134233On Jul 31, 12:26 pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > > I think my main problem with the ?: operator is the same as my problem > with goto statements and implicit type casting. It's not an inherently > problematic device, and can at times be the clearest way of getting the > point across, but it lends itself to abuse. I've certainly seen 10x as > much C code obfuscated by some "clever" use of ?: than I've seen code > clarified by it. > > It's like a driver notification device that warns you you're going over > 70 mph by crescendoing "Ride of the Valkyries". Theoretically it's a > fine tool, but practically it's just begging you floor it for maximum > effect. Nice illustration. But I don't see how it applies??? What construct in VHDL or Verilog can't be misused??? The reason that I prefer the ?: operator is because the resulting use of the conditional assignment or the required IF ELSE THEN construct can be "misused" in that it can obscure the purpose of what you are doing. Can you give a reasonable example of how the ?: operator has been misused in a way that can't be done with other operators? RickArticle: 134234
On Thu, 31 Jul 2008 09:26:10 -0700, Rob Gaddi wrote: > I think my main problem with the ?: operator is the same as my problem > with goto statements and implicit type casting. It's not an inherently > problematic device, and can at times be the clearest way of getting the > point across, but it lends itself to abuse. I've certainly seen 10x as > much C code obfuscated by some "clever" use of ?: than I've seen code > clarified by it. I've only seen the ?: badly used once. It was in C code, coded by a guy who used to have all his C code in one file, and who when designed his FPGAs had loads of clocks everywhere resulting in asynchronous problems. I don't think people like that should be the reason why abusable constructs shouldn't find there way into a language, expecially if there are just a few of them - if there were loads of abusable fetaures then that's different. In a work environment, if you have coding standards and reviews as part of the design process, then problems shouldn't occur. Maybe lint could also help? Most recently, my use of the ?: operator has been when writing some Tcl programs, and I wouldn't want to give it up there. PaulArticle: 134235
On Thu, 31 Jul 2008 11:44:58 -0700, rickman wrote: > Can you give a reasonable example of how the ?: operator has been > misused in a way that can't be done with other operators? They can be chained, it can make a right mess. Do a google search for chained ternary operator. Paul.Article: 134236
On Thu, 31 Jul 2008 20:07:41 +0100, Paul Taylor wrote: > They can be chained, it can make a right mess. Do a google search for > chained ternary operator. >From searching the net, other use of ?: that can cause confusion is when it spans more than one lineArticle: 134237
"kami" <kamran.wadood@yahoo.co.uk> wrote in message news:JJudnS58eI-AdwzV4p2dnAA@giganews.com... ... > Do you think it is a good design? A better question is, do _you_ think it's a good design? > > Now, I was wondering what will be the best option if I wanted to > demonstrate the filter operation more clearly. I mean these are just > numbers that I am showing on the 7-seg display. But if I want to give a > sinusoidal input and get a filtered waveform at the output. It wouldn't take much to drive a VGA display.Article: 134238
Hi,
I am using System Generator 10.1i. The generated code has multiple
times of the following similar code. I am curious about the definition
of:
use work.conv_pkg.all;
use work.clock_pkg.all;
I cannot find it anywhere. Anyone can tell me that?
Thanks in advance.
----------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
use work.clock_pkg.all;
use std.textio.all ;
entity xltbsource is
generic (o_width : integer := 4;
o_bin_pt : integer := 2;
o_arith : integer := xlSigned;
latency : integer := 1;
inputFile : string := "test.dat";
periodMultiplier : integer := 1;
reqHoldTime : time := 1500 ps);
port (o : out std_logic_vector (o_width-1 downto 0));
end xltbsource;
Article: 134239Thank you everybody for your help. Man that eval board looks like a great deal, huh? Either that or I just got ripped off for the Atmega16 uC eval board I just ordered for almost the same price! And none of the peripherals....and they say ebay is a great deal....bah....Article: 134240
On Mon, 28 Jul 2008 14:25:22 GMT, no.spam@gte.net (Scott Gravenhorst)
wrote:
>On Mon, 28 Jul 2008 15:03:05 +0200, Paul Boven <boven@jive.nl> wrote:
>
>>Hi Scott,
>>
>>Scott Gravenhorst wrote:
>>> I have a Spartan-3A DSP 1800A development board which comes with no
>>...
>>> Does anyone know
>>> if Will this cable (Digilent Parallel III) works with this board and
>>> iMPACT or any other Windows based FPGA programmer software?
>>
>>I've 'upgraded' from a Spartan-3 starter kit to the 3A DSP 1800 board a
>>while back. And I'm using the Parallel -> JTAG cable (from Digilent)
>>that came with the first, without trouble. I don't know about Windows,
>>but I'm using IMPACT under Linux and it programs the 1800A fine every time.
>>
>>The cable that I have officially works at 2.8V (and above) whereas the
>>3A DSP 1800 kit runs its JTAG at 2.5V, but this has not been a problem
>>for me. Newer models of the Digilent Parallel cable are specified from
>>1.8V and up ('JTAG3 cable') but I haven't tried those.
>>
>>Given all the hassle with proprietary USB drivers, firmwares etc. I'm
>>staying away from USB based programmers for now.
>>
>>Regards, Paul Boven.
>
>Thank you Paul, that's good information. I looked at the Digilent
>site and I see the JTAG3 cable says 1.8 volts or more as you pointed
>out. At $12.00, it's a no-brainer, it's worth a shot. I just ordered
>it, so when I get it, I will post my own test results here.
>
>-- ScottG
I've received a new Digilent Parallel JTAG3 cable. It does program
the FPGA on this board using iMPACT (I use ISE version 10.1.02, XP
Pro). It takes about 30 seconds.
Article: 134241On Jul 31, 1:47=A0pm, andersod2 <thechrisander...@gmail.com> wrote: > Thank you everybody for your help. =A0Man that eval board looks like a > great deal, huh? =A0Either that or I just got ripped off for the > Atmega16 uC eval board I just ordered for almost the same price! =A0And > none of the peripherals....and they say ebay is a great deal....bah.... Yeah, I bought the S3A board and it's a great deal, even though it lacks fun peripherals like D/A. It also comes with a PSoC programmer.Article: 134242
>"kami" <kamran.wadood@yahoo.co.uk> wrote in message >news:JJudnS58eI-AdwzV4p2dnAA@giganews.com... >... >> Do you think it is a good design? > >A better question is, do _you_ think it's a good design? > >> >> Now, I was wondering what will be the best option if I wanted to >> demonstrate the filter operation more clearly. I mean these are just >> numbers that I am showing on the 7-seg display. But if I want to give a >> sinusoidal input and get a filtered waveform at the output. > >It wouldn't take much to drive a VGA display. > > > Do you mean using a logic analyzer? But my friend is struggling to develop a logic analyzer in FPGA. So, how do you so it won't take much for VGA display? or do you mean using a cable (i've heard of a cable that can be connected to FPGA and then the other end to the PC) is that what you meant? Thanks for your help, Cheers, KamiArticle: 134243
Hi Mike,
Thanks very much for your reply. Please see my answers (and answers with
questions) below:
>If I were designing a IIR filter I would start in
>the dsp domain and work my way down. See:
>http://www.kxcad.net/cae_MATLAB/toolbox/hdlfilter/a1075521372b1.html
Yes, that's exactly what I have done. I think I didn't explain that much
but yes, that's what I've done. Infact, I should say, exactly the same
process as described in the link you've posted. I developed a SIMULINK
model and performed analysis. Then quantized the filter to make it
fixed-point and then generated HDL code and test-bench. But then I only
used the generated HDL code of filter and wrote another VHDL code for
testing it on FPGA and got the results as mentioned in my last post. So,
the logic for the filter is basically from the HDL code generated by MATLAB
FDA tool.
>I would focus on getting some sample data.
>Without expected values for my filter,
>what do I have to demonstrate?
Sorry, I couldn't quite get your point, do you mean the input that I am
giving? But it's being assigned through the buttons and switches which can
be changed. Or do you mean giving a real-time signal input? like speech or
any anlaogue input?
>+ and - is fine, * will be a problem without using the dsp blocks.
Well, not really I think, because I could see in the synthesis report that
3 MULT_18x18 blocks {Multiplier blocks} are being used. So, that means the
code is invoking those blocks by itself. I mean the '*' operator is doing
the bit.
>> Do you think it is a good design?
>
>If it works, it will be good.
>Keep it simple.
Well as I have mentioned earlier on that it's giving the 16-bit binary
output that I could show on the 7-segment display in hexadecimal format, I
can say it sounds good. But I want to make it look like an IIR filter. I
mean the algorithm is working (at least, I think so) now, it's just the
front end which can make it speak that I am an IIR filter. Any
suggestions/comments please?
Thanks very much for your time and help,
Much Appreciated,
Kami
Article: 134244Although the board lacks a lot of peripherals, it does have two Digilent-compatible 6-pin peripheral module headers. http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=Peripheral Xilinx created a bundle of 8 of these for their CR2 kit, but that bundle is also compatible with the Avnet Spartan-3A Eval Kit. http://www.xilinx.com/products/devkits/HW-CRII-PM-ACC-G.htm BryanArticle: 134245
Hi, in many times when I program Xilixn FPGA with parallel cable, I always get message "program failed". In some case I populated several capacitors to the pins of download cable and it works. But many times I still failed. Did anybody here met this problem? Is there any comments on this?Article: 134246
On Jul 31, 3:40 pm, Paul Taylor <pt@false_email.co.uk> wrote: > On Thu, 31 Jul 2008 20:07:41 +0100, Paul Taylor wrote: > > They can be chained, it can make a right mess. Do a google search for > > chained ternary operator. > > From searching the net, other use of ?: that can cause confusion is when it > spans more than one line I can't say that I give either of these examples much importance. Both examples of poor usage can create messes of logic no matter what operator is being used. This just seems to me to be a specious argument. a <= alongvariablename or blongvariablename and clongvariablename xor dlongvariablename and elongvariablename or flongvariablename; RickArticle: 134247
On Aug 1, 1:09 am, skyworld <chenyong20...@gmail.com> wrote: > Hi, > > in many times when I program Xilixn FPGA with parallel cable, I always > get message "program failed". In some case I populated several > capacitors to the pins of download cable and it works. But many times > I still failed. Did anybody here met this problem? Is there any > comments on this? This is not that unusual. You don't mention which cable, but there is generally more problems when the cable has long flying leads like the Parallel Cable III, especially with newer parts (Spartan 3, Virtex 4 and newer). There are notes in the configuration user guides for newer parts suggesting parallel termination on the CCLK lines (slave serial mode) and it seems that something is also required on the TCK pin to avoid extra clocks from signal reflections in long cables. These effects are noticeably less with shorter cables like the Platform Cable USB when using the 2mm ribbon cable. Regards, GaborArticle: 134248
hi all; I am using Edk to create IP peripheral which contains RD and WR Fifos. My question is, if the required data to be written to the read fifo is undefined it will not be stored in the fifo or what. fatmaArticle: 134249
"fmostafa" <fatma.abouelella@ugent.be> wrote in message news:7dd39237-2837-4722-b062-6a849321cfef@k37g2000hsf.googlegroups.com... > hi all; > > I am using Edk to create IP peripheral which contains RD and WR > Fifos. My question is, if the required data to be written to the read > fifo is undefined it will not be stored in the fifo or what. > > fatma If you write undefined data to a fifo .. that's what will be stored in the fifo .. undefined data. If you don't want this to be stored ... don't assert the fifo push signal. Mike
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z