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On Aug 17, 3:43=A0am, "vincese...@gmail.com" <vincese...@gmail.com> wrote: > Hi all, > > I am new to multicore platforms on FPGA's. I was wondering if there is > some good information somewhere on the net where I can read on > building multicore systems and installing an OS on an FPGA target > board for this multicore system (Digilent Virtex II-Pro,...). (I am > looking for theoretical and practical tutorials like in EDK,...) > > The multicore system I would like to build is around microblaze or > PowerPC cores but other references are good. > > Kind regards and thanks for your help. > > Vince Serti The MicroBlaze and PowerPC do not support cache coherency. Neither do most other CPUs that you can use inside an FPGA. The exception that I am aware of is the OpenSPARC T1. See here for more information on that running on an FPGA: http://www.opensparc.net/fpga/index.html The issue with not supporting cache coherency means that it is difficult to support a single system image OS that will schedule all of the CPUs. There was the openMosix project that would combine multiple systems into a single system image, but it has been discontinued. It was also only for x86 systems. For more information, see here: http://en.wikipedia.org/wiki/OpenMosix Since the available CPUs that are a good match for implementing with FPGAs do not have coherent caches, you will be more interested in message passing systems. I believe that Dr. John Williams has built some multi-processor systems that used MPI to communicate between the different CPUs, but I don't remember where I heard or read that. You can get more information about what he is doing at: http://www.petalogix.co= m/ Regards, John McCaskill www.FasterTechnology.comArticle: 134576
austin <austin@xilinx.com> wrote: >As many of you are aware, > >Xilinx has had a re-organization to provide focus, and better serve >our customers. My role has changed, and as part of that change, I no >longer will be posting here on c.a.f. I'm sorry to see you go. I'd like to thank you for your 'input' in this newsgroup and wish you good luck with your new job (assignment?). Just try to remind the guys at X that people like it when a company official posts here every now and then. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 134577
Il 19/08/2008 2.15, rickman ha scritto: > I want to run some simulations where I change one controlling > parameter that selects the specifics of the test bench. Is there a > way to do that without recompiling the source code? It seems like With ModelSim you can use the "force" statement to force a wire to a value. So in the design module I do: parameter DELAY_TOO_LONG_FOR_SIMULATIONS = 1000; // myDelay wires are constant in the design, no penalty wire [15:0] myDelay = DELAY_TOO_LONG_FOR_SIMULATIONS; ... if(rst) cnt <= myDelay; .... In my testbench: force uut.myDelay = 10; I'm sure there are better ways...Article: 134578
Il 19/08/2008 2.15, rickman ha scritto: > I want to run some simulations where I change one controlling > parameter that selects the specifics of the test bench. Is there a Oops! Sorry rick, just realized I misunderstood your question! And I can't even help on that, I don't know Aldec ActiveHDL.Article: 134579
"Antonio Pasini" <removethis_antonio.pasini@alice.it> wrote in message news:48AAF5B2.7060508@alice.it... > > And I can't even help on that, I don't know Aldec ActiveHDL. > Antonio, Too late, you already helped. It's called 'force' in ActiveHDL as well. :-) Cheers, Syms.Article: 134580
Hi everyone,
I'm pretty new in the FPGA and embedded area, and I'm working in an
application using the Xilinx ML403 board, and the Xilinx tools ISE and
EDK 10.1. I have some questions about that.
-Is it possible to get the calendar time from the PPC? I need to
generate a time stamp, and I was trying to use the standard c library
<time.h>. I'm using the standard approach like
time_t now;
struct tm *ts;
char buf[80];
time(&now);
ts = localtime(&now);
strftime(buf, sizeof(buf), "%a %Y-%m-%d %H:%M:%S %Z", ts);
xil_printf("%s\n", buf);
but I got an error saying that the function "time" is not defined.
However, the other functions (localtime and strftime) works OK. Is the
function "time" implemented in EDK? Do you know any other way to do
the same?
- I'm using the library <sysace_stadio.h> for writing data in a CF
memory. Basically, I'm capturing data from a ethernet connection and
saving it in a file.
To make sure that the file won't be corrupted if something happen to
the board, I'm closing the file after every write. However, the
problem is if I open the file to write again I lost the previous data.
Is there any way to append data to an existing file, or maybe to avoid
corruption in an open file forcing an inmediate write without using
the buffer?
Thanks a lot in advance.
Best Regards.
Article: 134581On Aug 19, 1:16 pm, "Symon" <symon_bre...@hotmail.com> wrote: > "Antonio Pasini" <removethis_antonio.pas...@alice.it> wrote in message > > news:48AAF5B2.7060508@alice.it... > > > And I can't even help on that, I don't know Aldec ActiveHDL. > > Antonio, > Too late, you already helped. It's called 'force' in ActiveHDL as well. :-) > Cheers, Syms. Thanks for the info. I guess I can try that. I was thinking more of a generic property sort of thing. But I guess it doesn't matter how I do it. I'll give this a try. Will the force be overwritten the next time the signal is driven by the model? I guess that is a parameter on the Force statement. Now that I know a name, I can check in the help files. Thanks, RickArticle: 134582
Hi all, To celebrate the Beijing Olympics we are doing our Personal Bests with the prices of the BurchED FPGA Videos. If you have not yet purchased the videos and you wanted to get started with FPGAs, then Olympic time is the best time! While the Olympics are still running, for this limited time you can get the FPGA videos for half-price. There are now 19 videos in the course, including our just added video: How to do a Xilinx ISE Verilog Project. Please have a look at our Olympics Celebration Offer at http://www.burched.com If you are a university or tech college lecturer, we have an Olympic Celebration Special on our University Site License. You can turn your students into FPGA champions for only 99 cents each during this Olympic sale! Please have a look at our 99 cents Olympics Celebration offer at http://www.burched.com/universities.ag.php * Site licenses are for 100 students Happy Olympics to all, and kind regards, Tony Burch Burch Electronic Designs PO Box 1548, Macquarie Centre, North Ryde, NSW, 2113, AustraliaArticle: 134583
"Tony Burch" <tony@burched.com.au> wrote in message news:48ab48fb$0$28216$afc38c87@news.optusnet.com.au... > Hi all, > > To celebrate the Beijing Olympics we are doing our Personal Bests with the > prices of the BurchED FPGA Videos. > > If you have not yet purchased the videos and you wanted to get started > with FPGAs, then Olympic time is the best time! While the Olympics are > still running, for this limited time you can get the FPGA videos for > half-price. > > There are now 19 videos in the course, including our just added video: How > to do a Xilinx ISE Verilog Project. > > Please have a look at our Olympics Celebration Offer at > http://www.burched.com > > If you are a university or tech college lecturer, we have an Olympic > Celebration Special on our University Site License. You can turn your > students into FPGA champions for only 99 cents each during this Olympic > sale! > > Please have a look at our 99 cents Olympics Celebration offer at > http://www.burched.com/universities.ag.php > * Site licenses are for 100 students > > Happy Olympics to all, and kind regards, > > Tony Burch > > Burch Electronic Designs > PO Box 1548, Macquarie Centre, North Ryde, NSW, 2113, Australia > Hi again, I just found out that our friend Clive "Max" Maxfield at Programmable Logic Design Line has posted a great blog entry about our Olympic Sale. Read it here http://www.pldesignline.com/blogs/210101879 Thanks Max! Kind regards, Tony BurchArticle: 134584
On Aug 19, 4:03 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Tue, 19 Aug 2008 10:15:50 +0100, Jonathan Bromley wrote:
> >ISE 8.2 (yeah, I know it's ancient, but I haven't got
> >around to installing anything newer yet) just locked-up
> >with 100% CPU usage, presumably because it failed to
> >infer theRAMfrom my description and was trying to
> >build a gazillion registers instead. Must go look up
> >the correct inference templates for XST :-)
>
> Ahah! Got it...
>
> XST User Guide is a bit woolly about VerilogRAMinference. It turns out that this form is OK:
>
> always @(posedge clock)
> if (enable) begin
> if (write) begin
> mem[address] <= write_data;
> read_data <= write_data ;
> end else begin
> read_data <= mem[address];
> end
> end
>
> but this form is not - it hangs XST:
>
> always @(posedge clock)
> if (enable) begin
> if (write) begin
> mem[address] = write_data;
> end
> read_data <= mem[address];
> end
>
> Despite what it says in the XST user guide, it seems
> that the same story applies in VHDL: the memory store
> must be a signal.
>
I've found the XST user guide pretty helpful for these templates.
However,
beware some nasty potholes.
XST can get confused with the enables to the RAMS. Don't have the
docs in front of me right now - but I believe the BRAMs have seperate
read/write enables - as opposed to a global "enable" and seperate
read/write strobe or similar. XST could build enable logic different
than your description. For one of my cases, the way I had the
enables couldn't actually be mapped to a BRAM. Problem on my part -
however
XST happily went and built something anyway - which was incorrect.
i.e. didn't match the description, and didn't throw any
error/warning. Just happily tied the enables is some wrong fashion.
I've also had issues with getting XST to infer the"read first/write
first" attribute
correctly. This one really bit me once - 3, or 4 days of lab debug to
figure out
XST had inferred "write first", when the description was
read first.
Other than that - the RAM inferrence in XST seems to work.
For the two write port RAMS, what I've got is the memory
being written two in two seperate procedural blocks (normally a no-
no):
i.e.
always @( posedge clk1)
if( wren1 )
mem[ addr1 ] <= data1;
...
always @( posedge clk2)
if( wren2 )
mem[ addr2 ] <= data2;
...
Although I confess, I haven't used this one in XST yet, just sims.
Regards,
Mark
Article: 134585On Aug 19, 5:27=A0pm, "gtw...@pacbell.net" <gtw...@pacbell.net> wrote: > On Aug 19, 4:03 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > wrote: > > > > > On Tue, 19 Aug 2008 10:15:50 +0100, Jonathan Bromley wrote: > > >ISE 8.2 (yeah, I know it's ancient, but I haven't got > > >around to installing anything newer yet) just locked-up > > >with 100% CPU usage, presumably because it failed to > > >infer theRAMfrom my description and was trying to > > >build a gazillion registers instead. =A0Must go look up > > >the correct inference templates for XST :-) > > > Ahah! Got it... > > > XST User Guide is a bit woolly about VerilogRAMinference. It turns out = that this form is OK: > > > =A0 always @(posedge clock) > > =A0 =A0 if (enable) begin > > =A0 =A0 =A0 if (write) begin > > =A0 =A0 =A0 =A0 mem[address] <=3D write_data; > > =A0 =A0 =A0 =A0 read_data <=3D write_data ; > > =A0 =A0 =A0 end else begin > > =A0 =A0 =A0 =A0 read_data <=3D mem[address]; > > =A0 =A0 =A0 end > > =A0 =A0 end > > > but this form is not - it hangs XST: > > > =A0 always @(posedge clock) > > =A0 =A0 if (enable) begin > > =A0 =A0 =A0 if (write) begin > > =A0 =A0 =A0 =A0 mem[address] =3D write_data; > > =A0 =A0 =A0 end > > =A0 =A0 =A0 read_data <=3D mem[address]; > > =A0 =A0 end > > > Despite what it says in the XST user guide, it seems > > that the same story applies in VHDL: the memory store > > must be a signal. > > I've found the XST user guide pretty helpful for these templates. > However, > beware some nasty potholes. > > XST can get confused with the enables to the RAMS. =A0Don't have the > docs in front of me right now - but I believe the BRAMs have seperate > read/write enables - as opposed to a global "enable" and seperate > read/write strobe or similar. =A0XST could build enable logic different > than your description. =A0For one of my cases, the way I had the > enables couldn't actually be mapped to a BRAM. Problem on my part - > however > XST happily went and built something anyway - which was incorrect. > i.e. didn't match the description, and didn't throw any > error/warning. =A0Just happily tied the enables is some wrong fashion. > > I've also had issues with getting XST to infer the"read first/write > first" attribute > correctly. =A0This one really bit me once - 3, or 4 days of lab debug to > figure out > XST had inferred "write first", when the description was > read first. > > Other than that - the RAM inferrence in XST seems to work. > > For the two write port RAMS, what I've got is the memory > being written two in two seperate procedural blocks (normally a no- > no): > i.e. > > always @( posedge clk1) > =A0 if( wren1 ) > =A0 =A0 mem[ addr1 ] <=3D data1; > =A0 =A0... > > always @( posedge clk2) > =A0 if( wren2 ) > =A0 =A0 mem[ addr2 ] <=3D data2; > =A0 =A0... > > Although I confess, I haven't used this one in XST yet, just sims. > > Regards, > > Mark Regarding Enables: All Xilinx BlockRAMs have a Clock Enable input that, if inactive, stops all writing and reading. There is also a Read/Write input that selects between reading and writing. That means, there is no explicit overriding "write enable" or "read enable" or "write strobe" or "read strobe". You can always do what you want to get done by following the rules (except you cannot read or write without a clock). Peter AlfkeArticle: 134586
rickman wrote: > > I was thinking more of a generic property sort of thing. > I've seen command line generic overrides in several tools: VHDL Simili manual: " -gName=Value " Using this option, you can override values for generics " for the top-level architecture/entity. XST manual: " Generics (-generics) allows you to to redefine generics (VHDL) or " parameters (Verilog) values defined in the top-level design block. <snip> " Define Generics globally in Project Navigator > Process Properties > " Synthesis Options > Generics, Parameters. A search on 'active hdl generic override' turned up: -G<generic_name=value> Design Settings->General->Simulation Parameters->Generic/Parameters http://support.aldec.com/KnowledgeBase/Article.aspx?aid=000705&show=Dia00007.htm BrianArticle: 134587
Nial Stewart wrote: >> Hi, >> How does the vertical migration, using different parts with the same package work with the altera >> cyclone 3 devices? For the EP3C40 and >> EP3C16 parts in the FBGA464 packages, pin D7 is gnd on the 16K part, >> and D7 is diffio on the 40K part. Also some gnd pins on the 40K part >> are I/O on the 16K part. So to design a PCB that can work with both of >> these parts alot of extra I/O will have to be grounded I guess? >> cheers, >> Jamie > > Jamie, > > Be careful here the documentation's not that clear, you could easily get > your fingers burnt with this migration. > > We discovered that the vref's change position between the different > devices that are supposed to be 'easily' migrate-able. It took a > big spreadsheet cross-referencing the three parts (we wanted to > be able to use the '55 too) to get a pinout that was compatable. Hi, You wouldn't happen to still have that spreadsheet would you? :) I went through the pin differences between the EP3C40 and EP3C16 parts in the FBGA484 package, and verified there are 22 I/O in the EP3C16 that can't be used in a EP3C40 compatible layout, and also there are 7 I/O in the EP3C40 that can't be used in a EP3C16 compatible layout, so the end result is a layout with 7 fewer I/O than the EP3C40 has in order to make it work with both parts. I didn't notice any vref's changing positions between these two parts, but you got me scared now ;) The 7 I/O on the EP3C40 that can't be used in a EP3C16 compatible layout are package balls: D7 H8 J5 J8 T13 U16 U17 The 22 I/O on the EP3C16 that can't be used in a EP3C40 compatible layout are package balls: F12 G12 H12 H13 H9 J15 J16 K15 K16 L15 L16 M15 N14 N15 P14 P8 R10 R11 R12 R13 R8 R9 so those 22+7 pins can be grounded or tied to VCC, and then that layout will work with both the parts, but a layout optimized only for the EP3C16 would have 29 more available I/O's. (346 instead of 317) Any verification of my results would be nice to hear, it is my first FPGA layout and first real BGA PCB at the same time! cheers, Jamie > > > > Nial. > >Article: 134588
On Aug 19, 11:12=A0pm, Jamie Morken <jmor...@shaw.ca> wrote: > Nial Stewart wrote: > >> Hi, > >> How does the vertical migration, using different parts with the same p= ackage work with the altera > >> cyclone 3 devices? =A0For the EP3C40 and > >> EP3C16 parts in the FBGA464 packages, pin D7 is gnd on the 16K part, > >> and D7 is diffio on the 40K part. =A0Also some gnd pins on the 40K par= t > >> are I/O on the 16K part. =A0So to design a PCB that can work with both= of > >> these parts alot of extra I/O will have to be grounded I guess? > >> cheers, > >> Jamie > > > Jamie, > > > Be careful here the documentation's not that clear, you could easily ge= t > > your fingers burnt with this migration. > > > We discovered that the vref's change position between the different > > devices that are supposed to be 'easily' migrate-able. It took a > > big spreadsheet cross-referencing the three parts (we wanted to > > be able to use the '55 too) to get a pinout that was compatable. > > Hi, > > You wouldn't happen to still have that spreadsheet would you? :) > > I went through the pin differences between the EP3C40 and EP3C16 parts > in the FBGA484 package, and verified there are 22 I/O in the EP3C16 that > can't be used in a EP3C40 compatible layout, and also there are 7 I/O in > the EP3C40 that can't be used in a EP3C16 compatible layout, so the end > result is a layout with 7 fewer I/O than the EP3C40 has in order to make > it work with both parts. =A0I didn't notice any vref's changing positions > between these two parts, but you got me scared now ;) > > The 7 I/O on the EP3C40 that can't be used in a EP3C16 compatible layout > are package balls: > D7 > H8 > J5 > J8 > T13 > U16 > U17 > > The 22 I/O on the EP3C16 that can't be used in a EP3C40 compatible > layout are package balls: > F12 > G12 > H12 > H13 > H9 > J15 > J16 > K15 > K16 > L15 > L16 > M15 > N14 > N15 > P14 > P8 > R10 > R11 > R12 > R13 > R8 > R9 > > so those 22+7 pins can be grounded or tied to VCC, and then that layout > will work with both the parts, but a layout optimized only for the > EP3C16 would have 29 more available I/O's. (346 instead of 317) > > Any verification of my results would be nice to hear, it is my first > FPGA layout and first real BGA PCB at the same time! > > cheers, > Jamie > > > > > > > Nial.- Hide quoted text - > > - Show quoted text -- Hide quoted text - > > - Show quoted text - Hi Jamie, use the Pin Migration View in the Pin Planner. The instructions are available at http://www.altera.com/literature/hb/qts/qts_q= ii52013.pdf Pg 38-40. Hope this helps, Subroto Datta Altera Corp.Article: 134589
On Aug 19, 10:22 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Tue, 19 Aug 2008 06:20:51 -0700 (PDT), rickman wrote:
>
> > always @(posedge clock)
> > if (enable1) begin
> > if (write1) begin
> > mem[address1] <= write_data1;
> > read_data1 <= write_data1 ;
> > end else begin
> > read_data1 <= mem[address1];
> > end
> > end
> > if (enable2) begin
> > if (write2) begin
> > mem[address2] <= write_data2;
> > read_data2 <= write_data2 ;
> > end else begin
> > read_data2 <= mem[address2];
> > end
> > end
>
> >How about this as a dual port memory?
>
> It's a fine model, but I can't find a synth tool that
> will infer DP memory when both ports can write.
>
> If only one of the two ports has write, it's OK.
I used the Synplify tool that came with the Lattice package and got
this message from the code below.
--------------------------------------------------------------------------------
Found multi-write port RAM mem, number of write ports=2, depth=128,
width=18
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
library xp;
use xp.components.all;
Library Common;
Use Common.Stuff.all;
Use Common.conversions.all;
Library Hardware;
Use Hardware.IRIG_Defs.all;
entity RAM_TEST is
port (
SysClk : in std_logic;
enable1 : in std_logic;
write1 : in std_logic;
address1 : in std_logic_vector (6 downto 0);
write_data1 : in std_logic_vector (17 downto 0);
read_data1 : out std_logic_vector (17 downto 0);
enable2 : in std_logic;
write2 : in std_logic;
address2 : in std_logic_vector (6 downto 0);
write_data2 : in std_logic_vector (17 downto 0);
read_data2 : out std_logic_vector (17 downto 0)
);
end RAM_TEST;
architecture RTL of RAM_TEST is
subtype RAM_Word is std_logic_vector (17 downto 0);
type RAM is array (127 downto 0) of RAM_Word;
signal mem : RAM;
begin
Mem: process (SysClk) begin
if (rising_edge(SysClk)) then
if (enable1 = '1') then
if (write1 = '1') then
mem(to_int(address1)) <= write_data1;
read_data1 <= write_data1 ;
else
read_data1 <= mem(to_int(address1));
end if;
end if; -- enable1
if (enable2 = '1') then
if (write2 = '1') then
mem(to_int(address2)) <= write_data2;
read_data2 <= write_data2 ;
else
read_data2 <= mem(to_int(address2));
end if;
end if; -- enable2
end if; -- rising_edge(SysClk
end process Mem;
end RTL;
Does this work for the Xilinx and Altera versions of the Synplify
tool?
Rick
Article: 134590On Aug 20, 2:45=A0am, rickman <gnu...@gmail.com> wrote: > On Aug 19, 10:22 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > Does this work for the Xilinx and Altera versions of the Synplify > tool? > > Rick- Hide quoted text - > Quartus didn't like it when targetting a Cyclone II device, it got implemented with logic cells. When it sees the second path in the code for writing to memory (i.e. enable2 and write2) it can't map it into the internal memory of the device. KJArticle: 134591
O.K. Big announcement, lots of marketing buzz, etc. Now without looking it up at the Xilinx website, i.e. using only the press release, what end of the line was extended? Was anything actually added or is this just a marketing gimmick? Are there new parts or did they just put three series (3A, 3AN, 3A DSP) into one datasheet? And where is Spartan 4? Eagerly awaiting much needed clarification, Gabor :)Article: 134592
Looks like a hiding away of S3/S3E families and the S3A-DSP now in same datasheet as mainline S3A. John Adair Enterpoint Ltd. On Aug 20, 1:27=A0pm, Gabor <ga...@alacron.com> wrote: > O.K. =A0Big announcement, lots of marketing buzz, etc. > > Now without looking it up at the Xilinx website, i.e. using > only the press release, what end of the line was extended? > > Was anything actually added or is this just a marketing > gimmick? =A0Are there new parts or did they just put > three series (3A, 3AN, 3A DSP) into one datasheet? > > And where is Spartan 4? > > Eagerly awaiting much needed clarification, > > Gabor > > :)Article: 134593
On Aug 20, 7:50 am, KJ <kkjenni...@sbcglobal.net> wrote: > On Aug 20, 2:45 am, rickman <gnu...@gmail.com> wrote: > > > On Aug 19, 10:22 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > > Does this work for the Xilinx and Altera versions of the Synplify > > tool? > > > Rick- Hide quoted text - > > Quartus didn't like it when targetting a Cyclone II device, it got > implemented with logic cells. When it sees the second path in the > code for writing to memory (i.e. enable2 and write2) it can't map it > into the internal memory of the device. What is the synthesis tool that Quartus uses? I don't recall that Altera has written their own. Instead I want to say that Altera uses one of the commercial tools for synthesis. RickArticle: 134594
On Wed, 20 Aug 2008 06:41:29 -0700 (PDT), rickman wrote: >What is the synthesis tool that Quartus uses? I don't recall that >Altera has written their own. Instead I want to say that Altera uses >one of the commercial tools for synthesis. Quartus can use third-party synthesis tools, but has its own synthesis engine. AFAIK its front-end is from Verific. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 134595
On Aug 19, 3:08=A0pm, gcarvaj...@gmail.com wrote:
> Hi everyone,
>
> I'm pretty new in the FPGA and embedded area, and I'm working in an
> application using the Xilinx ML403 board, and the Xilinx tools ISE and
> EDK 10.1. I have some questions about that.
>
> -Is it possible to get the calendar time from the PPC? I need to
> generate a time stamp, and I was trying to use the standard c library
> <time.h>. I'm using the standard approach like
There is no way to get the "real calendar" time from PPC unless you
implemented some logic to handle it yourself. The only time base that
the PPC405 has natively is a its TBR: Time Base Register. This is a
64bit counter that is nothing more than a CPU tick counter that is
updated every clock cycle.
You can create your own fake time implementation by reading the TBR.
Here's an example of how to read it:
unsigned long long read_tbr(void)
{
unsigned long tbr_low;
unsigned long tbr_high;
unsigned long tbr_high_old;
unsigned long long tbr;
do {
asm volatile( "mftbu %0" : "=3Dr" (tbr_high_old));
asm volatile( "mftb %0" : "=3Dr" (tbr_low));
asm volatile( "mftbu %0" : "=3Dr" (tbr_high));
} while ( tbr_high_old !=3D tbr_high );
tbr =3D tbr_high;
tbr <<=3D 32;
tbr |=3D tbr_low;
return tbr;
}
> time_t now;
> struct tm =A0*ts;
> char =A0 =A0 =A0 buf[80];
>
> time(&now);
> ts =3D localtime(&now);
> strftime(buf, sizeof(buf), "%a %Y-%m-%d %H:%M:%S %Z", ts);
> xil_printf("%s\n", buf);
>
> but I got an error saying that the function "time" is not defined.
> However, the other functions (localtime and strftime) works OK. Is the
> function "time" implemented in EDK? Do you know any other way to do
> the same?
>
> - I'm using the library <sysace_stadio.h> for writing data in a CF
> memory. Basically, I'm capturing data from a ethernet connection and
> saving it in a file.
>
> To make sure that the file won't be corrupted if something happen to
> the board, I'm closing the file after every write. However, the
> problem is if I open the file to write again I lost the previous data.
>
> Is there any way to append data to an existing file, or maybe to avoid
> corruption in an open file forcing an inmediate write without using
> the buffer?
Unfortunately, I'm not aware anything directly from the xilfatfs
library. And in fact we ran into a similar problem for our system,
where we needed to read around the contents of a file with random I/O.
To do this, we added our own sysace_seek() function that performed
this capability. It needs to be updated to support what an append
capability (and I'll be working on that in the very near future, since
I need it as well).
int sysace_seek(int count, SYSACE_FILE *stream)
{
FileStatus *fs =3D find_file_status(stream);
int readcount, n;
int remaining;
UINT32 sector;
UINT32 filesize;
UINT32 nsectors;
UINT32 sector_offset;
int byte_offset;
/* Safety check */
if (fs =3D=3D 0 || !fs->read || count < 0)
return 0;
filesize =3D fs->wd->v.child.FileSize;
if (fs->PositionInFile >=3D filesize)
return 0;
readcount =3D 0;
/* Compute number of bytes left to read - may be limited
* by size of users buf or by file size */
remaining =3D filesize - fs->PositionInFile;
if (count < remaining)
remaining =3D count;
while (fs->PositionInFile < filesize) {
/* Which sector of this cluster did we leave off at last time ? */
sector_offset =3D fs->PositionInCluster / SECTORSIZE;
/* Which byte of that sector did we leave off at last time ? */
byte_offset =3D fs->PositionInCluster % SECTORSIZE;
/* Sector address to start reading this time */
sector =3D starting_sector(fs->CurrentCluster, fs->wd->pi);
if (sector =3D=3D 0) {
/* FAT problem ? */
return 0;
}
sector +=3D sector_offset;
/* How many sectors left to read in this cluster */
nsectors =3D fs->wd->pi->SectorsPerCluster - sector_offset;
while (nsectors) {
if (remaining <=3D (SECTORSIZE - byte_offset)) {
/* End of file or end of buffer occurs in this sector
* Read what's left and quit */
fs->PositionInFile +=3D remaining;
fs->PositionInCluster +=3D remaining;
return (remaining + readcount);
}
/* End of file is beyond this sector */
n =3D SECTORSIZE - byte_offset;
fs->PositionInFile +=3D n;
fs->PositionInCluster +=3D n;
readcount +=3D n;
remaining -=3D n;
/* Point to start of next sector in cluster */
byte_offset =3D 0;
sector +=3D 1;
nsectors -=3D 1;
} /* end of while */
/* Done with that cluster, advance to the next one */
fs->CurrentCluster =3D next_cluster(fs->CurrentCluster, fs->wd->pi);
if (fs->CurrentCluster =3D=3D BAD_CLUSTER) {
/* Bad cluster address - this means that there is a FAT problem,
* because we should have dtected that this was the last cluster
* based on filesize. The file system is hosed. */
return 0;
}
/* We are at the start of this new cluster */
fs->PositionInCluster =3D 0;
}
return readcount;
}
HTH,
-- Mike
Article: 134596I'm looking for an efficient multichannel narrowband digital down converter core for my virtex-4 design. I need a rate change of about 256 to 28000. Seems the rf engines IP is overkill and the XIlinx stock IP is not efficient (no serialized comb in CIC, for example). I need independent tuning and bandwidth. I have a similar requirement for 2 channel DDC where each ddc is exactly the same tuning and bandwidth. Any leads on IP sources/vendors, is appreciated. Thanks, ClarkArticle: 134597
On Aug 20, 5:27=A0am, Gabor <ga...@alacron.com> wrote: > O.K. =A0Big announcement, lots of marketing buzz, etc. > > Now without looking it up at the Xilinx website, i.e. using > only the press release, what end of the line was extended? > > Was anything actually added or is this just a marketing > gimmick? =A0Are there new parts or did they just put > three series (3A, 3AN, 3A DSP) into one datasheet? > "Marketing gimmick" is a harsh word. Is a hair-cut a marketing gimmick, an image enhancement or a sales tool ? This is a re-positioning of a product line that had grown and become difficult to understand, for the sales force as well as for the customers. The messages had become cluttered and hard to untangle, explain and understand. Now it is easy to see what these parts are, and what they are good for, and especially what they cost, for low cost is the name of the game in this part of our industry. Regarding the next generation: It will come in due course. I am working on it every day. 'nough said... Peter AlfkeArticle: 134598
On Aug 20, 11:53 am, cep...@nc.rr.com wrote: > I'm looking for an efficient multichannel narrowband digital down > converter core for my virtex-4 design. I need a rate change of about > 256 to 28000. Seems the rf engines IP is overkill and the XIlinx stock > IP is not efficient (no serialized comb in CIC, for example). I need > independent tuning and bandwidth. Have you considered writing your own? It is not all that complicated, and you get the opportunity to tune it to your exact needs and resource budget. I wonder if a serializing the parts of the CIC that run at the decimated rate is worth the trouble. It doesn't seem like it would be very hard to do though - use something akin to an M512 (sorry, wrong vendor language) and do the math one bit at a time - or if you don't have enough clocks in between output rate samples, 2 or 4 bits at a time.Article: 134599
Thanks a lot for your directions. They are very useful.
Yeps. This is my first embedded application and I was assuming that
the PPC had a realtime clock with the calendar time. It's a little
complicated to get used to the new limitations when you have been
programming just in a desktop machine :). Now that I know the
limitation I can start to think in another way. But what called my
attention is why the other functions of the library for manipulate the
time are available for the architecture if you are not able to get the
time.
Thanks for the info and the function for xilfatfs. My temporal
solution was managing various temporal files and one master, but is a
really messy solution and not optimal at all, because the incoming
data is arriving very fast, and even I'm not sure if it's working. I
will check your option, a function similar to feof() is exactly was I
looking for.
Thank you very much and good luck.
On Aug 20, 11:22 am, morphiend <morphi...@gmail.com> wrote:
> On Aug 19, 3:08 pm, gcarvaj...@gmail.com wrote:
>
> > Hi everyone,
>
> > I'm pretty new in the FPGA and embedded area, and I'm working in an
> > application using the Xilinx ML403 board, and the Xilinx tools ISE and
> > EDK 10.1. I have some questions about that.
>
> > -Is it possible to get the calendar time from the PPC? I need to
> > generate a time stamp, and I was trying to use the standard c library
> > <time.h>. I'm using the standard approach like
>
> There is no way to get the "real calendar" time from PPC unless you
> implemented some logic to handle it yourself. The only time base that
> the PPC405 has natively is a its TBR: Time Base Register. This is a
> 64bit counter that is nothing more than a CPU tick counter that is
> updated every clock cycle.
>
> You can create your own fake time implementation by reading the TBR.
> Here's an example of how to read it:
>
> unsigned long long read_tbr(void)
> {
> unsigned long tbr_low;
> unsigned long tbr_high;
> unsigned long tbr_high_old;
> unsigned long long tbr;
>
> do {
> asm volatile( "mftbu %0" : "=r" (tbr_high_old));
> asm volatile( "mftb %0" : "=r" (tbr_low));
> asm volatile( "mftbu %0" : "=r" (tbr_high));
> } while ( tbr_high_old != tbr_high );
>
> tbr = tbr_high;
> tbr <<= 32;
> tbr |= tbr_low;
> return tbr;
>
>
>
> }
> > time_t now;
> > struct tm *ts;
> > char buf[80];
>
> > time(&now);
> > ts = localtime(&now);
> > strftime(buf, sizeof(buf), "%a %Y-%m-%d %H:%M:%S %Z", ts);
> > xil_printf("%s\n", buf);
>
> > but I got an error saying that the function "time" is not defined.
> > However, the other functions (localtime and strftime) works OK. Is the
> > function "time" implemented in EDK? Do you know any other way to do
> > the same?
>
> > - I'm using the library <sysace_stadio.h> for writing data in a CF
> > memory. Basically, I'm capturing data from a ethernet connection and
> > saving it in a file.
>
> > To make sure that the file won't be corrupted if something happen to
> > the board, I'm closing the file after every write. However, the
> > problem is if I open the file to write again I lost the previous data.
>
> > Is there any way to append data to an existing file, or maybe to avoid
> > corruption in an open file forcing an inmediate write without using
> > the buffer?
>
> Unfortunately, I'm not aware anything directly from the xilfatfs
> library. And in fact we ran into a similar problem for our system,
> where we needed to read around the contents of a file with random I/O.
> To do this, we added our own sysace_seek() function that performed
> this capability. It needs to be updated to support what an append
> capability (and I'll be working on that in the very near future, since
> I need it as well).
>
> int sysace_seek(int count, SYSACE_FILE *stream)
> {
> FileStatus *fs = find_file_status(stream);
>
> int readcount, n;
> int remaining;
> UINT32 sector;
> UINT32 filesize;
> UINT32 nsectors;
> UINT32 sector_offset;
> int byte_offset;
>
> /* Safety check */
> if (fs == 0 || !fs->read || count < 0)
> return 0;
>
> filesize = fs->wd->v.child.FileSize;
>
> if (fs->PositionInFile >= filesize)
> return 0;
>
> readcount = 0;
>
> /* Compute number of bytes left to read - may be limited
> * by size of users buf or by file size */
> remaining = filesize - fs->PositionInFile;
> if (count < remaining)
> remaining = count;
>
> while (fs->PositionInFile < filesize) {
> /* Which sector of this cluster did we leave off at last time ? */
> sector_offset = fs->PositionInCluster / SECTORSIZE;
>
> /* Which byte of that sector did we leave off at last time ? */
> byte_offset = fs->PositionInCluster % SECTORSIZE;
>
> /* Sector address to start reading this time */
> sector = starting_sector(fs->CurrentCluster, fs->wd->pi);
> if (sector == 0) {
> /* FAT problem ? */
> return 0;
> }
> sector += sector_offset;
>
> /* How many sectors left to read in this cluster */
> nsectors = fs->wd->pi->SectorsPerCluster - sector_offset;
>
> while (nsectors) {
> if (remaining <= (SECTORSIZE - byte_offset)) {
> /* End of file or end of buffer occurs in this sector
> * Read what's left and quit */
> fs->PositionInFile += remaining;
> fs->PositionInCluster += remaining;
> return (remaining + readcount);
> }
> /* End of file is beyond this sector */
> n = SECTORSIZE - byte_offset;
>
> fs->PositionInFile += n;
> fs->PositionInCluster += n;
> readcount += n;
> remaining -= n;
>
> /* Point to start of next sector in cluster */
> byte_offset = 0;
> sector += 1;
> nsectors -= 1;
> } /* end of while */
>
> /* Done with that cluster, advance to the next one */
> fs->CurrentCluster = next_cluster(fs->CurrentCluster, fs->wd->pi);
> if (fs->CurrentCluster == BAD_CLUSTER) {
> /* Bad cluster address - this means that there is a FAT problem,
> * because we should have dtected that this was the last cluster
> * based on filesize. The file system is hosed. */
> return 0;
> }
> /* We are at the start of this new cluster */
> fs->PositionInCluster = 0;
> }
>
> return readcount;
>
> }
>
> HTH,
> -- Mike
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