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On 17 Mrz., 16:31, Antti <Antti.Luk...@googlemail.com> wrote: > in virtually ALL cases where you need solution you need the "case > acceleration" to next level(s) That's fine. Filter out the dumb questions first. While there seems to be a clear path for vertical eelvation of the case to a higher level horizontal changes from one department to the other seems to be more difficult. KoljaArticle: 130176
I am experiencing intermittent failure on a custom V4FX20 board. The majority of the time when power is applied the SysACE configures and starts the application correctly. I have an external watchdog component that activates the ACE reset if certain events are detected, the wdog is working correctly. However, there are times when on Pwr-on that the FPGA appears to configure correctly but not start the application - my external watchdog will detect this and resets the ACE controller. The FPGA re- configures properly, but the app still fails to start. Basically, if my application ran at power on, it will always run after a ACE reset - likewise, if my app failed to start at power on, it will never start after an ACE reset. Any ideas as to why this is behaving this way? ThanksArticle: 130177
Antti wrote: > On 17 Mrz., 13:58, David Brown <da...@westcontrol.removethisbit.com> > wrote: >> Antti wrote: >>> On 17 Mrz., 11:16, sky46...@trline4.org wrote: >>>>> Why and how has xilinx managed to create software that triggers virus >>>>> on alert on task "HDL parse" ??? >>>> Those virus checkers tend to shoot from the hip. >>> If Xilinx would do REAL BETA testing, it could still be possible to >>> prevent that SP3->SP4 update causes the anti-virus alerts come!! >> Should Xilinx check all their software with all the virus checkers >> available? False alarms like that are the fault of the virus checkers, >> and are a good example of how useless most windows "security" software >> really is (hint - if your desktop anti-virus software finds something >> during on-access scanning, you've done something badly wrong). > > there are not so many virus scanners actually, and yes this test could > be done. > That depends on whether you count different versions - there are lots of people using whatever version of whatever software came with their machines, without updating beyond their initial "free" year. I expect that most FPGA developers are going to be a bit more careful than that, however. But even if Xilinx tests against every available anti-virus at the moment, they can't do anything about the shoddy testing done by anti-virus vendors when tomorrow's signature file calls Xilinx software a virus. Considering how often they manage to mark critical windows system files as viruses, resulting in unbootable computers, I have little respect for their testing methods. > and yes, maybe i need another anti-virus thing ;) > No, you need *no* anti-virus thing on a desktop computer. Your email should be scanned by servers before your desktop sees it, you should be protected from worms and crackers by a hardware firewall (not a paper firewall running on windows), and you should stick to a browser and email client that won't run ActiveX and won't run programs without your explicit permission (i.e., anything but IE for browsing, and anything but OE or O for email). Beyond that - use your common sense and judgement about where you wander on the net, and what attachments you open. Follow those rules, and you can live a carefree, virus-free life even with windows. No more slow virus checkers crippling your file system performance, no more irritating "firewall" popups asking if you really want to run the program you've just started, no more windows updates blocking you out of your computer and causing havoc with previously working applications.Article: 130178
> However > Icarus verilog still has some problems withe the present Lattice > code. Hopefully stephen, cary and Larry wil care. What is the problem? Cheers, JonArticle: 130179
> as of mico32 with XST, I did that LOOOOONG ago > it did take maybe some hour of tweaking. XST > doesnt support verilog good enough to synthesize mico32 code They've only had 7 years to implement Verilog 2001 after all. How hard can it be? Cheers, JonArticle: 130180
Kolja, The webcase tracking system is pretty sophisticated, and never forgets. The first CAE assigned has specific goals, and a time limit. Once they fail, the case pops up to the next level, where there are different goals. Even the first CAE assigned has access to thousands of internal answers (how other similar cases were resolved). And, so on, and so forth, until the escalation reaches the "Fire Department" (basically, the Xilinx equivalent of the Incident Command System (ICS), which is used throughout the world as a standard means of dealing with emergencies). Your local police, and fire departments probably all use the ICS. http://en.wikipedia.org/wiki/Unity_of_command#Unity_of_Command The "Fire Department" consists of a "Fire Chief" for each division, who is empowered to tap anyone on the shoulder, and form a team. These "Chiefs" are ultimately responsible to Moshe (he sees the "Fire Chief" reports). This system has been around for 7 years now, and gets refined with each new chief (the 'chief job' is a one year assignment here in APD). The good news is the number of "emergencies" is very small (often 0, only one, and sometimes two). Xilinx prides itself on their customer service (the goal is to be best in class). Any issues, problems, etc. Peter and I take VERY SERIOUSLY, so you may email either of us (or both) directly if you feel our service is not up to par. AustinArticle: 130181
I wish to design a FIFO to tansfer data from a high speed clock
domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to use
the cores available from any of the vendors.
Inputs =>
DataIn // 16 bit data input that is latched in on the posedge of
clkHigh when Wen is high
Wen // Write enable to strobe in the data into the register
Ren // read enable strobe to let the reg know data was read
out of the DataOut register
clkHigh // High speed clock for writing data in
clkLow // low speed clock for reading data out
Outputs =>
DataOut // 16 bit data out that is changed to the next value (or
all low if nothing is yet stored inside) when Ren
goes low after toggling high based on the clkL
Full // signal goes high when all input registers are filled
up.
Empty // Goes high when nothing
How to decide on the depth of register DataOut to ensure that data is
not overwritten. The issue is that the FIFO has to have some high
speed storage capacity to allow for more data coming in then was
written out.
Any suggestions would be appreciated.
Article: 130182On Mar 17, 10:45=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > I wish to design a FIFO to tansfer data from a high speed clock > domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to use > the cores available from any of the vendors. > > Inputs =3D> > DataIn =A0 =A0 =A0 // 16 bit data input that is latched in on the posedge = of > clkHigh when Wen is high > Wen =A0 =A0 =A0 =A0 // Write enable to strobe in the data into the registe= r > Ren =A0 =A0 =A0 =A0 // read enable strobe to let the reg know data was rea= d > out of the DataOut register > clkHigh =A0 =A0// High speed clock for writing data in > clkLow =A0 =A0// low speed clock for reading data out > > Outputs =3D> > DataOut =A0 =A0// 16 bit data out that is changed =A0to the next value (or= > all low if nothing is yet stored inside) when Ren > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goes low after toggling high based on t= he clkL > Full =A0 =A0 =A0 =A0 =A0// signal goes high when all input registers are f= illed > up. > Empty =A0 =A0 // Goes high when nothing > > How to decide on the depth of register DataOut to ensure that data is > not overwritten. The issue is that the FIFO has to have some high > speed storage capacity to allow for more data coming in then was > written out. > > Any suggestions would be appreciated. You need to know at what average and what burst rates you need to design for, both filling and emptying the FIFO. Without a limit on the input fill rate, you need an infinite-sized FIFO. So - figure out your limits and design your FIFO based on max fill and min empty rate conditions. Otherwise, FIFOs *can* be straight-forward. Synchronous FIFOs are easier if the 320 MHz and 40 MHz domains are precisely aligned but Gray code based FIFOs for asynchronous domains aren't too much worse as long as you don't need to cut the delay for a new value to the absolute minimum time possible; an extra clock of delay makes things work beautifully. - John_HArticle: 130183
On Mar 17, 1:55=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > On Mar 17, 10:45=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > > > > > > > I wish to design a FIFO to tansfer data from a high speed clock > > domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to use > > the cores available from any of the vendors. > > > Inputs =3D> > > DataIn =A0 =A0 =A0 // 16 bit data input that is latched in on the posedg= e of > > clkHigh when Wen is high > > Wen =A0 =A0 =A0 =A0 // Write enable to strobe in the data into the regis= ter > > Ren =A0 =A0 =A0 =A0 // read enable strobe to let the reg know data was r= ead > > out of the DataOut register > > clkHigh =A0 =A0// High speed clock for writing data in > > clkLow =A0 =A0// low speed clock for reading data out > > > Outputs =3D> > > DataOut =A0 =A0// 16 bit data out that is changed =A0to the next value (= or > > all low if nothing is yet stored inside) when Ren > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goes low after toggling high based on= the clkL > > Full =A0 =A0 =A0 =A0 =A0// signal goes high when all input registers are= filled > > up. > > Empty =A0 =A0 // Goes high when nothing > > > How to decide on the depth of register DataOut to ensure that data is > > not overwritten. The issue is that the FIFO has to have some high > > speed storage capacity to allow for more data coming in then was > > written out. > > > Any suggestions would be appreciated. > > You need to know at what average and what burst rates you need to > design for, both filling and emptying the FIFO. =A0Without a limit on > the input fill rate, you need an infinite-sized FIFO. =A0So - figure out > your limits and design your FIFO based on max fill and min empty rate > conditions. =A0Otherwise, FIFOs *can* be straight-forward. =A0Synchronous > FIFOs are easier if the 320 MHz and 40 MHz domains are precisely > aligned but Gray code based FIFOs for asynchronous domains aren't too > much worse as long as you don't need to cut the delay for a new value > to the absolute minimum time possible; an extra clock of delay makes > things work beautifully. > > - John_H- Hide quoted text - > > - Show quoted text - The FIFO is 16 bits wide and 8 words deep. The purpose of using this FIFO is for synchronization between the 2 clock domains.Article: 130184
Antti, > now a bit-serialized CPU to the above spec can be done. > it would use less than 100 slices. As you make a design more and more serial, you will often find yourself forced to add some extra registers. So a totally serial implementation is not necessarily the smallest one. In some of my own experiements, four bits proved to be the optimial size (though I was also taking performance into account when doing the evaluations). -- JecelArticle: 130185
Jon Beniston <jon@beniston.com> wrote: > > However > > Icarus verilog still has some problems withe the present Lattice > > code. Hopefully stephen, cary and Larry wil care. > What is the problem? At the moment, Icarus Verilog often stumbles over complex parameter or defines definitions. Problem report [ 1634527 ] Constant functions not recognized as constant describes the problem. It is one of the open priority 6 problems. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 130186
Daniel wrote: > Ok, the existing IP uses a lot of clocks and my logic must be very > simple. Anyway I'd like to ask what is the difference between IBUFG > and BUFG. > If the input to the DCM is: > > bufg_syncclk: bufg port map ( i=>sync_clk, o=>sync_clk_dcm); > > I get the error, but if the input is: > > bufg_syncclk: ibufg port map ( i=>sync_clk, o=>sync_clk_dcm); > > I don't. > > Why happens that?. Should I LOC the clock buffers?. It sounds like the problem is that you are specifying a pin for the clock that does not connect directly to an ibufg that connects directly to a dcm. What device/package/clock pin are you specifying? A bufg can be accessed with local routing resources from any input pin on the package. This might introduce a tiny bit more jitter, but is otherwise ok for many situations. An ibufg by definition means the connection from the pin to the buffer uses dedicated routing, not local routing resources. If you specify an ibufg, but the clock pin you picked is not connected with dedicated routing resources, then you will get an error like that.Article: 130187
sky465nm@trline4.org wrote: (snip) > The crc you need to apply is the CRC32 AUTODIN II. This is to be applied to > all bits after the frame start. In 10/100M ethernet each 4-bits is in > reverse order (low nibble - high nibble). So you may need to swap these > before feeding the bits to the crc32 generator. 10 megabit ethernet is sent LSB first, and traditionally processed using an LFSR to generate the CRC. So, in nibble mode, I would expect low nibble then high nibble would be right for a four bit CRC generator. Remember to initialize to all 1's (or F's), and complement later. -- glenArticle: 130188
"Kolja Sulimma" <ksulimma@googlemail.com> wrote in message news:e7a63971-0988-46db-b10f-3e6a9c7a4b20@e60g2000hsh.googlegroups.com... > > If someone dealing with a webcase finds that he is not the right > person to deal with the case they usually suggest that I start a new > case with an additional keyword to have it (hopefully) routed to the > right expert. > > I think that is a strange strategy. > I've never had this happening to me and I've filed quite a few cases... /MikhailArticle: 130189
On Mar 17, 11:03=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > On Mar 17, 1:55=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > > > > > > On Mar 17, 10:45=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > > > > I wish to design a FIFO to tansfer data from a high speed clock > > > domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to use > > > the cores available from any of the vendors. > > > > Inputs =3D> > > > DataIn =A0 =A0 =A0 // 16 bit data input that is latched in on the pose= dge of > > > clkHigh when Wen is high > > > Wen =A0 =A0 =A0 =A0 // Write enable to strobe in the data into the reg= ister > > > Ren =A0 =A0 =A0 =A0 // read enable strobe to let the reg know data was= read > > > out of the DataOut register > > > clkHigh =A0 =A0// High speed clock for writing data in > > > clkLow =A0 =A0// low speed clock for reading data out > > > > Outputs =3D> > > > DataOut =A0 =A0// 16 bit data out that is changed =A0to the next value= (or > > > all low if nothing is yet stored inside) when Ren > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goes low after toggling high based = on the clkL > > > Full =A0 =A0 =A0 =A0 =A0// signal goes high when all input registers a= re filled > > > up. > > > Empty =A0 =A0 // Goes high when nothing > > > > How to decide on the depth of register DataOut to ensure that data is > > > not overwritten. The issue is that the FIFO has to have some high > > > speed storage capacity to allow for more data coming in then was > > > written out. > > > > Any suggestions would be appreciated. > > > You need to know at what average and what burst rates you need to > > design for, both filling and emptying the FIFO. =A0Without a limit on > > the input fill rate, you need an infinite-sized FIFO. =A0So - figure out= > > your limits and design your FIFO based on max fill and min empty rate > > conditions. =A0Otherwise, FIFOs *can* be straight-forward. =A0Synchronou= s > > FIFOs are easier if the 320 MHz and 40 MHz domains are precisely > > aligned but Gray code based FIFOs for asynchronous domains aren't too > > much worse as long as you don't need to cut the delay for a new value > > to the absolute minimum time possible; an extra clock of delay makes > > things work beautifully. > > > - John_H- Hide quoted text - > > > - Show quoted text - > > The FIFO is 16 bits wide and 8 words deep. The purpose of using this > FIFO is for synchronization between the 2 clock domains.- Hide quoted text= - > > - Show quoted text - So if you know it's 8 words deep, what's the problem? Is it that you don't know how to design a FIFO from scratch since you don't want to use a core? Please specify if the domains are 100% synchronous or if they're asynchronous. If you can't guarantee phase alignment of the two domains, consider it asynchronous. Please verify that you want the empty flag on the read side and the full on the write side. Specify whether you're a VHDL or Verilog engineer. What family and vendor is your FPGA? Do you want to target a specific memory type (such as CLB SelectRAM or M512 RAMs)? You're no stranger to the board so this doesn't appear to be homework; why avoid the cores? - John_HArticle: 130190
On Mar 17, 11:27=A0am, Jecel <je...@merlintec.com> wrote: > Antti, > > > now a bit-serialized CPU to the above spec can be done. > > it would use less than 100 slices. > > As you make a design more and more serial, you will often find > yourself forced to add some extra registers. So a totally serial > implementation is not necessarily the smallest one. In some of my own > experiements, four bits proved to be the optimial size (though I was > also taking performance into account when doing the evaluations). > > -- Jecel But in the Xilinx fabric, for instance, shift registers are very inexpensive. Antti's divider back on 22 Mar 2005 "divide by 2^n, n=3D21..37 =3D=3D> 3 Virtex Slices !!" was an excellent example of serial going very small. http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/1bfa9e3a2577= 1282 Serial logic in FPGAs has some very strong advantages over parallel implementations for speed versus density metrics, allowing the fabric to often run at maximum FPGA clock speeds. It's great stuff! - John_HArticle: 130191
I'm using a virtex2p VP40 (xc2vp40-5ff1152). The pin is AH17, according to the datasheet, it's in bank =EF=BB=BF4 and the inputs are IO_L74N_4/GCLK3S. What I want, is to know the right way to use the DCM. According to the users guide, both ways (IBUFG and BUFG) are OK. I want to know which one should I use. If I use IBUFG I should look for the corresponding DCM and LOC it?. I guess using BUFG and DCM I run out of BUFG's but using IBUFG I don't. I'm sorry I'm very confused with this and that's because I'm newer. Thanks, Daniel. On Mar 17, 3:33 pm, Duane Clark <junkm...@junkmail.com> wrote: > Daniel wrote: > > Ok, the existing IP uses a lot of clocks and my logic must be very > > simple. Anyway I'd like to ask what is the difference between IBUFG > > and BUFG. > > If the input to the DCM is: > > > bufg_syncclk: bufg port map ( i=3D>sync_clk, o=3D>sync_clk_dcm); > > > I get the error, but if the input is: > > > bufg_syncclk: ibufg port map ( i=3D>sync_clk, o=3D>sync_clk_dcm); > > > I don't. > > > Why happens that?. Should I LOC the clock buffers?. > > It sounds like the problem is that you are specifying a pin for the > clock that does not connect directly to an ibufg that connects directly > to a dcm. What device/package/clock pin are you specifying? > > A bufg can be accessed with local routing resources from any input pin > on the package. This might introduce a tiny bit more jitter, but is > otherwise ok for many situations. An ibufg by definition means the > connection from the pin to the buffer uses dedicated routing, not local > routing resources. If you specify an ibufg, but the clock pin you picked > is not connected with dedicated routing resources, then you will get an > error like that.Article: 130192
On Mar 17, 3:19=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > On Mar 17, 11:03=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > > > > > > > On Mar 17, 1:55=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > > > On Mar 17, 10:45=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > > > > > I wish to design a FIFO to tansfer data from a high speed clock > > > > domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to us= e > > > > the cores available from any of the vendors. > > > > > Inputs =3D> > > > > DataIn =A0 =A0 =A0 // 16 bit data input that is latched in on the po= sedge of > > > > clkHigh when Wen is high > > > > Wen =A0 =A0 =A0 =A0 // Write enable to strobe in the data into the r= egister > > > > Ren =A0 =A0 =A0 =A0 // read enable strobe to let the reg know data w= as read > > > > out of the DataOut register > > > > clkHigh =A0 =A0// High speed clock for writing data in > > > > clkLow =A0 =A0// low speed clock for reading data out > > > > > Outputs =3D> > > > > DataOut =A0 =A0// 16 bit data out that is changed =A0to the next val= ue (or > > > > all low if nothing is yet stored inside) when Ren > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goes low after toggling high base= d on the clkL > > > > Full =A0 =A0 =A0 =A0 =A0// signal goes high when all input registers= are filled > > > > up. > > > > Empty =A0 =A0 // Goes high when nothing > > > > > How to decide on the depth of register DataOut to ensure that data i= s > > > > not overwritten. The issue is that the FIFO has to have some high > > > > speed storage capacity to allow for more data coming in then was > > > > written out. > > > > > Any suggestions would be appreciated. > > > > You need to know at what average and what burst rates you need to > > > design for, both filling and emptying the FIFO. =A0Without a limit on > > > the input fill rate, you need an infinite-sized FIFO. =A0So - figure o= ut > > > your limits and design your FIFO based on max fill and min empty rate > > > conditions. =A0Otherwise, FIFOs *can* be straight-forward. =A0Synchron= ous > > > FIFOs are easier if the 320 MHz and 40 MHz domains are precisely > > > aligned but Gray code based FIFOs for asynchronous domains aren't too > > > much worse as long as you don't need to cut the delay for a new value > > > to the absolute minimum time possible; an extra clock of delay makes > > > things work beautifully. > > > > - John_H- Hide quoted text - > > > > - Show quoted text - > > > The FIFO is 16 bits wide and 8 words deep. The purpose of using this > > FIFO is for synchronization between the 2 clock domains.- Hide quoted te= xt - > > > - Show quoted text - > > So if you know it's 8 words deep, what's the problem? =A0Is it that you > don't know how to design a FIFO from scratch since you don't want to > use a core? I am not sure if the design would change depending on whether the high and low frequencies change. > > Please specify if the domains are 100% synchronous or if they're > asynchronous. =A0If you can't guarantee phase alignment of the two > domains, consider it asynchronous. Asynchronous. > > Please verify that you want the empty flag on the read side and the > full on the write side. Yes > > Specify whether you're a VHDL or Verilog engineer. Verilog > > What family and vendor is your FPGA? =A0Do you want to target a specific > memory type (such as CLB SelectRAM or M512 RAMs)? I dont want the design to be specific to a particular chip. > > You're no stranger to the board so this doesn't appear to be homework; > why avoid the cores? The cores are not getting simulated with Modelsim XE. And I would like to design my own in either case. > > - John_H- Hide quoted text - > > - Show quoted text -Article: 130193
Jecel wrote: > Antti, > > >>now a bit-serialized CPU to the above spec can be done. >>it would use less than 100 slices. > > > As you make a design more and more serial, you will often find > yourself forced to add some extra registers. So a totally serial > implementation is not necessarily the smallest one. In some of my own > experiements, four bits proved to be the optimial size (though I was > also taking performance into account when doing the evaluations). Do you mean a 4 bit CPU, or a nibble-serial design of a larger 16/20/24/28/32 bit CPU ? (There are 4 bit CPUs with tool chains, the Atmel MARC4, and the Atom from CoreRiver ) http://www.coreriver.co.kr/product-lines/CORERIVERmcu_linkATOM.html -jgArticle: 130194
On Mar 17, 1:29=A0pm, FPGA <FPGA.unkn...@gmail.com> wrote: <snip> > And I would like to design my own in either case. <snip> So why are you asking us? ;-)Article: 130195
Hi! We are students working on implementing FFT on FPGA, virtex 4. We used Chipscope to test our code and capture signals off the hardware while its running. when we tried to test an 8 bit adder using chipscope, in the ILA core, we constantly got an error which said 'waiting for core to be armed'. We understand that this indicates that appropriate trigger signal has not been provided. We've tried everything possible but we're not able to figure out how to provided an appropriate trigger. some of the things we tried: 1) specified the two 8 bit inputs as trigger 2) specified the clock as trigger. Both the above had failed. So please help us by telling how to proceed.Article: 130196
Have you read: http://www.xilinx.com/support/documentation/index.htm Search for: chipscope trigger Lots and lots of things that might help. AustinArticle: 130197
On Mar 15, 7:19 am, Mike Treseler <mike_trese...@comcast.net> wrote:
> Xilinx User wrote:
> > I hope Xilinx introduces Systemverilog synthesis with ISE 10.1
>
> Systemverilog is mainly a simulation upgrade.
Mike,
While a large part of the SystemVerilog standard is dedicated to
simulation upgrades, there's
a large set of added design features. In fact, I'd argue that if we
compare the productivity gain
(for Design) from:
Verilog 1995 -> Verilog2001
and
Verilog 2001 -> SystemVerilog
The latter wins, hand down.
It's a shame we're still waiting for support from FPGA vendors here.
Regards,
Mark
Article: 130198Daniel wrote: > I'm using a virtex2p VP40 (xc2vp40-5ff1152). The pin is AH17, > according to the datasheet, it's in bank 4 and the inputs are > IO_L74N_4/GCLK3S. > What I want, is to know the right way to use the DCM. According to the > users guide, both ways (IBUFG and BUFG) are OK. I want to know which > one should I use. > If I use IBUFG I should look for the corresponding DCM and LOC it?. > > I guess using BUFG and DCM I run out of BUFG's but using IBUFG I > don't. > There are not actual different devices on the chip for ibufg and bufg, so whether you specify ibufgs or bufgs, you will run out at the same time. I don't ever LOC DCMs in the virtex2p devices I use, and I have not specified ibufgs; I always just use bufgs, and specify only the clock pin location. So I don't really know what the problem is in your case, and why specifying an ibufg fixes it. You say that you have a lot of clocks (something you might want to rethink ;). Are all the other clocks locked to pins, and is one locked to AJ17?Article: 130199
Antti wrote: > * 32 bit registers, say block of 16 (use 32 LUTRAM == 16 LUT/LC) > * serialized can run from spi flash up to 320MBit with > http://www.winbond.com/NR/rdonlyres/4C63AD62-967C-4B72-AF85-1F5984E8B199/0/W25Q80.pdf > * can address large code space > * can run at high fabric clocks (due to lack of parallel buses and > parallel ALUs) > > now a bit-serialized CPU to the above spec can be done. > it would use less than 100 slices. > > if anyone is willing to desing this CPU, I may have funds for it, > really please... Did you mean you have someome to fund this, or that you could do it if someone funds you ? > > hm at 320MB/sec spi streaming, we get byte reads at 40Mhz from serial > flash! and you can add a second SPI chip, if you want to double the bandwidth to 80MB/Sec. Of course, the jump latency does not improve, but a matched core design would minimise jumps. Short-Skip opcodes are an obvious cadidate. -jg
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