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Hi all, I'm trying to determine the correct procedure for simulating BRAMs using Xilinx ISE and ISE simulator (not ModelSim). Cores are generated using CoreGenerator and include initialization, which seems to be a part of the problem. What I've tried to do is to copy the core itself (.ngc), the simulation wrapper file (.vhd) and the memory initialization file (.mif) to my project's directory, include the .vhd file in the project and instantiate the core in the top module. Then I've created a testbench waveform and tried to simulate the top module but the behavioral simulation is incorrect: the BRAM's dout output is always 'U' in ISE 9.2 and ok in ISE 10.1., but in ISE 10.1 the initialization is ignored even though all the attributes (c_init_file_name etc.) seem correct in the .vhd file. Post-route simulation works fine but I still want the behavioral simulation to work for future (larger) designs. Any idas? I've tried the manuals, but all I've found has to do with compiling simulation libraries which doesn't seem to be required with ISE simulator. TIA and sorry if this is a bit of a noob question. Cheers, RGArticle: 135276
On Sep 23, 11:42=A0am, Gael Paul <gael.p...@gmail.com> wrote: > 5. Once you have converted your generated clock, you will probably > need to add multi-cycle paths constraints to avoid false critical > paths. Avoid using multi-cycle path constraints unless you absolutely have to use them, or are getting unacceptably long run-times trying to meet single cycle timing on those paths. The reason is that multi-cycle and false path constraints can be tricky to specify correctly, and make sure that only those paths that are truly multi-cycle or false are constrained (actually relaxed) as such. There are a few tools out there than supposedly can identify or verify multi-cycle and false paths in your design by formal analysis, but they are very expensive. Otherwise, full timing, post-route simulation can find some of the improperly constrained paths, but not all. The best defense against an ill-specified multi-cycle or false path is not to specify it in the first place. If you must use them, then a tcl command script to identify all paths covered by the constraint, and judicious review of each one is critical. Also consider adding assertion statements and supporting code to your rtl code that can verify multi-cycle paths are truly multi-cycle during functional RTL simulations. Also, full timing simulations should target design areas that use multi-cycle constraints. Treating related but uncontrolled clock domain crossings as asynchronous clock domain crossings can lead to problems. Statistical models for metastability are based on uncorrelated clocks, whereas related clocks (derived from the same source) are highly correlated. Instead of one edge per hundred or million cycles lining up just wrong, you could have every edge line up just wrong, greatly increasing the potential for statistically much longer metastability periods, which increases the likelihood that they could defeat traditional meta-stable rejection techniques (like double registering, etc.). Try very hard to constrain related clocks such that crossings between them are guaranteed to meet setup and hold requirements. AndyArticle: 135277
On Sep 23, 8:54=A0am, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> wrote: > On Sep 23, 2:52 pm, Andy <jonesa...@comcast.net> wrote: > > > > > You can also use "if rising_edge(clk) and clk_enable =3D '1' then" to > > I was told explicitly by a textbook that this isn't synthesisable so I > never tried it out. > I'm not surprised. Early synthesis tools were very much code-template based. If you varied from the narrow set of templates, they wouldn't work. Responsiveness to customer demands and competing tools' capabilities has changed that a lot, particularly with FPGA synthesis tools. Textbooks are notoriously out of date with respect to synthesis capabilities and best practices. AndyArticle: 135278
Hi Jon, "maxascent" <maxascent@yahoo.co.uk> wrote in message news:ReidnbnFVd2xakXV4p2dnAA@giganews.com... > Can I just connect the mode select pins (M0-M2) to power/gnd depending on > my required programming mode or do I need to connect them to resistors? If > I select a master serial mode will it prevent me from using JTAG. Sorry, I can't tell which family you are using. However, here's a snippet from page 47 in UG332: Spartan-3 Generation Configuration User Guide. http://www.xilinx.com/support/documentation/user_guides/ug332.pdf "?During configuration, the M[2:0] pin may be tied directly to power or ground, tied High or Low using external resistors, or actively driven by an external component." In many designs, I like to use pull-up/pull-down resistors as it always gives me the option to overdrive the resistor values and change the configuration mode. However, if you never need that flexibility, then the resistors are just extra space and expense. IIRC, JTAG is always functional, even if using Master Serial configuration mode. However, depending on the family on the programmed/unprogrammed status of the serial PROM, you can run into some issues. You can still reprogram the serial PROM via JTAG. You can still run ChipScope. However, the follow Answer Record seems to indicate that there might be problems if you are attempting to directly program the FPGA if the PROM is already programmed. For some reason, I thought that this was fixed in recent released, but perhaps not. http://www.xilinx.com/support/answers/9013.htm Again, some of the nuances depend on the specific FPGA family. =============================================== Steven K. Knapp Prevailing Technology, Inc. Web: www.prevailing-technology.comArticle: 135279
On 23 Sep 2008 04:37:34 -0700, thutt <thutt151@comcast.net> wrote: >Brian Drummond <brian_drummond@btconnect.com> writes: > >> On 20 Sep 2008 09:48:58 -0700, thutt <thutt151@comcast.net> wrote: ... >> >Is there any way to get the tools to output a netlist that is in the >> >more useful (to me) 'RTL' format? >> >> Have you looked at the post-synthesis simulation model (in VHDL)? >> >> - Brian > >No. Why? > >I don't understand; I'm not looking to simulate, I'm looking to view a >schematic outside of ISE. Because it is basically a netlist, in VHDL syntax. Its uses are not limited to simulation; I sometimes use it in preference to the RTL viewer (a) because it's easily searchable and (b) the viewer strikes me as unbelievably slow. Unfortunately as Kevin says, it's probably closer to a technology view than the RTL view you want. - BrianArticle: 135280
On Fri, 19 Sep 2008 09:54:27 -0700, Peter Alfke wrote: > After 13 years and >2000 postings I will retire from comp.arch.fpga. I Peter, thank you for sharing so much of your knowledge. I learned a lot from reading your posts. Xilinx should understand that accumulated influence of people like you and Austin may be more important than a legion of marketeers. They should make you an editor, and give you a bunch of them to ghost-write the docs as you see fit. -- Przemek Klosowski, Ph.D. <przemek.klosowski at gmail>Article: 135281
On 2008-09-23, glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:
> The Intel 8086 and 8088 use a 33% duty cycle clock for maximum
> clock speed. Something strange in that design.
My guess would be that this is caused by a latch based design.
I guess that a structure as the one below might cause non
50% duty-cycle clocks to be more optimal although I don't have
any personal experience in designing such latch based designs:
Logic (with delay t)
|
V
Latch (Enabled by positive clk)
|
V
Logic (with delay 2*t)
|
V
Latch (Enabled by negative clk)
/Andreas
Article: 135282On Sep 23, 12:55=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Mon, 22 Sep 2008 11:51:29 -0700 (PDT), osquillar > > <ogm101...@hotmail.com> wrote: > >> > > > Hello all, I'm working with an microblaze system and I'm trying = to > >> > > > work with a Micron MT48LC16M16 memory and something strange happ= ens, > >> > > > It seem than I can read positions all position but if I try to w= rite > >> > > > in positions 00 and 01 nothing changes and if I write something = in > >> > > > positions 02 and 03 they seems to be written in position 00 and = 01. It > >> > > > happens the same with the rest of the memory. > >ADDRESS =A0 =A0 =A0 =A000 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F > >DATA WRITTEN 01 23 45 67 89 AB CD EF 11 22 33 44 55 66 77 88 > > >If I read the result after writting. > > >ADDRESS =A0 =A0 =A0 =A000 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F > >DATA WRITTEN 45 67 FA DE CD EF 25 27 33 44 DA 11 77 88 FE A2 > > What result did you get in simulation? > > - Brian Hello Brian, I did not simulate it.Article: 135283
Thanks for the reply. I've tried very hard to find something definite regarding the PHY I'm using (Marvell 88E1112) but can't. In my original post I meant different PHYs seem to be connected differently. From what you say, IF the 88E1112 is a current mode driver, connecting to 2.5V could be the correct thing to do. Roger. "MM" <mbmsv@yahoo.com> wrote in message news:6jsmqmF4ulb3U1@mid.individual.net... > It's not clear from your post whether you are talking about the same PHY > used differently or different PHYs. PHY output drivers can be either > voltage or current mode. Current mode drivers require pullup to a voltage > source. Some PHYs have different dirvers in different modes of operation > (e.g. 10BaseT vs. 100 or 1000BaseT). Also, there are a few different types > of magnetics used, which might require different termination schemes. Try > to find appnotes relevant to the PHY you are using. > > /Mikhail > > > > "Roger" <rogerwilson@hotmail.com> wrote in message > news:xP6dnerrZZ6bakrVnZ2dnUVZ8sDinZ2d@posted.plusnet... >> The paired MDI signals from the PHY to the magnetics in a GbE application >> are each terminated by a 50R resistor and then together to a 10nF >> capacitor >> to GND. However some applications connect the 2 resistors to Vcc (2.5V) >> as >> well. Can anyone explain why some configurations are like this and others >> aren't? Is it something specific to the magnetics? >> >> TIA, >> >> Rog. > >Article: 135284
On Wed, 24 Sep 2008 00:25:55 -0700 (PDT), osquillar <ogm101274@hotmail.com> wrote: >On Sep 23, 12:55 pm, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> On Mon, 22 Sep 2008 11:51:29 -0700 (PDT), osquillar >> >> <ogm101...@hotmail.com> wrote: >> >> > > > Hello all, I'm working with an microblaze system and I'm trying to >> >> > > > work with a Micron MT48LC16M16 memory and something strange happens, >> >> > > > It seem than I can read positions all position but if I try to write >> >> > > > in positions 00 and 01 nothing changes and if I write something in >> >> > > > positions 02 and 03 they seems to be written in position 00 and 01. It >> >> > > > happens the same with the rest of the memory. >> >ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F >> >DATA WRITTEN 01 23 45 67 89 AB CD EF 11 22 33 44 55 66 77 88 >> >> >If I read the result after writting. >> >> >ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F >> >DATA WRITTEN 45 67 FA DE CD EF 25 27 33 44 DA 11 77 88 FE A2 >> >> What result did you get in simulation? >> >> - Brian > >Hello Brian, I did not simulate it. That makes it unnecessarily hard to find the problem, which looks like a pipeline error of some kind, such as data being presented to the memory a cycle or two late, or an unintended pipeline stage in the read path. Micron publish simulation models for their devices. Unfortunately, no longer in VHDL, but depending on your simulator you may be able to use the Verilog models they publish. Some Modelsim licences allow mixed language simulation. Also the ISE simulator (in ISE 10) allows it in theory, but in practice you have to find a workaround for a crash. If you are using Modelsim you can find the equivalent Hynix part; Hynix publish VHDL models, but only precompiled for Modelsim... - BrianArticle: 135285
On Sep 23, 5:54=A0pm, "Steve Knapp" <steveD.O.TknappA.Tprevailing- technologyD.O.Tcom> wrote: > IIRC, JTAG is always functional, even if using Master Serial configuratio= n > mode. =A0 Normal JTAG functions are always available. JTAG configuration functions (on some devices, including at least V2) are not available unless the mode pins are set to JTAG, or a valid configuration has already been completed. Don't ask me how I know... ;^) AndyArticle: 135286
On Sep 23, 8:53=A0am, vasu <vasu.devun...@gmail.com> wrote: > On Sep 22, 8:17=A0pm, Rob <BertyBoos...@googlemail.com> wrote: > > > > > Hi all, > > > I'm having problems with ISE seemingly ignoring timing constraints set > > in the UCF file. One of the constraints ignored comes from Xilinx's > > MIG tool and looks like this: > > > INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM =3D > > "TNM_PHY_INIT_DATA_SEL"; > > TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" =3D FROM "TNM_PHY_INIT_DATA_SEL" T= O > > FFS > > "TS_SYS_CLK" * 4; > > > I'm not getting any errors, such as unable to locate nets, rather the > > constraint seems ignored and looking in the timing report it is these > > very paths that are failing (by a long way). I thought that if the > > target nets don't exist then you get a translate error. > > > I am using partitions in the design. I've tried to do a build after a > > "clean up project files" and the constraint is still ignored. > > > Any ideas? > > > Rob > > Is this the only consrtaint in your design? If there are many, one of > them migth be covering these paths. So its better to run the TSI > report and check the path coverage. I've had a look at the TSI report and the ignored constraints aren't mentioned. This may be a silly question, but does it matter if some timing constraints are entered in the UCF, then loads of other constraints followed by some more timing contraints? I edit the constraints by hand and so the timing constraints aren't grouped together. RobArticle: 135287
what's the best way to transform decimal numbers to 32bits wide ieee 754 single precision floating point numbers? possibly using perl or verilog. i did some searching, there are converters like this http://babbage.cs.qc.edu/IEEE-754/Decimal.html, but not for large amount of data. thanks, -jArticle: 135288
On 23 Wrz, 11:31, secure...@gmail.com wrote: > Hi, > > I have implemented a system OFDM 2K with band of 8 MHz, style DVB-T. > Using a system clock of 64 MHz everything works perfectly. Now I > should be able to decrease the band OFDM to 7/6/5 MHz using the same > 64 MHz clock. To get the bandwidth of 8 MHz in 2K (1705 active > portant), simply clock output data from a IFFT at period of 7/64e6 = > 109.375 nS. > > In that way or with that technique can reduce the clock out for obtain > 7/6/5 MHz of band ? Without necessarily changing the clock 64 MHz ? > > Any idea ? > You can design new OFDM symbol, without part of carriers. But you have lower throughput in link. It's simplest way: - The same symbol template, - The same clock, - The same spaces between carriers (freq. domain), Regards, Jerzy GburArticle: 135289
Hi, I'm currently developping a FPGA application where I implemented a SDRAM controller with a DCM to remove external skew. So basically, I checked the XAPP462 application note, and I designed the deskew circuit with 1X feedback instead of 2X feedback. When I program the FPGA using the JTAG cable, the DCM locks and everything works fine (i.e. I can read and write the SDRAM correctly). However, when I program the FPGA with the onboard MPU, the DCM doesn't lock at all. It seems to me that it's probably some kind of timing issue with the DCM. I added the reset with the SRL as specified in the application note in order to properly reset the DCM at stat-up. The reason why I'm using 1X feedback instead of 2X feedback is because we have about 30 boards in the field with older silicon revisions of the Spartan3-1500. There's an erratum with the spartan 3 DCM and 2X clock feedback for older silicon revisions. I tried using 2X feedback. The DCM locks in both cases, i.e. when I program with the Platform Cable or when I program using the MPU. However, there's no guarantee that it would work for all our boards in the field since we're stuck with older Spartan 3 silicon revisions. Do you guys have any idea?Article: 135290
On 22 sep, 19:23, Stephen <st...@avalda.com> wrote: > Hello all, > =A0 =A0 I'm pleased to announce the release of Avalda FPGA Developer v1.0 > beta! It enables one to compile regular F# to RTL with parallel > programming semantics. Our aim is to help make FPGAs available to a > wider group of software programmers who may not have as much > experience with HDLs or FPGAs. Please visit Avalda's site to download > the beta and check out the blog! > > cheers, > > Stephen Afande > Avalda Corp.http://www.avalda.com I don't know if it's just me, but I'm suspicious of products that claim that software programmers will be able to program FPGAs without any Hardware experience. Maybe in some niche applications though.Article: 135291
Companies making Ethernet PHYs are very secretive for whatever reason. You need to talk to them to get access to even the most basic information. An NDA might be required, which is difficult to arrange if you don't work for a business. However, if you manage to get access, you will find that there is a lot of information available. A while ago I chose a different vendor because Marvell was slower to respond to my requests for nformation. /Mikhail "Roger" <rogerwilson@hotmail.com> wrote in message news:VZ-dndx23qW1v0fVRVnyvgA@posted.plusnet... > Thanks for the reply. I've tried very hard to find something definite > regarding the PHY I'm using (Marvell 88E1112) but can't. In my original > post I meant different PHYs seem to be connected differently. From what > you say, IF the 88E1112 is a current mode driver, connecting to 2.5V could > be the correct thing to do. > > Roger. >Article: 135292
Benjamin Couillard wrote: > Hi, I'm currently developping a FPGA application where I implemented a > SDRAM controller with a DCM to remove external skew. > > So basically, I checked the XAPP462 application note, and I designed > the deskew circuit with 1X feedback instead of 2X feedback. When I > program the FPGA using the JTAG cable, the DCM locks and everything > works fine (i.e. I can read and write the SDRAM correctly). However, > when I program the FPGA with the onboard MPU, the DCM doesn't lock at > all. It seems to me that it's probably some kind of timing issue with > the DCM. > > I added the reset with the SRL as specified in the application note in > order to properly reset the DCM at stat-up. > > The reason why I'm using 1X feedback instead of 2X feedback is because > we have about 30 boards in the field with older silicon revisions of > the Spartan3-1500. There's an erratum with the spartan 3 DCM and 2X > clock feedback for older silicon revisions. > > I tried using 2X feedback. The DCM locks in both cases, i.e. when I > program with the Platform Cable or when I program using the MPU. > However, there's no guarantee that it would work for all our boards in > the field since we're stuck with older Spartan 3 silicon revisions. > > Do you guys have any idea? > My bet is that clock source is not stable either before the MPU configures the device or is reset sometime after the device was configured by the MPU. Check through your schematics and software code to see how the clock is controlled in the system. You may get some additional insights if you can bring out the DCM locked signal to see what transitions it may have. Ed McGettigan -- Xilinx Inc.Article: 135293
On Sep 24, 5:45=A0am, Andy <jonesa...@comcast.net> wrote: > On Sep 23, 5:54=A0pm, "Steve Knapp" <steveD.O.TknappA.Tprevailing- > > technologyD.O.Tcom> wrote: > > IIRC, JTAG is always functional, even if using Master Serial configurat= ion > > mode. =A0 > > Normal JTAG functions are always available. JTAG configuration > functions (on some devices, including at least V2) are not available > unless the mode pins are set to JTAG, or a valid configuration has > already been completed. Don't ask me how I know... ;^) Yeow! Does anyone know if this is true for V5? I've got a board going to layout with the mode pins grounded for master serial, but I want to be able to do JTAG as well just in case. This is on a BGA part, so if I need to tweak these pins, I'll have to route them out or be screwed. EricArticle: 135294
Hi > Yeow! Does anyone know if this is true for V5? I've got a board going > to layout with the mode pins grounded for master serial, but I want to > be able to do JTAG as well just in case. This is on a BGA part, so if > I need to tweak these pins, I'll have to route them out or be screwed. It worked for me! cheers benArticle: 135295
Thanks for your reply. I have an NDA with Marvell and there is a fair bit of information to be had but I still can't find the answer. I've asked for help from them but they're not very responsive! I don't know why they're so secretive. Rog. "MM" <mbmsv@yahoo.com> wrote in message news:6jv41eF59d0sU1@mid.individual.net... > Companies making Ethernet PHYs are very secretive for whatever reason. You > need to talk to them to get access to even the most basic information. An > NDA might be required, which is difficult to arrange if you don't work for > a business. However, if you manage to get access, you will find that there > is a lot of information available. A while ago I chose a different vendor > because Marvell was slower to respond to my requests for nformation. > > /Mikhail > > > > "Roger" <rogerwilson@hotmail.com> wrote in message > news:VZ-dndx23qW1v0fVRVnyvgA@posted.plusnet... >> Thanks for the reply. I've tried very hard to find something definite >> regarding the PHY I'm using (Marvell 88E1112) but can't. In my original >> post I meant different PHYs seem to be connected differently. From what >> you say, IF the 88E1112 is a current mode driver, connecting to 2.5V >> could be the correct thing to do. >> >> Roger. >> > >Article: 135296
On 24 sep, 13:21, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > Benjamin Couillard wrote: > > Hi, I'm currently developping a FPGA application where I implemented a > > SDRAM controller with a DCM to remove external skew. > > > So basically, I checked the XAPP462 application note, and =A0I designed > > the deskew circuit with 1X feedback instead of 2X feedback. When I > > program the FPGA using the JTAG cable, the DCM locks and everything > > works fine (i.e. I can read and write the SDRAM correctly). However, > > when I program the FPGA with the onboard MPU, the DCM doesn't lock at > > all. It seems to me that it's probably some kind of timing issue with > > the DCM. > > > I added the reset with the SRL as specified in the application note in > > order to properly reset the DCM at stat-up. > > > The reason why I'm using 1X feedback instead of 2X feedback is because > > we have about 30 boards in the field with older silicon revisions of > > the Spartan3-1500. There's an erratum with the spartan 3 DCM and 2X > > clock feedback for older silicon revisions. > > > I tried using 2X feedback. The DCM locks in both cases, i.e. when I > > program with the Platform Cable or when I program using the MPU. > > However, there's no guarantee that it would work for all our boards in > > the field since we're stuck with older Spartan 3 silicon revisions. > > > Do you guys have any idea? > > My bet is that clock source is not stable either before the MPU > configures the device or is reset sometime after the device was > configured by the MPU. > > Check through your schematics and software code to see how the clock is > controlled in the system. =A0You may get some additional insights if you > can bring out the DCM locked signal to see what transitions it may have. > > Ed McGettigan > -- > Xilinx Inc. I'll try that! ThanksArticle: 135297
Since you are posting on c.a.f. you are probably following one of the FPGA eval board reference designs, right? Xilinx ML403 board uses a Marvell chip. I don't remember the exact P/N, but it is something similar to yours. Newer V5 boards might be using newer chips... If you follow one of these examples you should be pretty safe even if you don't understand all the details of the circuit... Also, why don't you post a link to the circuit in question and someone might be able to give you a better advice.... /Mikhail "Roger" <rogerwilson@hotmail.com> wrote in message news:B6OdnSCVGb3LHkfVnZ2dnUVZ8q_inZ2d@posted.plusnet... > Thanks for your reply. I have an NDA with Marvell and there is a fair bit > of information to be had but I still can't find the answer. I've asked for > help from them but they're not very responsive! I don't know why they're > so secretive. > > Rog.Article: 135298
There have been several projects with the goal of compiling functional languages to hw, including Satnam Singh's (ex Xilinx Research Labs) work on Lava. Several such projects are described at http://funhdl.org/wiki/doku.php?id=funhdl One of the more impressive is Sven Woop's HWML for graphics acceleration http://www.sven-woop.de/publications.html Best, PerArticle: 135299
FPGA Laboratory Liquidation Sale. Over 1,000 units - be quick, all stock must go! We have to get these items out of the lab! - The space needs to be cleared for new development. We are practically giving away this stuff so that we can get it into the hands of the creative people that are going to use it - that's you! http://www.burched.com/liquidation Some of the items: * CPLD boards, 10 for 20 bucks ($2 each) * Peripheral Connector Modules, 10 for 20 bucks ($2 each) * Switches modules, 10 for 10 bucks ($1 each) * LEDs modules, 10 for 10 bucks ($1 each) * 5 different grab-bags to choose from * FPGA eval boards, Xilinx and Altera * Lots of FPGA devices for prototyping, Xilinx and Altera * Lots more... Have a look at the pictures at http://www.burched.com/liquidation Prices are in Australian dollars, so when you order from Europe or USA you will be paying less. For example, approximately, AUD$20 = US$16.73 = EURO$11.39 * Stock may run out in less than one or two days. No minimum or maximum order limits per customer.
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