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Messages from 135400

Article: 135400
Subject: Re: Difference between PLD and General purpose CPU`
From: cs_posting@hotmail.com
Date: Tue, 30 Sep 2008 13:52:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 29, 5:51 am, Kolja Sulimma <ksuli...@googlemail.com> wrote:

> An FPGA is configured using a few million bits that can describe
> almost arbitrary behaviour in much detail. This can be seen as one big
> complex instruction. However, a
> conventional FPGA is then bound to this instruction (called
> configuration) and executes the same instruction over and over again.
> Issuing a new instruction takes tens of milliseconds.

From the perspective you wrote, yes.... but don't forget that
an FPGA can also be configured to implement a general purpose
processor, albeit one a few generations in complexity/programmable
performance behind that which could be achieved by general purpose
processor
fabricated in the same technology as the FPGA.

Article: 135401
Subject: Re: Sending UDP packets over Ethernet
From: vjs@calcite.rhyolite.com (Vernon Schryver)
Date: Tue, 30 Sep 2008 21:15:53 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <PvGdnWVRAIdVE3_VnZ2dnUVZ_sninZ2d@comcast.com>,
glen herrmannsfeldt  <gah@ugcs.caltech.edu> wrote:

>Also, you can't accept route redirect or source quench,
>two others that would seem useful in some cases.

ICMP Redirect might be useful, but might involve a lot of machinery
given the target situations of no routers.
I think ICMP Source has been deprecated for more than 20 years.  See
http://www.google.com/search?q=icmp+source+quench+deprecated

For an application like this that might otherwise use raw Ethernet
packets, Source Quench is obviously useless.  In general, Source Quench
is of little use, because transport protocols that real networks can
tolerate have their own congestion avoidance and recovery machinery.
Even if your UDP or other datagram application doesn't have official
congestion management stuff, it ought to have some sort of pacing
machinery that responds to losses caused by losses, which tends to make
ICMP Source Quench irrelevant.  

Besides, ICMP Source Quench uses bandwidth, which can make a merely
marginal situation into a bad situation.  So we get things like TCP
Explicit Congestion Notification   http://www.google.com/search?q=tcp+ecn


Vernon Schryver    vjs@rhyolite.com

Article: 135402
Subject: Re: Sending UDP packets over Ethernet
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 30 Sep 2008 13:41:49 -0800
Links: << >>  << T >>  << A >>
Vernon Schryver wrote:
(snip regarding generating UDP in an FPGA)

> My answer to the question at the start is that in the real world
> there are *always* situations where the absolutely guaranteed
> for certain always and forever promise that there will never be
> a router is broken.   Therefore the low the costs of slapping fake
> but servicable UDP/IP headers in front of the payload are so low that
> you can't afford not to pay them.  There are always test networks if
> the promises about no routers are always and forever met when the
> application is deployed...and the promises usually are broken in some
> deployed case.

But if you supply the MAC address of the router, it will even
work through a router.  The main problem it does have is that
if you change the net around it won't adapt to the change.

If you have no ability to receive you can't do ARP, anyway.
Also, you can't accept route redirect or source quench,
two others that would seem useful in some cases.

But networks do change...

-- glen


Article: 135403
Subject: Re: reasonable timing analysis without mapping design to IO
From: Andy <jonesandy@comcast.net>
Date: Tue, 30 Sep 2008 16:25:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 30, 2:27=A0pm, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:
> Heiner Litz wrote:
> > Hi,
>
> > I want to perform reasonable post place&route timing analysis for some
> > RTL modules. The modules have a higher pin count as the FPGA itself.
> > ISE always tries to map the modules I/Os to specific IO pads, so its
> > not possible to make post P&R timing analysis for such (internally
> > used) modules.
>
> > The post synthesis timing is unrealistic, so how can I get a timing
> > estimation including wire delay for dedicated modules?
>
> > Any ideas?
>
> If the problem is that you don't have enough pins on the device, you
> could make sure all the I/O are registered, instruct the synthesizer not
> to add IOB pads, and put syn_keep or syn_preserve (or whatever) HDL
> directives on the I/O registers to make sure they don't get pruned.
> Then you could have a static timing analysis even though no pins are
> connected. =A0You won't be able to easily use this for a simulation, sinc=
e
> none of the I/Os will come out to top-level ports. =A0-Kevin

No, just turn all those external registers into a parallel/serial
shift register, and only output the serial output.

Reverse for the input: serial/parallel shift register, and the only
chip-level input is the serial input.

A clock, input and output pin; should fit in anything.

Andy

Article: 135404
Subject: Re: Sending UDP packets over Ethernet
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 30 Sep 2008 21:58:45 -0800
Links: << >>  << T >>  << A >>
Vernon Schryver wrote:
(snip)

> I think ICMP Source has been deprecated for more than 20 years.  See
> http://www.google.com/search?q=icmp+source+quench+deprecated

Is it that long ago?

I remember trying to ftp a new version of NCSA Telnet to a PC,
(all the way from NCSA), the PC sending out source quench as
fast as it could, as its buffers kept overrunning.  That would
have been a little less than 20 years ago.

Many early PC ethernet cards had small buffers.

-- glen


Article: 135405
Subject: Re: OFDM band switch ...
From: "Kappasm" <_NOSPAM_78kappa78_NO_SPAM@virgilio.it>
Date: Wed, 1 Oct 2008 09:04:58 +0200
Links: << >>  << T >>  << A >>
Thanks Jerzy Gbur,

> I'm sorry. You can't maintain  a standard that way,
> I thougt you are building own system, undependly of standards.
> You have to switch clock.

I imagined that it was not possible ...

Kappa. 



Article: 135406
Subject: Re: Interfacing DDR RAM
From: Rob <BertyBooster@googlemail.com>
Date: Wed, 1 Oct 2008 01:05:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 30, 11:38=A0am, "msfaroo...@gmail.com" <msfaroo...@gmail.com>
wrote:
> Hi,
>
> I am using Virtex - 2pro Board of Xilinx, I am actually getting an
> image from expansion connectors and then saving it in the DDR RAM as
> my project. I am new to FPGAs and EDK v10.1 and have no information
> about how to interface the. I have read tutorials from Xilinx but none
> of them give any info about interfacing with Memory devices and
> expansion connectors.
>
> Moreover, i also wana save and retrieve data from FLASH CARD. I know
> that XilFATfs is a library used for this but i dont know how to use
> it...
>
> please provide me some tutorials and give me some links about how to
> do it...i would be very very thankful to u all...
>
> mail me at msfar...@gmail.com
>
> Regards,
> Saad

DDR interfaces on V2Pro devices is tricky, although do-able.
Unfortunately it looks as though Xilinx have stopped supporting this.

www.xilinx.com/memory no longer mentions the V2.

How fast are you hoping to run the memory? Is it possible to use the
Virtex-4 or Virtex-5 instead?

Rob

Article: 135407
Subject: Re: Difference between PLD and General purpose CPU`
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Wed, 1 Oct 2008 02:17:24 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 30 Sep., 22:52, cs_post...@hotmail.com wrote:
> On Sep 29, 5:51 am, Kolja Sulimma <ksuli...@googlemail.com> wrote:

> From the perspective you wrote, yes.... but don't forget that
> an FPGA can also be configured to implement a general purpose
> processor,

Yes. And a CPU can emulate the FPGA behaviour.
Oh, and both at the same time: Think UltrController. A CPU implemented
on an FPGA replacing hardware.

Kolja Sulimma

Article: 135408
Subject: Re: reasonable timing analysis without mapping design to IO
From: Heiner Litz <heinerlitz@googlemail.com>
Date: Wed, 1 Oct 2008 03:58:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
thanks @all

I have already worked with with wrapper files, however found it too
time consuming to handle all the inputs/outputs.

I will try a wrapper with only clk/res as IO and then use the KEEP
directive.

heiner

On Oct 1, 1:25=A0am, Andy <jonesa...@comcast.net> wrote:
> On Sep 30, 2:27=A0pm, Kevin Neilson
>
>
>
> <kevin_neil...@removethiscomcast.net> wrote:
> > Heiner Litz wrote:
> > > Hi,
>
> > > I want to perform reasonable post place&route timing analysis for som=
e
> > > RTL modules. The modules have a higher pin count as the FPGA itself.
> > > ISE always tries to map the modules I/Os to specific IO pads, so its
> > > not possible to make post P&R timing analysis for such (internally
> > > used) modules.
>
> > > The post synthesis timing is unrealistic, so how can I get a timing
> > > estimation including wire delay for dedicated modules?
>
> > > Any ideas?
>
> > If the problem is that you don't have enough pins on the device, you
> > could make sure all the I/O are registered, instruct the synthesizer no=
t
> > to add IOB pads, and put syn_keep or syn_preserve (or whatever) HDL
> > directives on the I/O registers to make sure they don't get pruned.
> > Then you could have a static timing analysis even though no pins are
> > connected. =A0You won't be able to easily use this for a simulation, si=
nce
> > none of the I/Os will come out to top-level ports. =A0-Kevin
>
> No, just turn all those external registers into a parallel/serial
> shift register, and only output the serial output.
>
> Reverse for the input: serial/parallel shift register, and the only
> chip-level input is the serial input.
>
> A clock, input and output pin; should fit in anything.
>
> Andy


Article: 135409
Subject: Re: $99 XMOS Dev kit
From: James Harris <james.harris.1@googlemail.com>
Date: Wed, 1 Oct 2008 05:06:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 30 Sep, 09:51, Leon <leon...@btinternet.com> wrote:
> XMOS has just announced a $99 dev kit for their XC-1 device. I've put
> my name down for one:
>
> https://products.xmos.com/
>
> I used to work with transputers, it's nice to see that the concept has
> been resurrected.

Thanks for posting this. I may try then out too time permitting.

The original concept was awesome. Hope David May et al have the
business model right this time. For one thing the new devices seem far
more accessible. A four-core CPU, development board and software for
$99 is a good price.

I have read some of the documentation. The new device looks similar to
the old one but there are some intriguing differences.

Did you not want to post on comp.sys.transputer?

--
James

Article: 135410
Subject: Re: $99 XMOS Dev kit
From: bastian42@yahoo.com (42Bastian Schick)
Date: Wed, 01 Oct 2008 12:27:49 GMT
Links: << >>  << T >>  << A >>
On Wed, 1 Oct 2008 05:06:51 -0700 (PDT), James Harris
<james.harris.1@googlemail.com> wrote:

>On 30 Sep, 09:51, Leon <leon...@btinternet.com> wrote:
>> XMOS has just announced a $99 dev kit for their XC-1 device. I've put
>> my name down for one:
>>
>> https://products.xmos.com/
>>
>> I used to work with transputers, it's nice to see that the concept has
>> been resurrected.
>
>Thanks for posting this. I may try then out too time permitting.
>
>The original concept was awesome. Hope David May et al have the
>business model right this time. For one thing the new devices seem far
>more accessible. A four-core CPU, development board and software for
>$99 is a good price.

This time, they seem to offer free development enviroment and core
seems to me more main-stream like, which ease fast learning.

(Also I guess a lot of people will struggle with the threading :-)

I'm keen on to port my company's RTOS :-)

>I have read some of the documentation. The new device looks similar to
>the old one but there are some intriguing differences.

Yes, no negative addressess (AFAICS).


-- 
42Bastian
Do not email to bastian42@yahoo.com, it's a spam-only account :-)
Use <same-name>@monlynx.de instead !

Article: 135411
Subject: Post-synthesis simulation
From: Alfreeeeed <Alfredo.Taddei@gmail.com>
Date: Wed, 1 Oct 2008 06:23:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
I need suggestions of which software should I use to simulate the
hardware I synthesized. I had no luck using the ISE 9.2 post-synthesis
simulation because for some reason it wont decode some piece of VHDL
code where I have fixed_pkg signals on my testbench.

Also I would like to know if you use SPICE models for simulating the
FPGA board. I know altium designer simulates FPGA systems but I
believe they do a VHDL simulation. Also I find hard to find SPICE
models for ADC and DAC.

Is there any tool you use?


Thanks a lot

Article: 135412
Subject: Re: Post-synthesis simulation
From: Mike Treseler <mtreseler@gmail.com>
Date: Wed, 01 Oct 2008 06:46:39 -0700
Links: << >>  << T >>  << A >>
Alfreeeeed wrote:
> I need suggestions of which software should I use to simulate the
> hardware I synthesized. I had no luck using the ISE 9.2 post-synthesis
> simulation because for some reason it wont decode some piece of VHDL
> code where I have fixed_pkg signals on my testbench.

I simulate the code before I synthesize it.
I use modelsim.

   -- Mike Treseler

Article: 135413
Subject: Re: $99 XMOS Dev kit
From: Leon <leon355@btinternet.com>
Date: Wed, 1 Oct 2008 07:29:56 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 1 Oct, 13:27, bastia...@yahoo.com (42Bastian Schick) wrote:
> On Wed, 1 Oct 2008 05:06:51 -0700 (PDT), James Harris
>
>
>
> <james.harri...@googlemail.com> wrote:
> >On 30 Sep, 09:51, Leon <leon...@btinternet.com> wrote:
> >> XMOS has just announced a $99 dev kit for their XC-1 device. I've put
> >> my name down for one:
>
> >>https://products.xmos.com/
>
> >> I used to work with transputers, it's nice to see that the concept has
> >> been resurrected.
>
> >Thanks for posting this. I may try then out too time permitting.
>
> >The original concept was awesome. Hope David May et al have the
> >business model right this time. For one thing the new devices seem far
> >more accessible. A four-core CPU, development board and software for
> >$99 is a good price.
>
> This time, they seem to offer free development enviroment and core
> seems to me more main-stream like, which ease fast learning.
>
> (Also I guess a lot of people will struggle with the threading :-)
>
> I'm keen on to port my company's RTOS :-)
>
> >I have read some of the documentation. The new device looks similar to
> >the old one but there are some intriguing differences.
>
> Yes, no negative addressess (AFAICS).
>
> --
> 42Bastian
> Do not email to bastia...@yahoo.com, it's a spam-only account :-)
> Use <same-name>@monlynx.de instead !

You have to buy the tools, but you can use them on-line for free. I've
tried the system and it works fairly well. They are working on an open
source set of tools.

I've booked for the London seminar next month, participants get a dev
kit. I might as well get the other one I've reserved, as well. They
are good value.

I have a contact at XMOS, he told me yesterday that they already have
some design wins, even though the chip isn't in full production yet.
It's a very friendly company, like Inmos used to be.

Leon

Article: 135414
Subject: Re: Interfacing DDR RAM
From: Gabor <gabor@alacron.com>
Date: Wed, 1 Oct 2008 08:06:54 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 1, 4:05=A0am, Rob <BertyBoos...@googlemail.com> wrote:
> On Sep 30, 11:38=A0am, "msfaroo...@gmail.com" <msfaroo...@gmail.com>
> wrote:
>
>
>
> > Hi,
>
> > I am using Virtex - 2pro Board of Xilinx, I am actually getting an
> > image from expansion connectors and then saving it in the DDR RAM as
> > my project. I am new to FPGAs and EDK v10.1 and have no information
> > about how to interface the. I have read tutorials from Xilinx but none
> > of them give any info about interfacing with Memory devices and
> > expansion connectors.
>
> > Moreover, i also wana save and retrieve data from FLASH CARD. I know
> > that XilFATfs is a library used for this but i dont know how to use
> > it...
>
> > please provide me some tutorials and give me some links about how to
> > do it...i would be very very thankful to u all...
>
> > mail me at msfar...@gmail.com
>
> > Regards,
> > Saad
>
> DDR interfaces on V2Pro devices is tricky, although do-able.
> Unfortunately it looks as though Xilinx have stopped supporting this.
>
> www.xilinx.com/memoryno longer mentions the V2.
>
> How fast are you hoping to run the memory? Is it possible to use the
> Virtex-4 or Virtex-5 instead?
>
> Rob

You may also want to use an older version of EDK that supports the
V2 PRO if you don't want to update the hardware.

Article: 135415
Subject: Re: Post-synthesis simulation
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Wed, 01 Oct 2008 09:13:38 -0600
Links: << >>  << T >>  << A >>
Alfreeeeed wrote:
> I need suggestions of which software should I use to simulate the
> hardware I synthesized. I had no luck using the ISE 9.2 post-synthesis
> simulation because for some reason it wont decode some piece of VHDL
> code where I have fixed_pkg signals on my testbench.
> 
> Also I would like to know if you use SPICE models for simulating the
> FPGA board. I know altium designer simulates FPGA systems but I
> believe they do a VHDL simulation. Also I find hard to find SPICE
> models for ADC and DAC.
> 
> Is there any tool you use?
> 
> 
> Thanks a lot
Modelsim has great language support and will surely work.  If you update 
to ISE 10.1, you might find that ISIM will support the fixed-point 
package, as it has a new parser.  -Kevin

Article: 135416
Subject: Re: Problem with mpmc(4.02.a) simulation -- DDR never initializes
From: Gabor <gabor@alacron.com>
Date: Wed, 1 Oct 2008 08:14:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 30, 4:53=A0am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Mon, 29 Sep 2008 17:14:57 -0700 (PDT), rao <rao...@gmail.com> wrote:
> >On Sep 29, 4:22=A0pm, Brian Drummond <brian_drumm...@btconnect.com>
> >wrote:
> >> On Mon, 29 Sep 2008 14:17:50 -0700 (PDT), rao <rao...@gmail.com> wrote=
:
> >> >Hi,
>
> >> > =A0 When I tried to probe I found out that the
> >> >"MPMC_InitDone"
> >> > =A0stayed low for a long time.
>
> >> What is "a long time" in this context?
>
> >> Remember that a full initialisation sequence for DDR memory is suppose=
d
> >> to take slightly over 200 us. Which is quite a long time in a simulato=
r.
>
> >> How long is your simulation?
>
> >> - Brian
>
> >Hi Brian,
> > =A0Thanks for the tip. I caught this init_done at almost 580us.
>
> > =A0I was expecting very short init_done as I was setting
> > =A0"PARAMETER C_SKIP_SIM_INIT_DELAY =3D 1".
>
> > You saved lot of time as I was thinking of ripping the design
> > =A0to have only mpmc for the debug.
>
> To be honest, 580 us would surprise me too, but I don't know the
> internal details of MPMC. If it needs some intervention from the host
> (PPC or Microblaze), that would explain it.
>
> I would also double-check what is happening with C_SKIP_SIM_INIT_DELAY.
> Does initialisation take another 200 us without it?
>
> Anyway I am glad the simulation is basically working.
>
> - Brian

I have seen similar timing with MIG 2.2 and DDR 2 memory attached to a
Virtex 5.

It seems that the controller does a lot of calibration cycles to the
DRAM.  I don't
think that the 200 uS startup delay was included as I also set the
appropriate
bit to skip it during simulation.  If you use the Micron models for
simulation
you can see all of the cycles being performed in the simulation
transcript.
These tend to be reads and writes (mostly reads) and the data flips
between
all zeroes and all ones (looks like calibration).

You will also see that the first access to the Mode register of the
DRAMs
comes well before 200 uS indicating that the warm-up delay was indeed
skipped.  I don't know how to work around this without either finding
a
smarter DDR memory core or getting a better simulator (or license)
to allow reasonable simulation run times.

Regards,
Gabor

Article: 135417
Subject: Re: $99 XMOS Dev kit
From: "Anthony Fremont" <nobody@noplace.net>
Date: Wed, 1 Oct 2008 10:16:58 -0500
Links: << >>  << T >>  << A >>
Leon wrote:
> XMOS has just announced a $99 dev kit for their XC-1 device. I've put
> my name down for one:
>
> https://products.xmos.com/
>
> I used to work with transputers, it's nice to see that the concept has
> been resurrected.

Looks cool, but I tried to look at the tutorial and it wanted me to register 
first.  :-(  Ok, so I tried to register and the page had no button to press 
to submit the form.  :-(    The tutorial page I could see was only visible 
when I selected all the text on the page with CTRL-A, else it looked like an 
empty page.  I'm using IE6 and maybe that's part of the problem; XMOS needs 
to fix it though. 



Article: 135418
Subject: Asynchronous delay report shows delays longer that clock period - ok?
From: Dave <doomeddave@yahoo.co.uk>
Date: Wed, 1 Oct 2008 08:56:30 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi group,

The asynchronous delay report of my ISE 9.2.04i project shows the Max
Delay of a reset net (a RocketIO reset) to be 14.632 ns when the clock
is 125MHz (8 ns).

 The 20 worst nets by delay are:
+-----------------+-----------+
| Max Delay       | Netname   |
+-----------------+-----------+
  14.632            fpga_a/irst_rocketio_usrclk_pl<2>
   7.299            fpga_a/bus_data_from_ppc_d<52>
   7.298            fpga_a/bus_data_from_ppc_d<23>
   7.251            fpga_a/bus_data_from_ppc_d<42>
etc...

The reset is set asynchronously, and deasserted synchronously with a 3-
stage shift register.  All timing constraints are being met.

Also, there are other nets in the body of the report listed as having
delays greater than 8 ns for another clock (also 125MHz) even though
everything is synchronous.   Interestingly, they are not listed in the
20 worst nets which leads me to believe they are not a problem.  Am I
correct?

Is there any way that it is ok for these delays (14.632 ns and the non-
top-20 8.x ns) to be greater than the clock period?  Or am I
dreaming?  Perhaps the RocketIO reset is used asynchronously and the
tools take care of this?

Many thanks for your time,
Dave

Article: 135419
Subject: Re: Asynchronous delay report shows delays longer that clock period
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Wed, 01 Oct 2008 10:00:51 -0700
Links: << >>  << T >>  << A >>
Dave wrote:
> Hi group,
> 
> The asynchronous delay report of my ISE 9.2.04i project shows the Max
> Delay of a reset net (a RocketIO reset) to be 14.632 ns when the clock
> is 125MHz (8 ns).
> 
>  The 20 worst nets by delay are:
> +-----------------+-----------+
> | Max Delay       | Netname   |
> +-----------------+-----------+
>   14.632            fpga_a/irst_rocketio_usrclk_pl<2>
>    7.299            fpga_a/bus_data_from_ppc_d<52>
>    7.298            fpga_a/bus_data_from_ppc_d<23>
>    7.251            fpga_a/bus_data_from_ppc_d<42>
> etc...
> 
> The reset is set asynchronously, and deasserted synchronously with a 3-
> stage shift register.  All timing constraints are being met.
> 
> Also, there are other nets in the body of the report listed as having
> delays greater than 8 ns for another clock (also 125MHz) even though
> everything is synchronous.   Interestingly, they are not listed in the
> 20 worst nets which leads me to believe they are not a problem.  Am I
> correct?
> 
> Is there any way that it is ok for these delays (14.632 ns and the non-
> top-20 8.x ns) to be greater than the clock period?  Or am I
> dreaming?  Perhaps the RocketIO reset is used asynchronously and the
> tools take care of this?
> 

If your reset is released on different registers in different clock 
cycles that has a high probability of creating a problem as parts of 
your design start operating and other parts are still held in reset.

Ed McGettigan
--
Xilinx Inc.

Article: 135420
Subject: Re: $99 XMOS Dev kit
From: Leon <leon355@btinternet.com>
Date: Wed, 1 Oct 2008 10:38:12 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 1 Oct, 16:16, "Anthony Fremont" <nob...@noplace.net> wrote:
> Leon wrote:
> > XMOS has just announced a $99 dev kit for their XC-1 device. I've put
> > my name down for one:
>
> >https://products.xmos.com/
>
> > I used to work with transputers, it's nice to see that the concept has
> > been resurrected.
>
> Looks cool, but I tried to look at the tutorial and it wanted me to regis=
ter
> first. =A0:-( =A0Ok, so I tried to register and the page had no button to=
 press
> to submit the form. =A0:-( =A0 =A0The tutorial page I could see was only =
visible
> when I selected all the text on the page with CTRL-A, else it looked like=
 an
> empty page. =A0I'm using IE6 and maybe that's part of the problem; XMOS n=
eeds
> to fix it though.

They are having lots of problems with their web site. I was able to
register OK with Firefox, but didn't get my password, although the
message said it was being sent. I used their Support facility, and
they emailed the password manually to me.

They now have schematics and design files for the XC-1 board
available:

https://support.xmos.com/published/xc1-schematics

Leon


Leon

Article: 135421
Subject: Gee Thanks Altera, I really enjoy having a break waiting on your
From: cs_posting@hotmail.com
Date: Wed, 1 Oct 2008 10:44:50 -0700 (PDT)
Links: << >>  << T >>  << A >>
Project behind schedule... but Quartus decides that today is the day
to demand a new license file.

Which the server has promised but not yet mailed.

Don't you just love control-freak software?

Article: 135422
Subject: Re: $99 XMOS Dev kit
From: Leon <leon355@btinternet.com>
Date: Wed, 1 Oct 2008 10:58:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 1 Oct, 18:38, Leon <leon...@btinternet.com> wrote:
> On 1 Oct, 16:16, "Anthony Fremont" <nob...@noplace.net> wrote:
>
> > Leon wrote:
> > > XMOS has just announced a $99 dev kit for their XC-1 device. I've put
> > > my name down for one:
>
> > >https://products.xmos.com/
>
> > > I used to work with transputers, it's nice to see that the concept ha=
s
> > > been resurrected.
>
> > Looks cool, but I tried to look at the tutorial and it wanted me to reg=
ister
> > first. =A0:-( =A0Ok, so I tried to register and the page had no button =
to press
> > to submit the form. =A0:-( =A0 =A0The tutorial page I could see was onl=
y visible
> > when I selected all the text on the page with CTRL-A, else it looked li=
ke an
> > empty page. =A0I'm using IE6 and maybe that's part of the problem; XMOS=
 needs
> > to fix it though.
>
> They are having lots of problems with their web site. I was able to
> register OK with Firefox, but didn't get my password, although the
> message said it was being sent. I used their Support facility, and
> they emailed the password manually to me.
>
> They now have schematics and design files for the XC-1 board
> available:
>
> https://support.xmos.com/published/xc1-schematics
>
> Leon
>
> Leon

I just had an email from my contact at XMOS and mentioned your
problem.

Leon

Article: 135423
Subject: Re: if data moves faster faster than the Clock....
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Wed, 1 Oct 2008 11:43:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 30 Sep., 15:04, "RCIngham" <robert.ing...@gmail.com> wrote:

> If the clock is not synchronised to the data, the clock frequency must be
> more than twice the maximum data rate.http://www.google.com/search?hl=en&q=nyquist+sampling+theory

The first link in that search states that theorem as:
"If a function x(t) contains no frequencies higher than B cps[2], it
is completely determined by giving its ordinates at a series of points
spaced 1/(2B) seconds apart."

This means, that the criterion you gave is suficient, but not
necessary....

Also note that the data rate is often defined with a factor of 2 with
respect to the frequency. Eg. A 1gbps signal has no frequency above
500MHz an can be directly sampled with a 1gbps clock. This is the
reason why DDR interfaces exist: To match the frequencies of the data
and clock lines.

Kolja Sulimma

Article: 135424
Subject: Xilinx device not listed
From: FP <FPGA.unknown@gmail.com>
Date: Wed, 1 Oct 2008 13:32:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello,

I have a quick question. I dont see Xilinx Virtex -5 sx95t device in
the list of devices in Xilinx ISE and CoreGen. How do I fix this
issue? I have unistalled and reinstalled ISE.

Your comments would be appreciated.



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