Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
faza wrote: > Can you spell "surface acoustic wave"? > That was the maximum cutoff frequency support i am expecting to > get ....as my FIR filter is generic it should support from low to high > frequency > That means you must process ten samples on each clock cycle. Do you > know how to do that? > my design accepts 1 sample/clockcycle > but also you must generate ten output samples on every clock. > current design takes number of taps specified+2 clock cycles to > generate o/p for each sample.can u pls suggest for the current design > wat should be the Fclk i should set to achieve 256 taps and 1GS/s,Is > it possible?.And how u relate Fclk with Fs and Fc?as those Fs and Fc > are constraints to generate coefficients why we have to consider in > hardware implementation?How to decide Fclk?since the maximum clock > rate depends on the logic and routing delay of the design... I believe the only way it to try it. There are tradeoffs between throughput and logic that can only be done trying different designs. Especially as routing delay is likely very important. The exact number of pipeline stages depends on routing delay, logic levels, etc. -- glenArticle: 132851
On Jun 9, 3:08 pm, Kolja Sulimma <ksuli...@googlemail.com> wrote: > The V4 is thant the V5 older, so it is only natural that there are > more published designs for it. > The EMIF is a rather generic bus interface, very similar to dozens of > other CPU or SRAM interfaces. > There is nothing specific about it that affects FPGA choice. You > probably can use V4 HDL code for > an EMIF interface without modifications in an V5. > > Also: If you can't code the interface yourself you probably should not > start this project. The EMIF > interface is not more complicated than what you would use internally > to interface to the components > of your design. Using existing code therefore provides next to no > abstraction. > > Did you see XAPP573? > > The circuits to interface to a FIFO inside the FPGA are not much more > than half a dozen gates. > > Kolja Sulimma > > On 9 Jun., 11:24, techG <giuliopul...@gmail.com> wrote: > > > Hi all, > > I'm working on a realtime application that requires to elaborate a > > digital video stream 25fps. Algorithms are very time consuming and an > > hardware parallel solution can help to satisfy time constraints. > > > Finally I decided for a mixed SW and HW that consists in a TI DSP and > > a Virtex-5 connected togheter on EMIF. > > > Initially I choosed a Virtex-5SX, because it has a large number of DSP > > blocks and a good number of logic cells (usefull for parallel hardware > > implementations), but on the net I saw that people tend to use > > Virtex-4FX as co-processor for TI DSP. I suppose that this choice is > > strictly related to the presence of an hard core PowerPC on > > Virtex-4FX, but I'm not sure. > > > In addition I didn't found any reference design for EMIF interface in > > Virtex-5 (there are only for Virtex-4 or Virtex-II). Could be this a > > good reason to choose a Virtex-4 instead of Virtex-5? Hi, I think that the interface speed of EMIF can be defined based on the distance between the processor and FPGA chip. While attempting to capture 30-Frames per second from Camera link interface, I interfaced TI- C-64x processor with XC2V1000 FPGA via 64-bit asynchronous EMIF interface at 133Mhz (internal clock) with processor setup and strobe set to one cycle when the physical distance between the chips was about one inch; and the same interface slowed by approximately five times when the distance increased to two inches. Important thing is to avoid setup and hold uncertainties and sample data at right time. Use DCMs and phase shifted clocks to sample at right time and the only limiting factor in the speed of the interface was the speed of block RAM that could not run at a speed above 120MHz in Virtex-2. 30-FPS can easily be done in Vitex2/ Spartan series FPGAs, I think virtex-4/5 would allow much more than that. Hope this helps Regards /MHArticle: 132852
On Jun 8, 11:22 pm, "Bill Ngo" <bill....@sympatico.ca> wrote: > I am having difficulties in trying to deskew the Clock on a synchronous > local bus interface between a Virtex4 FPGA and a PowerPC chip. > > The instantiation port map of a DCM to provide 0 phase-shift between the > external LCLK_IN and the internal CLK is shown below. > > --------------------- > port map ( > CLK0 => CLK, -- 0 degree DCM CLK ouptput > CLK180 => open, -- 180 degree DCM CLK output > CLK270 => open, -- 270 degree DCM CLK output > CLK2X => open, -- 2X DCM CLK output > CLK2X180 => open, -- 2X, 180 degree DCM CLK out > CLK90 => open, -- 90 degree DCM CLK output > CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) > CLKFX => open, -- DCM CLK synthesis out (M/D) > CLKFX180 => open, -- 180 degree CLK synthesis out > LOCKED => open, -- DCM LOCK status output > CLKFB => CLK, -- DCM clock feedback > CLKIN => LCLK_IN, -- Clock input (from IBUFG, BUFG or DCM) > RST => RESET -- DCM asynchronous reset input > ); > --------------------- > > The timing constraint is shown below; I believe that the OFFSET constraints > should be effective since the phase-shift, 0 in this case, due to the DCM on > LCLK_IN, is accounted for by the PAR tool. > --------------------- > NET "LCLK_IN" TNM_NET = LCLK_IN; > TIMESPEC TS_LCLK_IN = PERIOD "LCLK_IN" 10 ns HIGH 50%; > OFFSET = IN 8 ns BEFORE "LCLK_IN"; > OFFSET = OUT 7 ns AFTER "LCLK_IN"; > --------------------- > > A portion of the timing report (.twr) is shown below: > Note the Clock Path Delay of 4.979ns which the DCM usage has failed to > eliminate in this attempt. I was expecting that the delay would be 0ns or > very close to 0ns. > > --------------------- > Slack: -5.472ns (requirement - (clock arrival + clock path > + data path + uncertainty)) > Source: READY_CARRIER (FF) > Destination: LAD<30> (PAD) > Source Clock: CLK rising at 0.000ns > Requirement: 7.000ns > Data Path Delay: 7.313ns (Levels of Logic = 3) > Clock Path Delay: 4.979ns (Levels of Logic = 3) > Clock Uncertainty: 0.180ns > : > : > Maximum Clock Path: LCLK_IN to READY_CARRIER > Location Delay type Delay(ns) Physical Resource > Logical Resource(s) > ------------------------------------------------- ------------------- > D14.I Tiopi 0.963 LCLK_IN > LCLK_IN > LCLK_IN_IBUFG > DCM_ADV_X0Y3.CLKIN net (fanout=1) 1.260 LCLK_IN_IBUFG > DCM_ADV_X0Y3.CLK0 Tdmcko_CLK -2.213 DCM_BASE_inst > DCM_BASE_inst > BUFGCTRL_X0Y23.I0 net (fanout=3) 1.504 CLK1 > BUFGCTRL_X0Y23.O Tbgcko_O 0.900 CLK_BUFG > CLK_BUFG > SLICE_X52Y103.CLK net (fanout=123) 2.565 CLK > ------------------------------------------------- --------------------------- > Total 4.979ns (-0.350ns logic, > 5.329ns route) > --------------------- > > Can anyone shed light on this problem? > > Bill Ngo If you want to remove the buffer delay, you need to route the output of the BUFG back to the CLKFB input of the DCM. You have the CLK0 output routed directly (internal feedback) which only removes delay to the CLK0 output itself before the BUFG. HTH, GaborArticle: 132853
faza wrote: <snip> > In general for N=256 , > My design will take (256+2) *256=66048 clock cycles <snip> Suppose your task is to generate the sum of 8 numbers rather than something as complex as an FIR. How many clock cycles will it take to add these 8 numbers? The answer can be one. FPGAs can perform operations in parallel during any one clock. These FPGAs are not serial processors. The way to design a high sample-rate, 8-operand adder would be to pipeline the operations. You have to read up on what pipelining means in digital design. This is - again - an absolutely fundamental concept that you haven't grasped before taking on a design. You have no chance of processing data at 600 MHz even if the FPGA is capable of 600 MHz operation because you do not understand the fundamentals of hardware design, ,uch less the nuances. I suggest once again - stop your pursuit. As an alternative, PLEASE pursue some local help from educators or professionals that can help take you by the hand and START you down the path of hardware design. You are trying to accomplish something WAY beyond your capabilities and you are NOT doing your homework with respect to your needs. Matlab is fun to play with but it gives you no sense of what it takes to truly implement a design. Apologies to you and others for the tone - again - but you are not understanding that you have NO CHANCE of reaching your goals because you are not willing to pursue the fundamental research on your own to be ABLE to start a design with extreme goals. I would encourage people who work hard to get the fundamental understanding needed to pursue these kinds of designs. You are not one of those people. - John_HArticle: 132854
On Jun 7, 2:29 pm, Randy Yates <ya...@ieee.org> wrote: > rickman <gnu...@gmail.com> writes: > > On Jun 7, 12:13 am, Randy Yates <ya...@ieee.org> wrote: > >> rickman <gnu...@gmail.com> writes: > >> > [...] > >> > But if I want a laptop, I won't have much choice but to run Win XP > >> > (for the next few weeks) or Vista. I only wish I had a choice. > > >> You do. I have successfully installed Fedora 8 on an HP Pavillion > >> DV9620US. > > >> However one thing to be careful of in running linux on laptops is > >> Broadcom's stubborn refusal to open up their wireless card > >> specifications so that open source drivers can be developed. Translated: > >> don't buy a laptop with a Broadcom wireless card (or chipset) if you > >> want to run linux on it. Atheros I've heard is very good and supported > >> by madwifi.org. > > >> But, even though Broadcom is stubborn, I have still been successful at > >> getting the card to work on my home network. Unfortunately the reverse > >> engineered drivers (b43-fwcutter...) do not seem to support the Master > >> modes used in public hotspots. > > > I knew someone would mention Linux. Linux is still an alien platform > > to me and there is any amount of software that is not supported under > > it... or I should say that there is any amount of software that is > > only supported on specific versions of Linux. If I run Fedora 8, > > maybe vendor X gives me support and vendor Y doesn't. I run Redhat > > and vendor X gives me support and vendor Z doesn't... etc, etc, etc. > > > The reason that I still run windows at all is because for me, it is > > the only option. Currently Win2000 is the best that runs the minimum > > required set of software. If I want a laptop, my only choice > > currently is to buy a machine running XP which I can do for the next > > few weeks. After that there will be no choice on a new machine except > > for Vista. With a number of vendors not supporting that still, I will > > not have the option of buying a new laptop with an installed OS that > > runs the software I need. > > I have been able to operate just fine for 3 years without most of the > Microsoft-specific software. Most notably, OpenOffice replaces Microsoft > Office. And for those occasions that I do need a MS-based OS, such as > once a year to run TaxCut, or when I need to run TI Code Composer > Studio, I use Win2000 running in a virtual machine under a linux host. > I previously used VMWare and currently use VirtualBox for this. > > What software do you use that demands a MS OS? Various CAD/CAE tools. I am sure that it is possible to run most of them under WINE or something similar, but they are not supported that way. I am very happy with Win2000 and I see no need to switch to a *nix flavor. Even if I buy the *nix version of the various tools, they only support the version of *nix that they indicate. The CAE tools are pretty flaky compared to general software and I don't need the headache of trying to get support while running under an unsupported OS. My only problem is buying a laptop. You can't build one yourself and the vendors don't offer Win2K anymore. Next month even Dell says they will no longer offer XP. This is a double whammy because most of the tools are not supported under Vista yet AFAIK.Article: 132855
I am looking for a SDRAM controller for Xilinx Spartan3 device in Verilog. xapp 134 has one which targets virtex 2 devices. Xilinx MIG can be used for DDR and DDR2 SDRAMs. Can a DDR SDRAM controller be used to drive SDR SDRAM? What other options do I have?Article: 132856
On Jun 6, 11:46 pm, CBFalconer <cbfalco...@yahoo.com> wrote: > rickman wrote: > > moja...@mojaveg.lsan.mdsg-pacwest.com (Everett M. Greene) wrote: > > ... snip ... > > >> Who considers anything but the "latest and greatest" to be > >> outdated? This group is supposedly intelligent and familiar > >> enough with computing to make decisions about "upgrading". > >> If newer products don't offer anything in valued improvements, > >> ignore them. > > > You seem naive. I am very happy with Windows 2000 on my desktop > > computer. If I build another it will also run Windows 2000. But > > if I want a laptop, I won't have much choice but to run Win XP > > (for the next few weeks) or Vista. I only wish I had a choice. > > Seriously consider Linux, especially Ubuntu. You do have a > choice. A better choice. Only if I want to run programs without support. Most CAD/CAE tools are unsupported under *nix or only supported on a single flavor and version. The vendors don't even agree on the flavor and version supported. But there is also the issue of knowledge. I have *no* experience with *nix... well, no good experience. Some years ago I bought a $200 Walmart machine which came with Lindows, a version of Linux. It had a number of apps which were flaky and I didn't see much utility to it. I couldn't figure out how to do a lot of things and I ended up installing Win2000 over it. The company was also pretty poor about meeting the license requirements. I thought they had to make the sources available in the same manner that they distributed the binary. When I first asked them about it they feigned ignorance. After nagging they shipped me a hand copied CD. When I received an update there were no sources. This time I was told that they were available on the web site. Yes, they were there, but as individual files which had to be downloaded one at a time. I have just never had a positive experience with linux. I don't know how much time it would take, but I can't see spending the investment to convert and I seldom have the time to investigate. There is also the research I would have to do to figure out *which* version of Linux I would want. How can Linux be standard if there are so many versions and each software vendor only supports a few? So what exactly is better about Linux?Article: 132857
"readmemh" or "readmemb" in Verilog for initializing memories should only work in simulations and not for ASICs, but I've seen posts saying that XST can recognize readmemh and readmemb for FPGAs, just wondering whether it is true that readmem[b|h] is synthesisable for FPGAs or not?Article: 132858
Hai , U have not answered my following question.. so u mean to say eventhough i generate the filter coefficients before hand using FDA tool,i should set the Fclk by considering the sampling frequency and cutoff frequency for which i have generated the filter coefficients..am i correct?? regards, faza John_H wrote: > faza wrote: > <snip> > > In general for N=256 , > > My design will take (256+2) *256=66048 clock cycles > <snip> > > Suppose your task is to generate the sum of 8 numbers rather than > something as complex as an FIR. > > How many clock cycles will it take to add these 8 numbers? > > The answer can be one. > > FPGAs can perform operations in parallel during any one clock. These > FPGAs are not serial processors. > > The way to design a high sample-rate, 8-operand adder would be to > pipeline the operations. You have to read up on what pipelining means > in digital design. > > This is - again - an absolutely fundamental concept that you haven't > grasped before taking on a design. > > You have no chance of processing data at 600 MHz even if the FPGA is > capable of 600 MHz operation because you do not understand the > fundamentals of hardware design, ,uch less the nuances. > > I suggest once again - stop your pursuit. As an alternative, PLEASE > pursue some local help from educators or professionals that can help > take you by the hand and START you down the path of hardware design. > > You are trying to accomplish something WAY beyond your capabilities and > you are NOT doing your homework with respect to your needs. > > Matlab is fun to play with but it gives you no sense of what it takes to > truly implement a design. > > Apologies to you and others for the tone - again - but you are not > understanding that you have NO CHANCE of reaching your goals because you > are not willing to pursue the fundamental research on your own to be > ABLE to start a design with extreme goals. > > I would encourage people who work hard to get the fundamental > understanding needed to pursue these kinds of designs. You are not one > of those people. > > - John_HArticle: 132859
Hi,
I am trying to do the following on Microblaze. Here is the program
structure.
void main() {
Xuint32 countvalue;
enable_timer();
// do some stuff on Microblaze
... //some lines of code ....
countvalue = readback_timer();
disable_timer();
//send count value back to serial port
...
return1;
}
In short, I am trying to keep tab of how fast various sections of code
takes to run using a timer running on Microblaze.
when i do compile with some compiler optimization level set to -O1 or -
O2 or -O3, the compiler cleverly enables the timer at the WRONG place.
it enables the timer and then disables the timer again, giving me a
very short compute time. this is not what i want. :( since i want to
be able to accurately measure how long it takes for the code to
execute. I tried declaring countvalue as
volatile Xuint32 countvalue;
It doesn't quite work. Does anybody have an idea on how i could go
about solving this?
thanks for your patience; I have not much experience developing
embedded firmware.
Chris
Article: 132860faza wrote: > Hai , > > U have not answered my following question.. > > so u mean to say eventhough i generate the filter coefficients before > hand using FDA tool,i should set the Fclk by considering the > sampling > frequency and cutoff frequency for which i have generated the filter > coefficients..am i correct?? > > > regards, > faza The scope of the subject and the possible implementations are too large to answer your question. Since it *appears* from your posts that you want to use the FIR for real-time processing, the most straightforward implementation is a fully parallel FIR filter which takes in 1 sample per clock and performs a multitude of operations in parallel during each clock, delivering the filtered output many clocks after the last input sample is clocked into the circuit. The latency is a function of how the FIR is implemented and what level of pipelining is used to increase the possible process speed. The cutoff frequency is a function of your FIR. FIR filters with fewer taps have poorer characteristics in things like passband flatness, stopband attenuation, and the steepness of the cutoff than longer filters. ARE YOU FAMILIAR WITH THESE PARAMETERS? It seems that all you're thinking about is "cutoff" with no regard for what a filter really entails. You MUST do your homework - as in "basic research" - before you can take on this task. We cannot feed you piecemeal answers when it appears you don't have the fundamentals down.Article: 132861
rickman <gnuarm@gmail.com> writes: > On Jun 6, 11:46 pm, CBFalconer <cbfalco...@yahoo.com> wrote: >> rickman wrote: >> > moja...@mojaveg.lsan.mdsg-pacwest.com (Everett M. Greene) wrote: >> >> ... snip ... >> >> >> Who considers anything but the "latest and greatest" to be >> >> outdated? This group is supposedly intelligent and familiar >> >> enough with computing to make decisions about "upgrading". >> >> If newer products don't offer anything in valued improvements, >> >> ignore them. >> >> > You seem naive. I am very happy with Windows 2000 on my desktop >> > computer. If I build another it will also run Windows 2000. But >> > if I want a laptop, I won't have much choice but to run Win XP >> > (for the next few weeks) or Vista. I only wish I had a choice. >> >> Seriously consider Linux, especially Ubuntu. You do have a >> choice. A better choice. > > Only if I want to run programs without support. Most CAD/CAE tools > are unsupported under *nix or only supported on a single flavor and > version. The vendors don't even agree on the flavor and version > supported. I don't doubt that - I don't think Orcad runs on any linux platform. > But there is also the issue of knowledge. I have *no* experience with > *nix... well, no good experience. Some years ago I bought a $200 > Walmart machine which came with Lindows, a version of Linux. It had a > number of apps which were flaky and I didn't see much utility to it. > I couldn't figure out how to do a lot of things and I ended up > installing Win2000 over it. The company was also pretty poor about > meeting the license requirements. I thought they had to make the > sources available in the same manner that they distributed the > binary. When I first asked them about it they feigned ignorance. > After nagging they shipped me a hand copied CD. When I received an > update there were no sources. This time I was told that they were > available on the web site. Yes, they were there, but as individual > files which had to be downloaded one at a time. That was probably a bad way to experience linux. These days, for evaluation, you can install it (whatever flavor) in a virtual machine and play with it that way. The VM takes a piece of your hard drive (10G would be plenty), but in today's world that's largely negligible. > I have just never had a positive experience with linux. I don't know > how much time it would take, but I can't see spending the investment > to convert and I seldom have the time to investigate. There is also > the research I would have to do to figure out *which* version of Linux > I would want. How can Linux be standard if there are so many versions > and each software vendor only supports a few? Well, those are all valid reasons to stick with Windows. But that's not what you said; you said you didn't have an option. The truth is, you do have an option, but it doesn't seem very appealing to you. Also note that there are a set of open-source EDA tools available called gEDA - check then out. > So what exactly is better about Linux? 1. It's free. 2. It won't watch over your shoulder (Big Brother): a. You can watch whatever videos or audios you want whenever and make all the copies you'd ever want. b. No "phoning home" to tell the Corp. what your spending habits, eating habits, sex habits, surfing habits, etc. are. c. No checking to see if this is a valid installation. 3. It's built for global access. a. It is based on the X11 windows system, which means that you can run any application (X client) anywhere in the world from your desktop. b. It comes with ssh and ssh server out-of-the-box. That means that you can access (securely) any file on your system from any point on the internet. c. It's easy to install Apache (a web server), postgresql (a database server), subversion (version control software), and a myriad of other things and access these servers from anywhere there's an internet connection. 4. It's beautiful. There are several window managers that can be configured any way you want. I use Gnome. 5. It's fast. The newer linux distros, along with your video card's GL driver, makes fast work of graphics. 6. It's fun. It comes with a ton of utilities, games, programmer utilities, a Web server (THE web server - Apache), etc. out-of-the-box. 7. You only have to reboot once a month (if that). -- % Randy Yates % "So now it's getting late, %% Fuquay-Varina, NC % and those who hesitate %%% 919-577-9882 % got no one..." %%%% <yates@ieee.org> % 'Waterfall', *Face The Music*, ELO http://www.digitalsignallabs.comArticle: 132862
Wei Wang wrote: > "readmemh" or "readmemb" in Verilog for initializing memories should > only work in simulations and not for ASICs, but I've seen posts saying > that XST can recognize readmemh and readmemb for FPGAs, just wondering > whether it is true that readmem[b|h] is synthesisable for FPGAs or > not? Have a look in the XST User's Guide. It is not synthesisable, but supported to init the memory. Only constrain is that the file needs to have exactly the amount of entries as the memory has. Cheers, GuenterArticle: 132863
On Jun 9, 9:08 am, chrisde...@gmail.com wrote:
> Hi,
> I am trying to do the following on Microblaze. Here is the program
> structure.
>
> void main() {
> Xuint32 countvalue;
>
> enable_timer();
> // do some stuff on Microblaze
>
> ... //some lines of code ....
>
> countvalue = readback_timer();
> disable_timer();
>
> //send count value back to serial port
> ...
>
> return1;
> }
>
> In short, I am trying to keep tab of how fast various sections of code
> takes to run using a timer running on Microblaze.
>
> when i do compile with some compiler optimization level set to -O1 or -
> O2 or -O3, the compiler cleverly enables the timer at the WRONG place.
> it enables the timer and then disables the timer again, giving me a
> very short compute time. this is not what i want. :( since i want to
> be able to accurately measure how long it takes for the code to
> execute. I tried declaring countvalue as
>
> volatile Xuint32 countvalue;
>
> It doesn't quite work. Does anybody have an idea on how i could go
> about solving this?
>
> thanks for your patience; I have not much experience developing
> embedded firmware.
>
> Chris
Something you could try
Recode enable_timer to return a value (say zero) - use the return
value to initialize a variable (starting sum, whatever) in your "do
stuff" section, real close to the start.
Similar, re-code disable_timer to accept (and probably ignore) a
parameter. Pass the result of "do stuff" to disable_timer.
That should prevent the optimizer from moving the calls. At least, it
had better not move them very far.
Oh, and if it were me, I would disable (stop) the timer before reading
it, not the other way around.
Take a look at the assembler output to verify that you're getting what
you want.
G.
Article: 132864> If your FPGA clock frequency is the same as your Fs then it's > simple. Sorry, I mixed up the words ;) here's the correct one... You have a clock frequency Fclock. And a sample frequency Fsample. Suppose your impulse response length is N taps. If Fclock =3D N * Fsample this is simple. Every N periods of Fclock it receives a sample. Then, N times, it takes a coefficient, and multiplies it with the = appropriate sample of the input : sum of Coeff(n) * Input(T-n) for n in [0,1 ... N-1] So it takes N clocks to process a sample because you use 1 multiplier a= nd = you have N taps. Now if you use N multipliers you can process everything in one clock an= d = therefore use Fclock =3D Fsample. But you are going to use much more sli= ces = in your FPGA. And if you have Fclock =3D N * X * Fsample Then your filter is faster than what you need, but that is not a proble= m, = once an input sample is processed, it will just sit idle waiting for the= = next input sample. In this case you could process X channels instead of 1 channel still = using 1 multiplier, by using the time the silicon is idle to process the= = other channels. Get it ? > If you then clock this filter with a frequency of kFs, the cut off > frequency > will be kFc . Not necessarily ;) An impulse response is just a list of numbers. It does not have a cutof= f = frequency. If it is a filter all it can have is a cutoff frequency ratio= = which is a number without a Unit (no hertz, just a number), for instance= r = =3D 0.1 for a lowpass filter. Only when you say "the sample rate is Fs" then you can say "the cutoff = of = this impulse response when used on a signal of frequency Fs is r * Fs" o= r = 0.1 Fs in this case. If you change the Fs it will just scale. Now if your processing is not done in real time, say for instance you = sample a chunk of data at Fs then you store the data in a buffer then yo= u = stop sampling and you take the time to filter it, you can use any clock = = you want since it's not in real time anymore. > so u mean to say eventhough i generate the filter coefficients before > hand using FDA tool,i should set the Fclk by considering the sampling= > frequency and cutoff frequency for which i have generated the filter > coefficients..am i correct?? No, you should set the clock frequency so that it's practical for you. Say your Fsample is 1 MHz you have N =3D 10 taps in your filter for each sample you need 10 multiplications and 10 additions it takes a clock cycle to do a multiply + accumulate So you need a Fsample * N =3D 10 MHz clock at least. But if you have other stuff in the FPGA running at 50 MHz you can use 5= 0 = MHz instead. The filter will just sleep during 40 clock cycles then work for 10 cycl= es = then sleep again etc. > In that case how it is possible to fix fclk which can support a > maximum sampling frequency till 600Mhz? Well I have bad news for you lol. Since the multipliers in your FPGA don't reach that frequency you will = = need to use several multipliers and adders in parallel. For instance if you have 10 taps and 600 MHz you need 6 billion MACs/s = = and if your multipliers run at 100 MHz (for example) each provides 100 = million MAC/s so you're going to need 60 multipliers and a spaghetti = monster of logic. And since the FPGA fabric doesn't run at 600 MHz (unless you're rich) = you'll need to input several samples in parallel and add still more = spaghetti logic to coordinate all this stuff. What is the signal you want to filter ? Who chose the sample frequency ? Is it a REAL application which NEEDS that speed IN REAL TIME ? If it is= , = it is going to be very EXPENSIVE. What is it that you want to do ?Article: 132865
FP <FPGA.unknown@gmail.com> wrote: >I am looking for a SDRAM controller for Xilinx Spartan3 device in >Verilog. xapp 134 has one which targets virtex 2 devices. Xilinx MIG >can be used for DDR and DDR2 SDRAMs. Can a DDR SDRAM controller be >used to drive SDR SDRAM? Yes, with some minor modifications this should be possible. But beware, there are no usefull free DDR controllers available for the Spartan3 series. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 132866
rickman wrote: > I couldn't figure out how to do a lot of things and I ended up > installing Win2000 over it. > So what exactly is better about Linux? I second your opinion regarding Linux. It is a toy of students and enthusiasts who are enjoying the process of configuring the computer instead of getting the actual job done hard and fast. BTW, why do you prefer Win2k rather then XP? Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.comArticle: 132867
> I am looking for a SDRAM controller for Xilinx Spartan3 device in > Verilog. xapp 134 has one which targets virtex 2 devices. Xilinx MIG > can be used for DDR and DDR2 SDRAMs. Can a DDR SDRAM controller be > used to drive SDR SDRAM? > What other options do I have? I need this SDRAM controller too. There are some on OpenCores, but with gotchas.Article: 132868
> In short, I am trying to keep tab of how fast various sections of code= > takes to run using a timer running on Microblaze. I've done that before, like this : int timer_value =3D * (volatile int *) TIMED_REG_ADDRESS; .. do stuff.. timer_value =3D (* (volatile int *) TIMED_REG_ADDRESS) - timer_value; printf( "Elapsed cycles : %d", timer_value ) > volatile Xuint32 countvalue; It is the timer register which is incremented unbeknowst to gcc, not yo= ur = int variable. Therefore it is the pointer to the timer register you read which must b= e = declared (volatile int *), not the int variable (this is useless). I put the explicit code in the example above. You can use defines or = functions to make it prettier. Note also that this handles wraparound : instant 1 : you get 0xFFFFFFFF from timer instant 2 : you get 0x00000001 from timer (it wrapped) (int)0xFFFFFFFF =3D -1 (int)0x00000001 =3D 1 Difference : 1 - (-1) =3D 2 cycles. int arithmetic handles the wraparound nicely for you. Note that if you set the timer to wraparound at some random value it = won't work. = "volatile int x" is a contradiction so gcc optimized away which is the = = expected behaviour. However *(volatile *)address has a very specific meaning which is what = = you want. Accesses to volatiles create barriers that gcc instruction = reordering cannot skip so it will do what you want.Article: 132869
On Jun 6, 3:46 am, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> wrote: > In comp.arch.fpga, > > Thomas Stanka <usenet_nospam_va...@stanka-web.de> wrote: > > Only strange thing I see is lastval beeing updatet again at the > > falling edge of clock, but the code shown here should work right. > > Sorry about that, that was a mistake in the example, the update > should have been inside the "if rising_edge(clock) then". Take this example: sigA <= varB + varC; If it appears immediately before the clock's "end if" (after any possible assignments to the variables), then sigA is a register, and the addition is performed on the combinatorial references to the variables. If it appears after the clock's "end if", then the references to the variables are registered and the addition is performed and assigned combinatorially to sigA (without a register). The cycle-accurate behavior of both of these descriptions is identical, and so would that of the resulting implementations. The effects of combinatorial logic before or after the register may have other effects (glitches, etc.). However, since you have no operators in your variable expression, the two would be identical in implementation too. AndyArticle: 132870
Wei Wang wrote: > "readmemh" or "readmemb" in Verilog for initializing memories should > only work in simulations and not for ASICs, but I've seen posts saying > that XST can recognize readmemh and readmemb for FPGAs, just wondering > whether it is true that readmem[b|h] is synthesisable for FPGAs or > not? XST and Synplify both support $readmem for initializing RAMs/ROMs. -KevinArticle: 132871
On Jun 9, 1:43 pm, PFC <li...@peufeu.com> wrote: > "volatile int x" is a contradiction so gcc optimized away which is the > expected behaviour. How is it a contradiction? You can still get it's address and modify or examine it that way behind the compiler's back, so the compiler must assume that when you say it's volatile, you might mean it. Granted you want to be careful that you only do this during a time when the compiler is obligated to ensure that the variable exists, but that's not unreasonable within the scope, or when playing with a hardware-based debugger.Article: 132872
PFC wrote: > >> In short, I am trying to keep tab of how fast various sections of code >> takes to run using a timer running on Microblaze. > > I've done that before, like this : > > int timer_value = * (volatile int *) TIMED_REG_ADDRESS; > > .. do stuff.. > > timer_value = (* (volatile int *) TIMED_REG_ADDRESS) - timer_value; > > printf( "Elapsed cycles : %d", timer_value ) > >> volatile Xuint32 countvalue; > > It is the timer register which is incremented unbeknowst to gcc, not > your int variable. > Therefore it is the pointer to the timer register you read which > must be declared (volatile int *), not the int variable (this is useless). > > I put the explicit code in the example above. You can use defines or > functions to make it prettier. > > Note also that this handles wraparound : > > instant 1 : you get 0xFFFFFFFF from timer > instant 2 : you get 0x00000001 from timer (it wrapped) > > (int)0xFFFFFFFF = -1 > (int)0x00000001 = 1 > > Difference : 1 - (-1) = 2 cycles. > int arithmetic handles the wraparound nicely for you. > > Note that if you set the timer to wraparound at some random value it > won't work. > > "volatile int x" is a contradiction so gcc optimized away which is > the expected behaviour. > However *(volatile *)address has a very specific meaning which is > what you want. Accesses to volatiles create barriers that gcc > instruction reordering cannot skip so it will do what you want. This is a common misconception about volatile in C. The compiler cannot change volatile accesses with respect to other volatile accesses - but it can happily re-order non-volatile accesses around the volatile access. Thus it is perfectly allowed to do "...do stuff..." either before or after the two volatile reads of the timer. Even if you write something like : int timer_value = * (volatile int *) TIMED_REG_ADDRESS; volatile int result = doSomething(); timer_value = (* (volatile int *) TIMED_REG_ADDRESS) - timer_value; The compiler can call doSomething(), storing the result in a temporary register, then read TIMED_REG_ADDRESS, store the result in "result", then re-read TIMED_REG_ADDRESS - all without violating the volatile requirements. What's important is that you read the timer with a volatile access, then call doSomthing() in a way that requires a volatile access at the start and the end of the process, then re-read the timer with a volatile access at the end.Article: 132873
rickman wrote:
>
... snip ...
>
> I have just never had a positive experience with linux. I don't
> know how much time it would take, but I can't see spending the
> investment to convert and I seldom have the time to investigate.
> There is also the research I would have to do to figure out *which*
> version of Linux I would want. How can Linux be standard if there
> are so many versions and each software vendor only supports a few?
>
> So what exactly is better about Linux?
I think you will find that switching from Winders is much easier
now. Also, you have much less disturbance of your existing system
to simply try it out. If you get the free CD from Ubuntu.com you
will find you can install a working system without using your hard
disk at all (some penalties, obviously), or a dual booting system,
with no penalties except gobbling some disk space, or a complete
replacement. Just fill out the order and wait three or so weeks
for a CD delivery.
The unixy variations are largely in the GUI programs. The old
fashioned easy linkage of CLI programs remains available, largely
unchanged. Ubuntu 8.04 is a long term maintenance version (3
years). I am still running the previouss long term version (6.06).
Expect to invest one to two hours. Also see alt.os.linux.ubuntu.
--
[mail]: Chuck F (cbfalconer at maineline dot net)
[page]: <http://cbfalconer.home.att.net>
Try the download section.
** Posted from http://www.teranews.com **
Article: 132874Using verilog and ISE 10.1. I add a reg to modify the design's behaviour. It works and it works correctly. The change is intended to invert the carry logic for some op-codes. However synthesis , using XST , gives the following warning message. WARNING:Xst:646 - Signal <borrow> is assigned but never used. This unconnected signal will be trimmed during the optimization process. What I would like to do is to find out which lines are caing this warning and see if I have missed something or the synthesis tool has made a mistake. All sixteen op-codes assign something to borrow. Sometimes true, sometimes inverse and sometimes 0. I added a KEEP statement to the reg and of course everything was OK. When I added a KEEP statement to each line that assigned to the reg borrow I got the abover warning message. Is there any synthesis qualifiers which say presevre the nets in this line only? Thanks for any advice andy.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z