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Ambreen Ashfaq Afridi wrote: > I have to use the Trimode Ethernet MAC core for my FPGA project, which > will send and recieve data while connected to LAN though an Ethernet > cable. For that obviously some IP address should be assigned to the > FPGA, I couldn't find the part of code where this is happening ... Can > anyone help me identify that part of code where IP address assignment > is taking place? Usually that would be done in software outside the FPGA. In some cases you can assign a static address, but DHCP would be nice. Much easier to do in software in a simple processor. It only needs to be done once (get a long lease from DHCP). Another way is putting an entry into ARP on another host with your hosts MAC address as the destination. Then all you need to do is accept any data coming in. You can exchange the MAC and IP addresses before sending the data back, easiest for UDP. -- glenArticle: 132901
Hi, I was trying to compile uClinux image for microblaze. For doing so I followed the step by step process given in http://www.itee.uq.edu.au/~wu/downloads/uClinux_ready_Microblaze_design.pdf But, while doing 'make all' I get the following error - " make[3]: Entering directory `/home/saransh/project/uClinux-cvs/ uClinux-2.4.x/uClinux-dist/user/agetty' make[3]: warning: -jN forced in submake: disabling jobserver mode. ucfront-gcc mb-gcc -Wl,--fatal-warnings -Wl,-elf2flt -Wl,--fatal- warnings -Wl,-elf2flt -o agetty agetty.o /opt/xilinx/v10_1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze- xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld.real: agetty.gdb: Not enough room for program headers, try linking with -N /opt/xilinx/v10_1/EDK/gnu/microblaze/lin64/bin/../lib/gcc/microblaze- xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld.real: final link failed: Bad value collect2: ld returned 1 exit status make[3]: *** [agetty] Error 1 make[3]: Leaving directory `/home/saransh/project/uClinux-cvs/ uClinux-2.4.x/uClinux-dist/user/agetty' make[2]: *** [agetty] Error 2 make[2]: Leaving directory `/home/saransh/project/uClinux-cvs/ uClinux-2.4.x/uClinux-dist/user' make[1]: *** [all] Error 2 make[1]: Leaving directory `/home/saransh/project/uClinux-cvs/ uClinux-2.4.x/uClinux-dist/user' make: *** [subdirs] Error 1 " Can anyone please help me in this regard. SaranshArticle: 132902
TSIuser wrote:
> I was worried
> that the vendor's libs used weird (non-standard) Verilog modeling, and that
> it might not work 'out of the box' with non-Modelsim simulators.
> (My coworker told me this was a BIG problem with the whole Verilog
> scene in general, back when the original Verilog-XL was king.)
I have heard nothing but good reports about Aldec.
> ?!? If your synthesizeable-RTL only uses generic statements (i.e. infered
> FPGA-structures) , and not hand-instantiations, I can understand.
That's my style.
> But what about when you instantiate specific I/O-cells, or a DCM?
> Don't those have to come from the library?
Only if I need PLL or DCM over
a generic phase accumulator and then
only if I choose to use the vendor model.
> And let's not forget Xilinx's Smartmodels for the TEMAC, Microblaze,
> among other IP.
See page 8 of
www.synopsys.com/products/designware/docs/doc/smartmodel/manuals/relnotes.pdf
"FPGA SmartModel Obsolescence Notes
Effective December 1st 2003,
the Synopsys FPGA SmartModel simulation models that
are offered as part of the DesignWare Library will be obsolete. This
section documents the transition and technical support plans."
-- Mike Treseler
Article: 132903On 29 Mai, 08:56, Markus <n...@nowhere.org> wrote: > There was a similar discussion about device support on this list, for edk 9.2: > > http://groups.google.de/group/comp.arch.fpga/browse_frm/thread/d91828... > > I remember that VirtexII devices should be supported properly again in > version 10.1 which is not the case, obviously. > > If you want to hack your EDK, change the *.mpd file: add VirtexII to the > supported families and see what happens then. (And tell us) > > -Markus > > rmeiche schrieb: > > > Hi, > > > I'm trying to build a system for a XC2V6000 FPGA. The problem I have > > is that I have to implement a PLB. But the PLB shipped with the EDK > > 10.1 is the PLB_v46 which doesn't support the virtex II, only V2Pro > > and V4. > > > At the datasheets on the xilinx website I found that the PLB_v34 > > should support the V2 (see this link: http://www.xilinx.com/products/ipcenter/plb_v34.htm > > ). > > > But there exist two versions of the datasheet. One on the xilinx > > website and one at the pcore directory. I got the pcore from the EDK > > 8.2 which includes the PLB_v34 in version 1.01a. The datasheet says > > that this version only supports V2Pro and V4. > > > I just took that core and copied it to the pcore directory of my EDK > > 10.1 project and added it to the system. I ignored the warnings and > > started the build process but this was aborted with the reason that > > the Virtex2 isn't supported. > > > Does that mean that the datasheet on the xilinx website is wrong? Did > > I something wrong? > > > Has anyone tried to implement a PLB on a Virtex II system? > > > Thanks. Hello and sorry for my late answer. I tried it with "hacking" the mpd file and it works. I used the plb_v34 (version 1.02a) and the opb2plbbridge (version 1.00c). I only edited the "ARCH_SUPPORT_MAP".Article: 132904
I have successfully compiled some ISE's (version 6.x and 7.x) with
aldecs tools (riviera),
and made a Makefile (see below) for this, hope it helps. Haven't tried
later versions yet.
(I'm running this in a cygwin/XP environment.)
I think there are aldec specifics around using/finding the
"smartmodels"
you need for simulating PPCs, MGTs etc. using swift libraries, but i'm
on thin ice here.
So far my experience with riviera is good, slower (than the M*
simulator) in the elaboration,
but atleast as fast during simulation.
Regards /Pontus
#
# Makefile to compile xilinx libs for the riviera simulator
#
# Existing libraries:
# unisim simulation models of unisim components
# simprim simulation models of post PAR components with vital
timing
# xilinxcorelib simulation models of coregen components (needs
unisim)
# First we need to create the library file, then compile the source
into
# that library.
# I don't create an aldec "global" library, since the version of
xilinx
# should be set by my specific design, not the simulator.
# Before running this makefile you must setup paths to the the
tool(s).
# First check some environment variables.
ifeq ($(XILINX),)
$(error XILINX environment variable not set)
endif
# -93 : vhdl language revision
# -o : automatic file ordering
VCOM_OPTS := -93 -o
.PHONY : all
all : unisim xilinxcorelib simprim
################################################################
# unisim
################################################################
.PHONY : unisim
unisim : unisim_vlib.log unisim_vcom.log
unisim_vlib.log :
vlib unisim | tee $@
unisim_files := ${XILINX}/vhdl/src/unisims/*.vhd
unisim_vcom.log :
vcom ${VCOM_OPTS} -work unisim ${unisim_files} | tee $@
################################################################
#simprim
################################################################
.PHONY : simprim
simprim : simprim_vlib.log simprim_vcom.log
simprim_vlib.log :
vlib simprim | tee $@
# dont use any of the _mti files
simprim_files := $(filter-out %_mti.vhd,$(wildcard ${XILINX}/vhdl/src/
simprims/*.vhd))
simprim_vcom.log :
vcom ${VCOM_OPTS} -work simprim ${simprim_files} | tee $@
################################################################
# xilinxcorelib (needs unisim to be compiled first)
################################################################
.PHONY : xilinxcorelib
xilinxcorelib : unisim xilinxcorelib_vlib.log xilinxcorelib_vcom.log
xilinxcorelib_vlib.log :
vlib xilinxcorelib | tee $@
# Remember this_pwd so to avoid specifying source paths for vcom.
this_pwd := $(shell cygpath -m `pwd`)
# -s tells vcom to use the library.cfg in this folder
# -d tells vcom to use this folder for tmp files
# vhdl_analyze_order is a xilinx file listing all coregen files,
# and their proper analysis order.
xilinxcorelib_vcom.log :
cd ${XILINX}/vhdl/src/XilinxCoreLib/; \
vcom ${VCOM_OPTS} -work xilinxcorelib \
-s $(this_pwd) \
-d $(this_pwd) \
-f vhdl_analyze_order | tee $(this_pwd)/$@; \
################################################################
# clean
################################################################
# Aldec leaves a number of different files behind if compile is
interupted...
.PHONY : clean
clean :
rm -f library.cfg *.dag *.tmp *.epr *.bin *.log *.opr *.top
rm -rf unisim simprim xilinxcorelib
.PHONY : check
check : unisim_vlib.log unisim_vcom.log simprim_vlib.log
simprim_vcom.log xilinxcorelib_vlib.log xilinxcorelib_vcom.log
cat $^ | grep -i err
# last line
Article: 132905I am planning to support 256-taps with direct form FIR filter which suffers from less speed and more hardware resources compared to distributed arithmetic architecture( i dont know about this) I have tested my design with inputs as impulse test,step test,sine,square,sawtooth,pulse and white noise...I dont know how to check for overflow?wat is the test case? regards, faza PFC wrote: > > Faza:I have coded as per direct form structure..so for N-taps it > > requires N-multiplication and N-1 addition...And also for fs= 1Mhz ,1 > > million samples will be generated, > > since N=10,it has 10 filter coefficients.. > > Here number of Input samples> number of filter coefficients > > samples... > > as per my code i will get 1 million o/p samples ...Is it correct?? > > Well with N input samples and M taps you get N+M-1 output samples but if > you are streaming a real time signal, noone cares about the boundary > conditions, so you can say that roughly number of input samples = number > of output samples > > > But i know as per convolution i should get 10+1 million-1 samples.. > > In general i will get number of output samples = number of input > > samples > > If i have number of input samples < coefficients i have to zero pad > > the end of input samples to process all the coefficients.. > > pls clarify on this?? > > Yes you have to zero pad. If you stop the input stream, your filter will > go to sleep waiting for more data which doesn't come, so the output will > be truncated. > > > PFC:What is the signal you want to filter ? > > Faza:An audio signal for audio applications and signals used in > > multimedia applications are my real time inputs > > OK then if it's audio why do you mention crazy sample rates like 600 MHz ? > For audio ultimate quality is 192 kHz which is easy to do in FPGA. > > > PFC:Who chose the sample frequency ? > > Faza:sampling frequency of input signal will be choosen by me in > > software to generate the samples as an input to FPGA > > Then choose a realistic input frequency... > > > PFC:it a REAL application which NEEDS that speed IN REAL TIME ? If it > > is, it is going to be very EXPENSIVE. > > Faza:Yes it should be real time...But i am not sure whether my design > > target to xilinx FPGA as I am planning to support 256-taps with direct > > form FIR filter which suffers from less speed and more hardware > > resources compared to distributed arithmetic architecture( i dont know > > about this) > > > > PFC: What is it that you want to do ? > > Faza:A generic FIR filter which can support upto 256-taps for audio > > and multimedia applications... > > Suppose you have 8 channels of 192 kHz audio in real time that's > 1.536.000 samples/s, now if you use 256 taps that's about 400 million > MAC/s which means you can do it with a $10 FPGA.Article: 132906
I am planning to support 256-taps with direct form FIR filter which suffers from less speed and more hardware resources compared to distributed arithmetic architecture( i dont know about this) I have tested my design with inputs as impulse test,step test,sine,square,sawtooth,pulse and white noise...I dont know how to check for overflow?wat is the test case? regards, faza On Jun 10, 4:45=A0pm, PFC <li...@peufeu.com> wrote: > > Faza:I have coded as per direct form structure..so for N-taps it > > requires N-multiplication and N-1 addition...And also for fs=3D 1Mhz ,1 > > million samples will be generated, > > since N=3D10,it has 10 filter coefficients.. > > Here number of =A0Input samples> number of filter coefficients > > samples... > > as per my code i will get 1 million o/p samples ...Is it correct?? > > =A0 =A0 =A0 =A0 Well with N input samples and M taps you get N+M-1 output = samples but if =A0 > you are streaming a real time signal, noone cares about the boundary =A0 > conditions, so you can say that roughly number of input samples =3D number= =A0 > of output samples > > > But i know as per convolution i should get 10+1 million-1 samples.. > > In general i will get number of output samples =3D number of input > > samples > > If i have number of input samples < coefficients i have to zero pad > > the end of input samples to process all the coefficients.. > > pls clarify on this?? > > =A0 =A0 =A0 =A0 Yes you have to zero pad. If you stop the input stream, yo= ur filter will =A0 > go to sleep waiting for more data which doesn't come, so the output will = =A0 > be truncated. > > > PFC:What is the signal you want to filter ? > > Faza:An audio signal for audio applications =A0and =A0signals used in > > multimedia applications are my real time inputs > > =A0 =A0 =A0 =A0 OK then if it's audio why do you mention crazy sample rate= s like 600 MHz ? > =A0 =A0 =A0 =A0 For audio ultimate quality is 192 kHz which is easy to do = in FPGA. > > > PFC:Who chose the sample frequency ? > > Faza:sampling frequency of input signal will be choosen by me in > > software to generate the samples as an input to FPGA > > =A0 =A0 =A0 =A0 Then choose a realistic input frequency... > > > PFC:it a REAL application which NEEDS that speed IN REAL TIME ? If it > > is, =A0it is going to be very EXPENSIVE. > > Faza:Yes it should be real time...But i am not sure whether my design > > target to xilinx FPGA as I am planning to support 256-taps with direct > > form FIR filter which suffers from less speed and more hardware > > resources compared to distributed arithmetic architecture( i dont know > > about this) > > > PFC: =A0What is it that you want to do ? > > Faza:A generic FIR filter which can support upto 256-taps for audio > > and multimedia applications... > > =A0 =A0 =A0 =A0 Suppose you have 8 channels of 192 kHz audio in real time = that's =A0 > 1.536.000 samples/s, now if you use 256 taps that's about 400 million =A0 > MAC/s which means you can do it with a $10 FPGA.Article: 132907
On Mon, 09 Jun 2008 21:02:25 +0100, Andy Botterill <andy@plymouth2.demon.co.uk> wrote: >Using verilog and ISE 10.1. > >I add a reg to modify the design's behaviour. It works and it works >correctly. The change is intended to invert the carry logic for some >op-codes. > >However synthesis , using XST , gives the following warning message. > >WARNING:Xst:646 - Signal <borrow> is assigned but never used. This >unconnected signal will be trimmed during the optimization process. > >What I would like to do is to find out which lines are caing this >warning and see if I have missed something or the synthesis tool has >made a mistake. > >All sixteen op-codes assign something to borrow. Sometimes true, >sometimes inverse and sometimes 0. What do you do with borrow? The synthesis tool is complaining that you don't use "borrow" not that you don't assign to it. You can store the borrow net's value in a register and use it in later instructions. That way it can not be optimized away. Are you sure borrow is being used ie, it is on the right side of an assignment? Also remember that if you're using borrow in combinational logic and it's a real inverse of carry, as someone else already pointed out, you may not need borrow at all. Investigate how borrow is used.Article: 132908
On Jun 9, 9:06 pm, "Bill Ngo" <bill....@sympatico.ca> wrote:
> "Gabor" <ga...@alacron.com> wrote in message
>
> <news:e3538f86-b448-4bb4-91da-bf172b836b78@8g2000hse.googlegroups.com>...
>
> > If you want to remove the buffer delay, you need to route the output
> > of the BUFG
> > back to the CLKFB input of the DCM. You have the CLK0 output routed
> > directly
> > (internal feedback) which only removes delay to the CLK0 output itself
> > before
> > the BUFG.
>
> > HTH,
> > Gabor
>
> Thanks Gabor,
>
> I explicitly added an BUFG between the DCM's CLK0 output to CLK before
> feeding it back as well as an explicit IBUFG from the input pad to CLKIN of
> the DCM and the delay is nulled out.
>
> It is noteworthy though, that even when there is no BUFG instantiated
> explicitly, the tool does add a BUFG in the feedback path as well as an
> IBUFG from the input pad to DCM CLKIN. This can be seen in the .twr report
> showing details for the CLK path which is shown below:
>
> -------------------------------------------------------
> Maximum Clock Path: LCLK_IN to READY_CARRIER
> Location Delay type Delay(ns) Physical Resource
> Logical Resource(s)
> ------------------------------------------------- -------------------
> D14.I Tiopi 0.963 LCLK_IN
> LCLK_IN
> LCLK_IN_IBUFG
> DCM_ADV_X0Y3.CLKIN net (fanout=1) 1.260 LCLK_IN_IBUFG
> DCM_ADV_X0Y3.CLK0 Tdmcko_CLK -2.213 DCM_BASE_inst
> DCM_BASE_inst
> BUFGCTRL_X0Y23.I0 net (fanout=3) 1.504 CLK1
> BUFGCTRL_X0Y23.O Tbgcko_O 0.900 CLK_BUFG
> CLK_BUFG
> SLICE_X52Y103.CLK net (fanout=123) 2.565 CLK
> ------------------------------------------------- ---------------------------
> Total 4.979ns (-0.350ns logic,
> 5.329ns route)
> -------------------------------------------------------
>
> The similar detail for the explicitly instantiated IBUFG and BUGF is shown
> below - note
> the much larger 'minus' delay introduced by the DCM:
>
> -------------------------------------------------------
> Maximum Clock Path: LCLK_IN to ASTATE_FFd2
> Location Delay type Delay(ns) Physical Resource
> Logical Resource(s)
> ------------------------------------------------- -------------------
> B17.I Tiopi 0.988 LCLK_IN
> LCLK_IN
> IBUFG_LCLK_IN
> DCM_ADV_X0Y3.CLKIN net (fanout=1) 1.191 LCLK_INf
> DCM_ADV_X0Y3.CLK0 Tdmcko_CLK -7.207 DCM_BASE_inst
> DCM_BASE_inst
> BUFGCTRL_X0Y25.I0 net (fanout=1) 1.504 DCM_CLK0
> BUFGCTRL_X0Y25.O Tbgcko_O 0.900 BUFG_CLK
> BUFG_CLK
> SLICE_X0Y53.CLK net (fanout=174) 2.676 CLK
> ------------------------------------------------- ---------------------------
> Total 0.052ns (-5.319ns logic,
> 5.371ns route)
> -------------------------------------------------------
>
> I don't understand the difference - both reports show similar connections
> for the global buffers.
>
> Bill
Actually the difference between the two is in the feedback path. When
you don't instantiate the BUFG, the synthesis will place one between
the
DCM CLK0 output and your clock loads, but it doesn't use the output of
that BUFG for feedback as indicated by the much smaller 'minus' delay.
So the clock paths in the report will only differ by the feedback
compensation ('minus') delay. You could verify the connection if
you looked at an RTL schematic or use the FPGA editor.
Regards,
Gabor
Article: 132909On Jun 10, 1:39 am, Peter Alfke <al...@sbcglobal.net> wrote: > On Jun 9, 10:32 pm, vikram <vikram...@gmail.com> wrote: > > > hi.... > > > how many times cain i download .bit files onto an fpga? i use > > virtex2pro.... > > > thanks > > vikram > > Billions of times. Since the configuration is stored in latches > (commonly called SRAMs) there is no known wear-out mechanism. > You might wear out the Flash storage device after tens of thousands of > changes, but nevevr the FPGA itself. > Peter Alfke, Xilinx What never? No, never! What never? Well, hardly ever... ;)Article: 132910
The task of my student research project is to implement a digital VSB modulator for analog TV in an FPGA. The design has three inputs: CVBS (Color Video Baseband Signal) and audio1 (mono/left) as well as audio2 (right) - digital sampled as YCbCr and I2S, respectively. The output shall be "sampled" analog TV baseband (real-values) as input for direct digital synthesis to TV RF. Can anyone help me with an idea how to solve this task? Thanks in advance!Article: 132911
Hi all,
thanks for your reply. I have tried some suggestions:
1)
> >> int timer_value =3D * (volatile int *) TIMED_REG_ADDRESS;
> >> volatile int result =3D doSomething();
> >> timer_value =3D (* (volatile int *) TIMED_REG_ADDRESS) - timer_value;
this doesnt work.
2)
Hi David, you said this:
> You can't make a function itself "volatile", but you can use the
> "noinline" function attribute to ensure it is not inlined - that's
> probably enough to make sure it is called properly.
how do you make an inline function? can kindly provide give a brief
example?
kindly help. I have already tried to dump out the assembly
instructions from the compiled binary file beforehand using mb-
objdump. I already know that the smart compiler reorders the timer
enable and puts it some where at the bottom just before the read back
of timer value and timer disabled.
so i get something like this ( in C terms for easy reading):
void main() {
Xuint32 countvalue;
// enable_timer(); <=3D=3D=3D=3D=3D=3D it dun do it here :(
// do some stuff on Microblaze
... //some lines of code ....
countvalue =3D readback_timer();
enable_timer(); <=3D=3D=3D=3D=3D=3D the stupid compiler reshuffles the =
code
here
disable_timer();
//send count value back to serial port
...
return1;
}
this is really disaster. :(
kindly help
Chris
On Jun 10, 12:47=A0am, David Brown <da...@westcontrol.removethisbit.com>
wrote:
> PFC wrote:
>
> >> int timer_value =3D * (volatile int *) TIMED_REG_ADDRESS;
> >> volatile int result =3D doSomething();
> >> timer_value =3D (* (volatile int *) TIMED_REG_ADDRESS) - timer_value;
>
> >> The compiler can call doSomething(), storing the result in a temporary
> >> register, then read TIMED_REG_ADDRESS, store the result in "result",
> >> then re-read TIMED_REG_ADDRESS - all without violating the volatile
> >> requirements.
>
> > =A0 =A0 Does the compiler know that doSomething() will never access any
> > volatile variable ?
> > =A0 =A0 (the generated assembly code was correct last time I checked).
>
> > =A0 =A0 Anyway you can always put your timer code in functions. I don't
> > think gcc reorders function calls ?...
>
> >>> =A0 =A0 =A0 =A0 "volatile int x" is a contradiction so gcc optimized a=
way
> >>> which is the
> >>> expected behaviour.
>
> >> How is it a contradiction?
>
> >> You can still get it's address and modify or examine it that way
> >> behind the compiler's back, so the compiler must assume that when you
> >> say it's volatile, you might mean it. =A0Granted you want to be careful=
> >> that you only do this during a time when the compiler is obligated to
> >> ensure that the variable exists, but that's not unreasonable within
> >> the scope, or when playing with a hardware-based debugger.
>
> > =A0 =A0 Sounds like a big shiny foot-gun.
> > =A0 =A0 But you're right... C is so perverse, lol.
>
> In answer to this and the other replies to my post:
>
> You are right that the compiler can only re-order "doSomething()" around
> volatile accesses if it knows that doSomething() does not make volatile
> accesses itself. =A0But the compiler can be surprisingly knowledgeable
> about such things - if the doSomething() function is in the same source
> file, and you have at least some optimisations enabled, then it probably
> has this knowledge. =A0In fact, in many common cases when you are writing
> test code like this, the doSomething() function is not only in the same
> file, but it is only used the one time, and the compiler may well inline
> the function. =A0Thus even if it *does* use volatile accesses,
> non-volatile accesses in doSomething() can be shuffled around about and
> below the timer accesses. =A0Just to add to the fun, the compiler might
> also figure out that parts of the code in doSomething() can be
> calculated at compile time, and eliminated from the object code.
>
> You can't make a function itself "volatile", but you can use the
> "noinline" function attribute to ensure it is not inlined - that's
> probably enough to make sure it is called properly.
>
> As has been said, check the assembly listing to make sure you are
> measuring the code you want to measure.- Hide quoted text -
>
> - Show quoted text -
Article: 132912
On Jun 10, 11:51=A0am, Gabor <ga...@alacron.com> wrote:
> On Jun 9, 9:06 pm, "Bill Ngo" <bill....@sympatico.ca> wrote:
>
>
>
> > "Gabor" <ga...@alacron.com> wrote in message
>
> > <news:e3538f86-b448-4bb4-91da-bf172b836b78@8g2000hse.googlegroups.com>..=
.
>
> > > If you want to remove the buffer delay, you need to route the output
> > > of the BUFG
> > > back to the CLKFB input of the DCM. =A0You have the CLK0 output routed=
> > > directly
> > > (internal feedback) which only removes delay to the CLK0 output itself=
> > > before
> > > the BUFG.
>
> > > HTH,
> > > Gabor
>
> > Thanks Gabor,
>
> > I explicitly added an BUFG between the DCM's CLK0 output to CLK before
> > feeding it back as well as an explicit IBUFG from the input pad to CLKIN=
of
> > the DCM and the delay is nulled out.
>
> > It is noteworthy though, that even when there is no BUFG instantiated
> > explicitly, the tool does add a BUFG in the feedback path as well as an
> > IBUFG from the input pad to DCM CLKIN. This can be seen in the .twr repo=
rt
> > showing details for the CLK path which is shown below:
>
> > -------------------------------------------------------
> > =A0 Maximum Clock Path: LCLK_IN to READY_CARRIER
> > =A0 =A0 Location =A0 =A0 =A0 =A0 =A0 =A0 Delay type =A0 =A0 =A0 =A0 Dela=
y(ns) =A0Physical Resource
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Logical Resource(s)
> > =A0 =A0 ------------------------------------------------- =A0-----------=
--------
> > =A0 =A0 D14.I =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Tiopi =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 0.963 =A0 LCLK_IN
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LCLK_IN
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LCLK_IN_IBUFG
> > =A0 =A0 DCM_ADV_X0Y3.CLKIN =A0 net (fanout=3D1) =A0 =A0 =A0 =A01.260 =A0=
LCLK_IN_IBUFG
> > =A0 =A0 DCM_ADV_X0Y3.CLK0 =A0 =A0Tdmcko_CLK =A0 =A0 =A0 =A0 =A0 -2.213 =
=A0 DCM_BASE_inst
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0DCM_BASE_inst
> > =A0 =A0 BUFGCTRL_X0Y23.I0 =A0 =A0net (fanout=3D3) =A0 =A0 =A0 =A01.504 =
=A0 CLK1
> > =A0 =A0 BUFGCTRL_X0Y23.O =A0 =A0 Tbgcko_O =A0 =A0 =A0 =A0 =A0 =A0 =A00.9=
00 =A0 CLK_BUFG
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0CLK_BUFG
> > =A0 =A0 SLICE_X52Y103.CLK =A0 =A0net (fanout=3D123) =A0 =A0 =A02.565 =A0=
CLK
> > =A0 =A0 ------------------------------------------------- =A0-----------=
----------------
> > =A0 =A0 Total =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A04.979ns (-0.350ns logic,
> > 5.329ns route)
> > -------------------------------------------------------
>
> > The similar detail for the explicitly instantiated IBUFG and BUGF is sho=
wn
> > below - note
> > the much larger 'minus' delay introduced by the DCM:
>
> > -------------------------------------------------------
> > Maximum Clock Path: LCLK_IN to ASTATE_FFd2
> > =A0 =A0 Location =A0 =A0 =A0 =A0 =A0 =A0 Delay type =A0 =A0 =A0 =A0 Dela=
y(ns) =A0Physical Resource
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Logical Resource(s)
> > =A0 =A0 ------------------------------------------------- =A0-----------=
--------
> > =A0 =A0 B17.I =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Tiopi =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 0.988 =A0 LCLK_IN
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0LCLK_IN
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IBUFG_LCLK_IN
> > =A0 =A0 DCM_ADV_X0Y3.CLKIN =A0 net (fanout=3D1) =A0 =A0 =A0 =A01.191 =A0=
LCLK_INf
> > =A0 =A0 DCM_ADV_X0Y3.CLK0 =A0 =A0Tdmcko_CLK =A0 =A0 =A0 =A0 =A0 -7.207 =
=A0 DCM_BASE_inst
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0DCM_BASE_inst
> > =A0 =A0 BUFGCTRL_X0Y25.I0 =A0 =A0net (fanout=3D1) =A0 =A0 =A0 =A01.504 =
=A0 DCM_CLK0
> > =A0 =A0 BUFGCTRL_X0Y25.O =A0 =A0 Tbgcko_O =A0 =A0 =A0 =A0 =A0 =A0 =A00.9=
00 =A0 BUFG_CLK
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0BUFG_CLK
> > =A0 =A0 SLICE_X0Y53.CLK =A0 =A0 =A0net (fanout=3D174) =A0 =A0 =A02.676 =
=A0 CLK
> > =A0 =A0 ------------------------------------------------- =A0-----------=
----------------
> > =A0 =A0 Total =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A00.052ns (-5.319ns logic,
> > 5.371ns route)
> > -------------------------------------------------------
>
> > I don't understand the difference - both reports show similar connection=
s
> > for the global buffers.
>
> > Bill
>
> Actually the difference between the two is in the feedback path. =A0When
> you don't instantiate the BUFG, the synthesis will place one between
> the
> DCM CLK0 output and your clock loads, but it doesn't use the output of
> that BUFG for feedback as indicated by the much smaller 'minus' delay.
> So the clock paths in the report will only differ by the feedback
> compensation ('minus') delay. =A0You could verify the connection if
> you looked at an RTL schematic or use the FPGA editor.
>
> Regards,
> Gabor
Just wanted to point out that the User Guide outlines the standard
usage of the DCMs, including having the BUFG in the feedback path.
http://www.xilinx.com/support/documentation/user_guides/ug070.pdf
It's quite a handy little guide! :-)
Article: 132913Hi, im an sending with an Virtex4-FX 8b10b encoded data at 1.25Gbps. It is working fine in simulation, but the implementation sends incorrect data. (checked with a scope at the MGT output) Apparently 6-bit sub-characters with no disparity are sent inverted: D.03 is sent as D.28 D.05 is sent as D.26 D.06 is sent as D.25 etc. As far as I can tell all other charecters (e.g. those with negative of positive disparity) are sent correctly. The MGTs are configured for normal automatic 8b10b encoding. I am only controlling the data pins and txcharisk. Has anybody seen this before? Any ideas what could cause this? Instable clocks? Incorrect CONFIG STEPPING? Timing Errors? Thx for your help, Kolja SulimmaArticle: 132914
Modellpilot wrote: > The task of my student research project is to implement a digital VSB > modulator for analog TV in an FPGA. The design has three inputs: CVBS > (Color Video Baseband Signal) and audio1 (mono/left) as well as audio2 > (right) - digital sampled as YCbCr and I2S, respectively. The output > shall be "sampled" analog TV baseband (real-values) as input for > direct digital synthesis to TV RF. > > Can anyone help me with an idea how to solve this task? > > Thanks in advance! The Vestigal SideBand modulation gives a spectrum where the baseband DC level modulated up to the carrier frequency is half amplitude with the signal falling to zero on the one side and up to full scale on the other side of the carrier ( the side where almost all the information is maintained). Since you can't mix a signal with real-only samples (no I-Q modulation) up to that carrier frequency with lobes that are different on both sides of the carrier, you need to either preform your filtering in complex space and translate it to real or translate your signal to something that can be filtered to produce real, filtered results. I'd recommend you think about how you might accomplish either approach and get back to us on how you'd like to proceed. - John_HArticle: 132915
On Jun 10, 12:02=A0am, "ALu...@web.de" <ALu...@web.de> wrote: > Hi, > > I have described a state machine running with an external pixel clock. > As I could see > on the oscilloscope the ScanDetect signal becomes high indicating that > the pixel clock > is stable. BUT the clock is not stable for some while after Scdt > becomes high. The clock > seems to tune after some us. (stable clock should have around 100MHz) > The clock is changing its frequency, high and low phases are > symmetrical. > > If the FSM is running with that clock and if Scdt=3D'1' is used to start > the FSM, can I trust > the state changes of the FSM ? > > Thank you for your opinion. > > Rgds > Andre If the unstable clock runs directly into the chip (without using the DCM) your only concern is the shortest possible time between two rising (or falling) clock edges, which your design must accommodate. Frequency modulation is otherwise irrelevant. If you use a DCM, you must follow the rules for input cycle changes, as specified in the data sheet. Peter AlfkeArticle: 132916
Thanks for the whitepaper, Peter! WP335 - Creative Uses of Block RAM http://www.xilinx.com/support/documentation/white_papers/wp335.pdf It's good to see the start of the conversion. I remember the BlockRAM tricks from one of the many helpful TechXclusives and am happy to see it once again - in some form - available for reference. I appreciate the extra time you have (and will) put in to get those useful bits into a white-paper form. Are the six easy pieces already up or a planned event? - John_HArticle: 132917
On Jun 10, 10:35=A0am, John_H <newsgr...@johnhandwork.com> wrote: > Thanks for the whitepaper, Peter! > > WP335 - Creative Uses of Block RAM > =A0http://www.xilinx.com/support/documentation/white_papers/wp335.pdf > > It's good to see the start of the conversion. =A0I remember the BlockRAM > tricks from one of the many helpful TechXclusives and am happy to see > it once again - in some form - available for reference. =A0I appreciate > the extra time you have (and will) put in to get those useful bits > into a white-paper form. > > Are the six easy pieces already up or a planned event? > > - John_H Thanks, John , for the friendly comment. Some TechXclusives are now reborn as White Papers. And not without problems. The TechXclusive process had been extremely informal, hardly any peer review, no formal Tech-writing, and no legal "censorship". It was built on trust, kind of like my postings in this newsgroup. A White Paper goes through tech-writing and through peer review, and if somebody does not like it, he can veto and stall the project. Since I often stick my head out with unconvential solutions, I thus encounter these problems. Makes you wish for the good old days... PeterArticle: 132918
"John_H" <newsgroup@johnhandwork.com> wrote in message news:57a49bb7-7ef2-47d4-ba6e-8e55f3458ada@79g2000hsk.googlegroups.com... > Thanks for the whitepaper, Peter! > > WP335 - Creative Uses of Block RAM > http://www.xilinx.com/support/documentation/white_papers/wp335.pdf > [snip] > - John_H Just FYI, there are also some other uses described in XAPP463 starting on page 24. Although this is written for Spartan-3, the block RAM is compatible with Spartan-3A/-3E, Virtex-II/Pro, etc. http://www.xilinx.com/support/documentation/application_notes/xapp463.pdf -- Steve Knapp Prevailing Technology, Inc. www.prevailing-technology.comArticle: 132919
On Jun 10, 10:55 am, Peter Alfke <pe...@xilinx.com> wrote: > > WP335 - Creative Uses of Block RAM > > http://www.xilinx.com/support/documentation/white_papers/wp335.pdf Peter, for the read-modify-write trick, don't you need to forward the write in case the previous cycle wrote the same location? TommyArticle: 132920
Hey all -- So I've got a design, the very vaguest outlines of which are beginning to gel. But one of the things that's becoming apparent is that it would benefit from real clock rates somewhere between the obscene and the unthinkable. Throwing lots of money at the problem seems to get me to 500 MHz, yet more can get me up to 550 MHz, but I could get a lot of other things to run much more smoothly if I could get clock rates out into the 650 MHz ballpark. That's for BRAMS and multipliers/DSP slices, not just the flops. So I get to thinking about how the clock rate specs get figured out, and how they have to accomodate the slow silicon at the maximum operating temperatures. And that thought leads around in circles for a while, and ultimately leads to the following appalling question: Anyone know anything about using Peltier modules, refrigerant pumping systems, or the like, to cheat up the speed of an FPGA? Is it even feasible to try to get a 20-30% overclock just from the joys of lower temperatures? Or do I just suck it up and deal with the rated clock speeds? -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 132921
I've just had an email from Altera about the availability of Quartus Web Edition 8.0. I'm in the process of downloading it. Hopefully It'll have finished before the system gets overloaded. LeonArticle: 132922
John_H wrote: > Modellpilot wrote: > > The task of my student research project is to implement a digital VSB > > modulator for analog TV in an FPGA. The design has three inputs: CVBS > > (Color Video Baseband Signal) and audio1 (mono/left) as well as audio2 > > (right) - digital sampled as YCbCr and I2S, respectively. The output > > shall be "sampled" analog TV baseband (real-values) as input for > > direct digital synthesis to TV RF. > > > > Can anyone help me with an idea how to solve this task? > > > > Thanks in advance! > > The Vestigal SideBand modulation gives a spectrum where the baseband > DC level modulated up to the carrier frequency is half amplitude with > the signal falling to zero on the one side and up to full scale on the > other side of the carrier ( the side where almost all the information > is maintained). > > Since you can't mix a signal with real-only samples (no I-Q > modulation) up to that carrier frequency with lobes that are different > on both sides of the carrier, you need to either preform your > filtering in complex space and translate it to real or translate your > signal to something that can be filtered to produce real, filtered > results. > > I'd recommend you think about how you might accomplish either approach > and get back to us on how you'd like to proceed. > > - John_H I just remembered that the 1/2 amplitude at the carrier I spoke of is in the demodulation side. Vestigal Side Band modulation has flat response to the carrier on the useful lob side but lops off most of the unimportant lobe, keeping only close-in information flat. The suggestion still applies: produce complex filter results and convert (indirectly) to real or convert your baseband signal to something you can filter to produce real outputs.Article: 132923
Hi, You can try increasing the supply voltage too I guess. Be careful with sub-zero cooling, might cause condensation. The problem is the speeds are not characterised at those voltages, temperatures. So its difficult for the tool to find what speed is achieved/can be achieved. Raghu. On Jun 10, 11:51=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > Hey all -- > > So I've got a design, the very vaguest outlines of which are beginning > to gel. =A0But one of the things that's becoming apparent is that it would= > benefit from real clock rates somewhere between the obscene and the > unthinkable. > > Throwing lots of money at the problem seems to get me to 500 MHz, yet > more can get me up to 550 MHz, but I could get a lot of other things to > run much more smoothly if I could get clock rates out into the 650 MHz > ballpark. =A0That's for BRAMS and multipliers/DSP slices, not just the flo= ps. > > So I get to thinking about how the clock rate specs get figured out, and > how they have to accomodate the slow silicon at the maximum operating > temperatures. =A0And that thought leads around in circles for a while, and= > ultimately leads to the following appalling question: > > Anyone know anything about using Peltier modules, refrigerant pumping > systems, or the like, to cheat up the speed of an FPGA? =A0Is it even > feasible to try to get a 20-30% overclock just from the joys of lower > temperatures? =A0Or do I just suck it up and deal with the rated clock spe= eds? > > -- > Rob Gaddi, Highland Technology > Email address is currently out of orderArticle: 132924
Rob Gaddi wrote:
> Anyone know anything about using Peltier modules, refrigerant pumping
> systems, or the like, to cheat up the speed of an FPGA? Is it even
> feasible to try to get a 20-30% overclock just from the joys of lower
> temperatures?
I would finish a proto design and run some sims
before I tried to speed it up.
-- Mike Treseler
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