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> I am not an expert on Altera licensing, but as far as I can tell you u= se = > Quartus web edition and open core evaluation during development. This= = > means you can use the DDR core (the sdram core is always free from = > Altera, and runs a lot more than 50 MHz, as is their dma core) and the= = > NIOS core while connected to Quartus with by jtag. For stand-alone us= e, = > you have to buy a NIOS license and a DDR core license (in practice, yo= u = > buy a licence for the full version of Q, and get the DDR core license = = > along with it, as well as other cores - the FIR and FFT cores might be= = > of interest). When you buy these, you get a year's worth of upgrades = = > and support, and a perpetual license for the cores. Duhhhhhhhhh I missed the fact that the "free" NIOS was not free, thanks for pointin= g = this out ! > Of course, it might work out cheaper (depending on your volumes, and = > development times and costs) just to use two SDRAM chips and a faster Or a 32 bit SDRAM which is what I had in mind initially. > clock, saving you the need to buy Q. Similarly, you might find a = > different cpu core such as Lattice's free core, or something from = > opencores, will do the same job. I have an escape route. If I include FireWire in the project (which now seems likely), then I c= an = use the ARM7 cpu which is in the DICE FireWire chip. I would have to = connect its bus to the FPGA, using lots of pins, but there are enough pi= ns = to do this. I think this is going to be the simplest way to pass the = licensing minefield. Now I am thinking about the memory interface : - DDR=3Dhard, SDR=3Deasy, - DDR=3D2.5V, SDR=3D3.3V, - We want some LVDS IO and lots of 3.3V IO, so we want one 2.5V bank, = Xilinx has 4 banks and Altera 8, so LVDS IO mandates DDR on Xilinx lest = a = lot of pins be wasted, not so on Altera because of the 8 banks, - But Altera Cyclone III has extremely tight tolerances on 3.3V because = of = the process used, I read on this group that actually it likes 3.0V bette= r, = and a little overshoot on 3.3V makes it latchup apparently. - This makes me uneasy to use Altera because there will be cables, and = cables =3D risks of overshoot...Article: 132676
Hello, I have been using Xilinx MLxxx series boards. For the first time, we are planning to buy a PCIe evaluation board from HiTech global. Do anyone has experience with HiTech global boards before? Could you comment on their support and quality of documentation & board? Would appreciate your inputs. Thanks, MuthuArticle: 132677
PFC wrote: > >> I am not an expert on Altera licensing, but as far as I can tell you >> use Quartus web edition and open core evaluation during development. >> This means you can use the DDR core (the sdram core is always free >> from Altera, and runs a lot more than 50 MHz, as is their dma core) >> and the NIOS core while connected to Quartus with by jtag. For >> stand-alone use, you have to buy a NIOS license and a DDR core license >> (in practice, you buy a licence for the full version of Q, and get the >> DDR core license along with it, as well as other cores - the FIR and >> FFT cores might be of interest). When you buy these, you get a year's >> worth of upgrades and support, and a perpetual license for the cores. > > Duhhhhhhhhh > I missed the fact that the "free" NIOS was not free, thanks for > pointing this out ! > Yes, you can use the Nios "freely" during development, and "freely" once you've paid the license :-) It's not unreasonable, actually - it's a one-off cost for a perpetual royalty-free license. But for a low-budget project, it's a significant cost. >> Of course, it might work out cheaper (depending on your volumes, and >> development times and costs) just to use two SDRAM chips and a faster > > Or a 32 bit SDRAM which is what I had in mind initially. > >> clock, saving you the need to buy Q. Similarly, you might find a >> different cpu core such as Lattice's free core, or something from >> opencores, will do the same job. > > I have an escape route. > If I include FireWire in the project (which now seems likely), then > I can use the ARM7 cpu which is in the DICE FireWire chip. I would have > to connect its bus to the FPGA, using lots of pins, but there are enough > pins to do this. I think this is going to be the simplest way to pass > the licensing minefield. > If you have an external processor connected anyway, you can also save a bit by using the processor to download the FPGA configuration - no need for a configuration flash, and it's easier to update the fpga software in the field. I might also suggest an FTDI FT2232C USB device - you can use it to download software into an FPGA or a processor via SPI or UART, thus avoiding any flash at all on the card (if you are happy always being connected to a PC, of course). > Now I am thinking about the memory interface : > > - DDR=hard, SDR=easy, > - DDR=2.5V, SDR=3.3V, > - We want some LVDS IO and lots of 3.3V IO, so we want one 2.5V bank, > Xilinx has 4 banks and Altera 8, so LVDS IO mandates DDR on Xilinx lest > a lot of pins be wasted, not so on Altera because of the 8 banks, > - But Altera Cyclone III has extremely tight tolerances on 3.3V because > of the process used, I read on this group that actually it likes 3.0V > better, and a little overshoot on 3.3V makes it latchup apparently. > - This makes me uneasy to use Altera because there will be cables, and > cables = risks of overshoot... Look carefully at the Altera application notes for how to use 3.3V safely on the CIII - don't just accept the word of a Xilinx employee! (I'm not accusing anyone in c.a.f. of lying - but you can't except a X employee to go out of their way to put Altera devices in the best light.) I haven't used a CIII yet, so I have no experience here.Article: 132678
On Jun 5, 7:15=A0am, muthu...@gmail.com wrote: > Hello, > > I have 2 boards, of which one has PPC core and other do not. > > [board1 /w PPC]-------uart-------[board2 /wo PPC] > > I want to use UART as a debug interface for board2. > > So,I am looking for a UART Master core that shall be Maser on the PLB/ > OPB bus that I can use it in board2 FPGA. > > The Xilinx EDK library provide UART cores that has PLB/OPB interfaces > as core side interfaces. But these interfaces are Slave interface. > > Do anyone has UART core (Master on PLB/OPB)? Is it advisable to go for > such setup? > > Thank you. > > Best regards, > Muthu Hi Muthu, I do not know if this is the best way to go, this depends on your application requirements. A UART would be a slow way to control the bus on the second board but it may be enough. I also needed something like that mainly for debugging or controlling configuration register from a PC. So, I wrote a small interpreter connected to a UART that can control a BUS in the FPGA. Its not PLB/ OPB compatible but can be modified as required. The interpreter can receive either ASCII commands from a PC Terminal for example or binary format commands which are much more efficient and also support block reading/writing. If you think it might help you please send me an email and I will send you the source files. Regards, MotiArticle: 132679
> If you have an external processor connected anyway, you can also save = a = > bit by using the processor to download the FPGA configuration - no nee= d = > for a configuration flash, and it's easier to update the fpga software= = > in the field. I might also suggest an FTDI FT2232C USB device - you c= an = > use it to download software into an FPGA or a processor via SPI or UAR= T, = > thus avoiding any flash at all on the card (if you are happy always = > being connected to a PC, of course). Actually this CPU needs a parallel flash to boot (which it then copies = to = its own SDRAM). Since I'll put the FPGA on the CPU bus, I could use a = small SPI flash to program the FPGA into a SRAM containing the CPU = bootloader, this way I can do without the parallel Flash and the special= = cable to program it (who needs YET ANOTHER JTAG cable ?). Then the CPU c= an = read the rest of the firmware from SPI flash and reconfigure the FPGA fr= om = a choice of bitstreams... >> Now I am thinking about the memory interface : >> - DDR=3Dhard, SDR=3Deasy, >> - DDR=3D2.5V, SDR=3D3.3V, >> - We want some LVDS IO and lots of 3.3V IO, so we want one 2.5V bank,= = >> Xilinx has 4 banks and Altera 8, so LVDS IO mandates DDR on Xilinx le= st = >> a lot of pins be wasted, not so on Altera because of the 8 banks, >> - But Altera Cyclone III has extremely tight tolerances on 3.3V becau= se = >> of the process used, I read on this group that actually it likes 3.0V= = >> better, and a little overshoot on 3.3V makes it latchup apparently. >> - This makes me uneasy to use Altera because there will be cables, an= d = >> cables =3D risks of overshoot... > > Look carefully at the Altera application notes for how to use 3.3V = > safely on the CIII - don't just accept the word of a Xilinx employee! Heheh. Actually I looked and it doesn't seem that scary. But the issue = = made me a bit uneasy as I said. I will look more. I tried to generate some DDR interface with the Xilinx MIG but it's not= = very noob friendly. I need to try harder, lol.Article: 132680
On Jun 4, 3:44 pm, rickman <gnu...@gmail.com> wrote: > On Jun 2, 8:58 am, timinganalyzer <timinganaly...@gmail.com> wrote: > > > > > Hello All, > > > The TimingAnalyzer can be used to quickly and easily draw timing > > diagrams. > > Signals, clocks, buses, delays, constraints, and states are easily > > added > > from the GUI. > > > It can also be used to quickly do a timing analysis and check for > > timing faults. Minimum, typical, and worst case analysis can be > > performed. > > Delays and constraints are easily specified and changed to see if > > faster > > clocks or slower parts can be used without any timing faults. > > > There are 3 editions planned. The Free Edition(FE), the Standard > > Edition(SE), > > and the Professional Edition(PE). > > > You can download the Free Edition now and read all about the > > TimingAnalyzer at: > > >www.timing-diagrams.com > > > Comments and feedback are welcome at > > > supp...@timing-diagrams.com > > I spent about 5 minutes working with this program before I gave up. > My reason is not the problem posted below, but because of the user > interface decisions made. I don't know why every new program has to > reinvent something about the user interface. There is a standard call > Common User Interface (CUI) that is even documented by Microsoft, > IIRC. > > The one big difference that hit me up side my head was the way the > Cntl key is used counter-intuitively with mouse clicks for > selections. If you click on one item it is selected. If you click on > an second item, it is *added* to the selections. To deselect > something you have to either press the Cntl key while clicking on it > or you have to use the ESC key. I have *never* seen a program use > this sort of selection mechanism. I have seen variations on how you > select multiple, but every other program I have ever worked with, the > default action of clicking a new thing while an old thing was selected > was to deselect the first thing and to select the new thing. > > It was more than once that I tried to move some things and ended up > with a mess because extra moves kept happening. Combine this with the > lack of a working undo feature and I ended up rather frustrated and > gave up. I was looking for something that would save me time over a > program like Visio. > > I suggest that the author get some references on CUI or better yet, > use some other programs with graphical interfaces and go with the > flow. It is so much more productive than trying to retrain the > world... if you don't believe me, just look down at your keyboard. Do > you think the keyboard layout we all use was a good idea? It's just > easier to continue to use it than it is to retrain everyone that is > using it now. > > Rick Hello Rick, The goal is to make drawing timing diagrams as easy as possible, and I do agree about sticking to standard GUI practices, and that should be done for each OS. The program is in beta testing and I know it's not perfect but don't forget to look at the big picture. Not only can you draw timing diagrams, you can do timing analysis and show margins and find faults in designs, you can write scripts that automatically draw the diagrams so complex diagrams can be made with one command, or test vectors or testbenches can be generated with one command. If you need to document simulation results, it can read VCD formated files, then you can make annotated timing diagrams from simulations and include them in design documentation. With actual logic functions you can simulate gates, registers, counters, shift registers, and other logic functions which can help when deciding if the logic if fast enough or the clocks are to fast. So, keeping all that in mind, if beta users make valid and constructive suggestions for improvements and new features, they will incorporated into the program. Most all of them will be added before the final release 1.0. -DanArticle: 132681
Can you spell "surface acoustic wave"? That was the maximum cutoff frequency support i am expecting to get ....as my FIR filter is generic it should support from low to high frequency That means you must process ten samples on each clock cycle. =A0Do you know how to do that? my design accepts 1 sample/clockcycle but also you must generate ten output samples on every clock. current design takes number of taps specified+2 clock cycles to generate o/p for each sample.can u pls suggest for the current design wat should be the Fclk i should set to achieve 256 taps and 1GS/s,Is it possible?.And how u relate Fclk with Fs and Fc?as those Fs and Fc are constraints to generate coefficients why we have to consider in hardware implementation?How to decide Fclk?since the maximum clock rate depends on the logic and routing delay of the design... Were the figures you gave us (Fclk=3D250MHz, Fs=3D2.5GHz, Fc=3D1GHz) intended to reflect a real problem? Or were they simply random numbers? Those r the worst case i should support.. regards, faz On Jun 5, 4:27=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Thu, 5 Jun 2008 01:21:39 -0700 (PDT), fazulu deen wrote: > >can i implement a FIR filter of 256-taps(all the taps clocked > >synchronously),1Ghz cutoff frequency,2.5GS/s > > Can you spell "surface acoustic wave"? > > > with a input FPGA clock frequency of 250Mhz? > > So you plan to clock your FPGA at 1/10th the filter's > sampling frequency. =A0That means you must process ten > samples on each clock cycle. =A0Do you know how to do that? > > Since you plan for a cutoff frequency of 1GHz, you can't > undersample the filter's output. =A0So you not only need > to process ten input samples on every clock, but also > you must generate ten output samples on every clock. > That would lead to "interesting" I/O requirements. > There will also be "interesting" internal resource > requirements, unless your filter coefficients are > very sparse. > > Were the figures you gave us (Fclk=3D250MHz, Fs=3D2.5GHz, > Fc=3D1GHz) intended to reflect a real problem? Or were > they simply random numbers? > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 132682
On Wed, 4 Jun 2008 12:44:03 -0700 (PDT), rickman <gnuarm@gmail.com> wrote: >On Jun 2, 8:58 am, timinganalyzer <timinganaly...@gmail.com> wrote: >> Hello All, >> >> The TimingAnalyzer can be used to quickly and easily draw timing >> diagrams. >> Signals, clocks, buses, delays, constraints, and states are easily >> added >> from the GUI. >> www.timing-diagrams.com >> >> Comments and feedback are welcome at >> >> supp...@timing-diagrams.com > >I spent about 5 minutes working with this program before I gave up. >My reason is not the problem posted below, but because of the user >interface decisions made. I don't know why every new program has to >reinvent something about the user interface. There is a standard call >Common User Interface (CUI) that is even documented by Microsoft, >IIRC. Do you work in the NHS, or for one of their equipment suppliers? All the CUI references (including http://www.mscui.net/ seem to be associated with the health care sector. If you are thinking of some other user interface specification, can you help find it? (Not that a specification for the medical industry couldn't be more generally useful, but it seems unlikely to cover complex drawing tools) - BrianArticle: 132683
On Wed, 04 Jun 2008 18:05:58 -0400, Jeff Cunningham <jcc@sover.net> wrote: >PFC wrote: > >> So I thought about Spartan-3A DSP but it has a packaging problem : >> 0.8mm BGA ! No way. 1mm is fine but not 0.8mm. > >What's the big deal? I'm no expert, but is 0.8mm that much more >difficult to deal with than 1.0? And academic if you can use the FG676 which is still 1mm (and gives more I/O) - BrianArticle: 132684
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:jtif4418p6c196kebpq0d7r3rfk1n4ja3j@4ax.com... > On Thu, 5 Jun 2008 01:21:39 -0700 (PDT), fazulu deen wrote: > >>can i implement a FIR filter of 256-taps(all the taps clocked >>synchronously),1Ghz cutoff frequency,2.5GS/s > > Can you spell "surface acoustic wave"? > Hi Jonathan, Ha, that reminds me of a DSP course some of us attended in the mid-eighties. The lecturer chap tried to convince us that DSP was the only way to make linear phase filters. Sadly for him, several of us knew how our colour tellys extracted the chrominace signal! Cheers, Syms.Article: 132685
PFC wrote: > >> If you have an external processor connected anyway, you can also save >> a bit by using the processor to download the FPGA configuration - no >> need for a configuration flash, and it's easier to update the fpga >> software in the field. I might also suggest an FTDI FT2232C USB >> device - you can use it to download software into an FPGA or a >> processor via SPI or UART, thus avoiding any flash at all on the card >> (if you are happy always being connected to a PC, of course). > > Actually this CPU needs a parallel flash to boot (which it then > copies to its own SDRAM). Since I'll put the FPGA on the CPU bus, I > could use a small SPI flash to program the FPGA into a SRAM containing > the CPU bootloader, this way I can do without the parallel Flash and the > special cable to program it (who needs YET ANOTHER JTAG cable ?). Then > the CPU can read the rest of the firmware from SPI flash and reconfigure > the FPGA from a choice of bitstreams... > What I'm thinking of is that the CPU would boot from parallel flash (unless you are using the FTDI USB device mentioned), and copy its own software into sdram for speed. Then it uses an SPI interface to download the fpga firmware into the fpga, so that the fpga does not have any configuration flash devices. Normally you don't need a special cable to program the parallel flash on the board - you either pre-program it (if it's a big volume product) before mounting, or use the cpu's debug port or built-in bootloader (depending on the cpu in question).Article: 132686
On Jun 4, 9:48 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Seems there is room for one more ? > > http://www.siliconbluetech.com/news.html > > This seems to push the low-power envelope a little higher in > total gates (but still small, compared to the top-end FPGAs). > > What IS new, is the combination of 65nm process, and uA Icc numbers. > > They also have targeted 32Khz operation, a data point many others > simply ignore. > > Look to be still in early-silicon stages.... > > Anyone actually got some devices/tools ? > > -jg There is an article on them in FPGA journal: http://www.fpgajournal.com/articles_2008/20080603_newkid.htm I have looked at their website and it seems that they are not ready for a lot of small customers at this time (no sales office or distributor listings). My guess is that their continued success is based on their ability to land designs in high-volume consumer handheld devices. By the way, the FPGA Journal article seems to imply that the OTP non-volatile memory can hold more than one configuration. The datasheet does not bear this out. Cheers, GaborArticle: 132687
On Jun 5, 6:10 am, jid...@hotmail.com wrote: > I think the the problem lays on the TDO signal. The rising edge on TDO > is abnormally slow and flat on the first pulse, here:http://img239.imageshack.us/my.php?image=jtagtdoprommh2.png. The TDO > signal is connected directly from PROM to a Xilinx JTAG USB cable. > Does somebody know why the signal is so flat? > > Thanks, > > JJ Any chance that the power was still coming up when you acquired the trace on your 'scope?Article: 132688
I would like some suggestions on interfacing the Xilinx Spartan3 device with a DDR SDRAM. The idea is to build a controller that will set up the DDR-SDRAM so that I can do a burst read of a page of data into a block of internal SRAM (dual port). Your help is appreciatedArticle: 132689
Jon Beniston wrote: > Profits up by 7% then staff down by 7%. Presumably will be followed by > large executive level bonuses. How can your company still be > advertising jobs? Assuming Xilinx doesn't want to reduce the staff even more, it is just some mathematic: 7% for 250 jobs means Xilinx has about 3500 people. If everyone works some 20 years and then go into retirement or changes the job, Xilinx needs about one new employee every two days to keep the staff number at the same level. Using this calculation, I wonder why they cut the jobs, because not employing new people for about 2 years would have the same result. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 132690
On Thu, 5 Jun 2008 14:25:33 +0100, "Symon" wrote:
>Ha, that reminds me of a DSP course some of us attended in the mid-eighties.
>The lecturer chap tried to convince us that DSP was the only way to make
>linear phase filters. Sadly for him, several of us knew how our colour
>tellys extracted the chrominace signal!
Putting to one side for the moment the universal hazards of
appearing in public - undone fly-zips, remains of yesterday's
supper on the tie, iridescent facial pustules, and the like -
there are two obvious ways a trainer or lecturer can make
a complete idiot of themselves:
(1) simply getting something completely wrong - hard to
avoid in a training course of several days' duration,
human frailty being what it is;
(2) assuming that the audience/students/clients know
less than the trainer does.
These days, my preferred response to (2) is simply to enjoy
the fact that whenever I deliver a class I learn a bunch
of interesting stuff from the students. I hope they don't
mind too much, given that they're paying :-) In any case,
a certain humility is in order; most of us know quite a
lot about some things, but embarrassingly little about
other things. I reckon it'll be time to give up when I
find myself no longer willing to learn from students.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 132691On Jun 5, 9:14 am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Wed, 4 Jun 2008 12:44:03 -0700 (PDT), rickman <gnu...@gmail.com> > wrote: > > > > >On Jun 2, 8:58 am, timinganalyzer <timinganaly...@gmail.com> wrote: > >> Hello All, > > >> The TimingAnalyzer can be used to quickly and easily draw timing > >> diagrams. > >> Signals, clocks, buses, delays, constraints, and states are easily > >> added > >> from the GUI. > >>www.timing-diagrams.com > > >> Comments and feedback are welcome at > > >> supp...@timing-diagrams.com > > >I spent about 5 minutes working with this program before I gave up. > >My reason is not the problem posted below, but because of the user > >interface decisions made. I don't know why every new program has to > >reinvent something about the user interface. There is a standard call > >Common User Interface (CUI) that is even documented by Microsoft, > >IIRC. > > Do you work in the NHS, or for one of their equipment suppliers? > All the CUI references (includinghttp://www.mscui.net/seem to be > associated with the health care sector. I have no idea what you are talking about... I am an electronic design engineer and have never worked in the health care sector. What exactly is NHS? Is that a government agency or a company? BTW, I typoed above "call" should have been "called". CUI is a windows standard as far as I know. I guess maybe it is more general, but I have only heard the term used in the context of Windows. > If you are thinking of some other user interface specification, can you > help find it? Doesn't Microsoft provide a CUI for Windows? If nothing else, all you have to do is fire up most *any* program to learn how mouse clicks work to select items. Having the default action of a click to be "adding" items to the selection is a new twist. Most programs use Cntl-Left Click to cumulatively select items (or often to unselect them too). Unselection is typically done by clicking on *anything* else including nothing. So if I click on object A and then click on object B and drag, I would not expect object A to be dragged along with B. This happened to me with this program. Object A was dragged off the view and the undo didn't work. I couldn't find a way to expand the view, so I ended up with a drawing that had things in it that I couldn't delete or see. I ended up closing the program (partly out of frustration and partly out of time constraints) and let it save the file. I tried to start the program up again and it would not run. The author says the drawing file is now corrupt. When the program auto-opens it on startup, it crashes. Independant of the UI issues, a program really shouldn't crash when it reads a data file... of any nature. Of course that is a theoretical goal and can be difficult to achieve in practice. But certainly crashing on startup without visible error messages is not a good thing either. I had to start it from a DOS box to get anything useful from it... maybe that is more of a Java issue... and don't get me started complaining about Java. Does *anything* written in Java actually work? I'm really not trying to bash the tool. I expect there are those who like it and use it. I have often wanted a good tool for drawing waveforms and timing diagrams. But the very first and most important feature is that it has to be easy and intuitive to use. I feel that I should be able to sit down and use it without reading a manual or taking a tutorial. Many years ago I did that with a Mac! I expect most people do that with the iPhone and iPod. A timing diagram editor is not a complex tool. I should be able to draw simple waveforms without learning a complex interface. I currently use Visio and I find that to be a burdensome tool for simple things. It also has its own ways in which it doesn't work. I just wanted something a bit simpler. > (Not that a specification for the medical industry couldn't be more > generally useful, but it seems unlikely to cover complex drawing tools) I agree. I'm not sure why you mention this, but it sounds right. Do you know of a common denominator for tools with graphical interfaces? BTW, as long as I am ragging on the world of software. I don't like excessive movements of the mouse and switching back and forth with the keyboard. One of the things I have done to minimize movements is to move my windows toolbar to the top of the screen next to the menu of most programs. I find this so much easier to use than dragging the mouse around from top to bottom of the screen when I want to select between programs (which I seem to do a lot). The problem is that *many* programs (including Visio) don't understand that the windows toolbar is at the top now. New windows open with the title bar at the top of the screen, under the toolbar. Worse, some programs remember that they were at the top of screen, but remember it correctly (as being X pixels above the visible edge). Then when they restart incorrectly (or the dialog is reopened) the window is that much *more* off the top of the screen!!! With those applications I have to drag them well back onto the visible screen and try to remember to drag them back toward the middle before I close when they start drifting off the top again. Is it time to start cutting off fingers of programmers who continually mess up things like this? After a few mistakes they will be much less proficient at pumping out code (producing fewer bad programs) and after 10 mistakes... well I guess they could still type with their noses... 8^* Just a thought... Rick PS I am currently struggling with the Aldec simulator which has it's own set of problems. I'm actually here to complain about that, but I'll do it in another thread.Article: 132692
On Jun 5, 7:31=A0am, Frank Buss <f...@frank-buss.de> wrote: > Jon Beniston wrote: > > Profits up by 7% then staff down by 7%. Presumably will be followed by > > large executive level bonuses. How can your company still be > > advertising jobs? > > Assuming Xilinx doesn't want to reduce the staff even more, it is just som= e > mathematic: 7% for 250 jobs means Xilinx has about 3500 people. If everyon= e > works some 20 years and then go into retirement or changes the job, Xilinx= > needs about one new employee every two days to keep the staff number at th= e > same level. > > Using this calculation, I wonder why they cut the jobs, because not > employing new people for about 2 years would have the same result. > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-syst= ems.de Interesting theory, but we first have to get rid of sexual propagation, and institute massive cloning, so that all employees have the same brain cells, and then also receive the same experience and education. Really make them interchangeable. Brave New World... Peter AlfkeArticle: 132693
PFC wrote: >> What would your board bring to the table not available from the >> jillion of dev boards out there? > Low noise/EMI, small, cheap, and ethernet that works without > headaches. Believe it or not I found no such thing on the market. me too. I'm working on high-speed signal compression, btw. contact me (through my initials at ygdes.com) when you have something ready ! ygArticle: 132694
OK, What about the press release did you not get? We reorganized from a business unit structure, to a functional unit structure. We recognized the need to be more efficient, and serve our customers better. Get it? http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1162292&highlight= Better to re-organize when times are good. It wasn't fun, but in my 13 years in telecom, and my 10 years here at Xilinx, it was the best 'RIF' I have ever seen, done in a fashion which is consistent with Xilinx values, in which respect for the employees is held very dear. Ever heard of what any of the tel/com/ companies did? Still do? Yet, Xilinx is a business, and has stockholders: there are certain realities in this world we can not choose to ignore. I will verify that those who worked for me were excellent people, and if I had a position for them, I would hire them back in an instant. AustinArticle: 132695
Gabor, I believe they have a new memory technology, where they can OTP the device, and then even after that, they can reload a bitstream into SRAM. Thus, you may prototype by just downloading streams until it is correct, and then do the OTP step to "freeze" that stream in place. This avoids the traditional OTP (fuse) problem of wasting parts until you get it right. It also allows you to test the parts before you ship them (unlike fuse FPGAs). They have a number of ex-X employees working there. Good luck guys (I mean it)! AustinArticle: 132696
On Jun 5, 11:14 am, Peter Alfke <pe...@xilinx.com> wrote: > On Jun 5, 7:31 am, Frank Buss <f...@frank-buss.de> wrote: > > > > > Jon Beniston wrote: > > > Profits up by 7% then staff down by 7%. Presumably will be followed by > > > large executive level bonuses. How can your company still be > > > advertising jobs? > > > Assuming Xilinx doesn't want to reduce the staff even more, it is just some > > mathematic: 7% for 250 jobs means Xilinx has about 3500 people. If everyone > > works some 20 years and then go into retirement or changes the job, Xilinx > > needs about one new employee every two days to keep the staff number at the > > same level. > > > Using this calculation, I wonder why they cut the jobs, because not > > employing new people for about 2 years would have the same result. > > > -- > > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de > > Interesting theory, but we first have to get rid of sexual > propagation, and institute massive cloning, > so that all employees have the same brain cells, and then also receive > the same experience and education. > Really make them interchangeable. > Brave New World... > Peter Alfke Peter, There are just some posts that are better left without responses. I think Frank's was one of those. I have seen layoffs of just 2% of a workforce. Of course, it was followed by more layoffs of 2%, 4% and 5%. But I don't see that happening with the FPGA companies... at least not yet. RickArticle: 132697
On Jun 5, 7:24 am, FP <FPGA.unkn...@gmail.com> wrote: > I would like some suggestions on interfacing the Xilinx Spartan3 > device with a DDR SDRAM. The idea is to build a controller that will > set up the DDR-SDRAM so that I can do a burst read of a page of data > into a block of internal SRAM (dual port). > > Your help is appreciated Xilinx has several design examples on their web site. A google search turns up a few more on various sites. You do know about burst length limitations with DDR devices? You can't burst a full page. G.Article: 132698
PFC <lists@peufeu.com> wrote: >>> So I thought about Spartan-3A DSP but it has a packaging problem : >>> 0.8mm BGA ! No way. 1mm is fine but not 0.8mm. >> >> What's the big deal? I'm no expert, but is 0.8mm that much more >> difficult to deal with than 1.0? > > It adds a lot to board cost. This is a hobby project, lol. > >>> Also this board will be used as part of an open source project. >>> We'll make a board fab run and sell them so people can hack them. >> >> Interesting. Are you planning to sell blank boards or stuffed ones? Will >> the PCB database be open source, or just gerber files? What particular >> audio applications do you think people would use it for? > > Stuffed, I doubt people would want to solder the BGA... > Open source, > And multichannel remote audio soundcard with DSP capabilities. > One of the guys is more interested in recording capabilities and I'm more If you are going to do multi-channel audio, Xilinx may have the advantage that you can use the LUTs as 16x1 memory instead of flipflops. If you want to process up to 16 channels, you can use luts as temporary storage for filter results etc. The space savings can be huge. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 132699
"FP" <FPGA.unknown@gmail.com> wrote in message news:c1b1e317-7bf9-48ad-af6f-4d46444e4c7a@a1g2000hsb.googlegroups.com... >I would like some suggestions on interfacing the Xilinx Spartan3 > device with a DDR SDRAM. The idea is to build a controller that will > set up the DDR-SDRAM so that I can do a burst read of a page of data > into a block of internal SRAM (dual port). > > Your help is appreciated STW or at least Xilinx's website. http://www.xilinx.com/products/devkits/HW-SPAR3ADDR2-DK-UNI-G.htm
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