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Jan pisze: > Dear all, > > I'm trying to map two 16bit wide buses into one 32 bit wide bus. > I can't get the syntax right though. > > How do I connect the bits (15 downto 0) from bus16a to bus32 (15 downto > 0) and bits (15 downto 0) from bus16b to bus32 (31 downto 16)? > > My VHDL: > > architecture Behavioral of bus_test is > > component bus16 is > port ( > data16 : out std_logic_VECTOR(15 downto 0); > ); > end component; > > component bus32 is > port ( > data32 : in std_logic_VECTOR(31 downto 0); > ); > end component; > signal ibus32 : std_logic_vector(31 downto 0); > begin > bus16a_inst : bus16 > port map (data16=>ibus32(15 downto 0 ) ); > > bus16b_inst : bus16 > port map ( data16=>ibus32(31 downto 16) ); > > bus32_inst : bus32 > port map ( data32=>ibus32 ); > > end; > > Thank you in advance! > > regards > Jan AdamArticle: 135851
On Oct 17, 10:04=A0am, Jan <webpjat@future-design_DELETE.dk> wrote: > Dear all, > > I'm trying to map two 16bit wide buses into one 32 bit wide bus. > I can't get the syntax right though. > > How do I connect the bits (15 downto 0) from bus16a to bus32 (15 downto > 0) and bits (15 downto 0) from bus16b to bus32 (31 downto 16)? > > My VHDL: > > architecture Behavioral of bus_test is > > =A0 =A0component bus16 is > =A0 =A0 =A0port ( > =A0 =A0 =A0 =A0 =A0 =A0data16 : out std_logic_VECTOR(15 downto 0); > =A0 =A0 =A0 =A0 =A0 ); > =A0 =A0end component; > > =A0 =A0component bus32 is > =A0 =A0 =A0port ( > =A0 =A0 =A0 =A0 =A0 =A0data32 : in std_logic_VECTOR(31 downto 0); > =A0 =A0 =A0 =A0 =A0 ); > =A0 =A0end component; > > begin > =A0 =A0 bus16a_inst =A0: bus16 > =A0 =A0 =A0 =A0port map ( ); > > =A0 =A0 bus16b_inst =A0: bus16 > =A0 =A0 =A0 =A0port map ( ); > > =A0 =A0 bus32_inst =A0: bus32 > =A0 =A0 =A0 =A0port map ( ); > > end; > > Thank you in advance! > > regards > =A0 =A0Jan Make a 32-bit signal to describe the 32-bit bus, and in the port mappings for the 16-bit components, call out which bit slices you want to connect to each component, like port map(bus_16bit =3D> bus_32bit(15 downto 0)); In the future, you should probably post VHDL-specific questions in comp.lang.vhdl rather than in comp.arch.fpga And you should also research bit-slicing - it's a very important concept in VHDL. DaveArticle: 135852
Dave wrote: > In the future, you should probably post VHDL-specific questions in > comp.lang.vhdl rather than in comp.arch.fpga > Dave Sorry, my mistake! JanArticle: 135853
On Fri, 17 Oct 2008 00:52:22 -0700 (PDT), Fred <fred__bloggs@lycos.com> wrote: >The output MLT-3 is also >feasible. For some reason the IEEE 802 docs don't mention MLT-3 >either, I suspect it's in there under another description. > Yes, MLT-3 is described in TP-PMD not in 802.3. And MLT-3 output has some relatively strict slew control requirements so it would be difficult to generate a compliant signal if that's something important. >I accept that the driver for the line and magnetics has to be snappy, >but was trying to get away from buying a PHY when all the other things >can be done in the FPGA. In essence it would be nice to have an >example stream to start with, even just in waveform. The notes I read >so far is that different scrambling is used for idle and I need to >read up more about it. > Not really. There is 4b/5b encoding to go from 4 bits at 25 MHz (ie 100mb/s) and then there is a scrambler at 125 MHz. This scrambler is a self-synchronizing one and there is no CRC associated with it. At 4bit stage if there is no packet data (ie if MAC is not sending anything) a 5 bit IDLE code is inserted in the bitstream continuously. >I do know I have an obvious source of data, ie a real ethernet adaptor >but it's not the same as a waveform down on paper, explaining what is >scrambled, when and how. They are also very fussy in only accepting >data with a correct checksum! The checksum is only at the MAC packet level so it's still the same as that in the 10bt standard. After you assemble the packet correctly you send it down to be processed for 100b-tx signalling. HTH. Muzaffer Kal ASIC/FPGA Design Services DSPIA INC. http://www.dspia.comArticle: 135854
In the Core Generator there are 2 separate Aurora IPs: "GTP Aurora 2.8" and "Virtex-5 Aurora 3.0". Both work with Virtex 5 LXTs so which one is the best to use? Presumably the "Virtex 5" version, is this right? What's the difference anyway? In my project several dual tiles will be used, clocked via the GTP Dedicated Clock Routing from 2 sources. How is the clock routing set-up? Once set it'll never be changed. Do the RefClk_Sel0,1,2 and ClkNorth, ClkSouth bits have to be set using the DRP?! or is there a simpler way? TIA Roger.Article: 135855
aleksa wrote: >>So are you saying this works on some targets, but not others, >>and it works on small examples, but not larger ones ? > > > Yes. > > Please test this on XC3S50 TQFP144 and then on XC2S50 TQFP144: <snip>> > > That should show that it works on S3 but fails on S2. > > As for the "and it works on small examples, but not larger ones" > remove the comment on attribute lines and it will work on S2 > (but not on S3). > I'm not at liberty to show the complete design, however. > > BUFGP is probably a bad idea, anyway. > > > >>You can check the code is ok, by splitting >>the offending signal to two pins, and then RST use >>of the Clock is removed. >> >>If the tools (or silicon) still refuse to co-operate fully, >>you can always join two pins :) > > > That is what I was doing from the start (see s and c version) > but wanted to have only one pin with the SAME SIGNAL. > > Since I'm meeting too much resistance, two pins-same signal > is the way to go.. Sometines that happens... :) Send it to Xilinx with examples on when it does, and does not, work and it will eventually get fixed.... -jgArticle: 135856
On Oct 16, 10:03=A0am, aleksa <aleks...@gmail.com> wrote: > if falling_edge(clock2) then > =A0 =A0 =A0 =A0 out2 <=3D data2; > end if; > > if clock2=3D'0' then out1 <=3D 'Z'; > elsif falling_edge(clock1) then out1 <=3D data1; > end if; > > (This is just a sample VHDL) > > Clock2 is used both as a GCK and as a signal. > > ISE (10.1) complains on Spartan 2. > > I've tried replacing clock2 with clock2a: > =A0 =A0 =A0 =A0 signal clock2a : STD_LOGIC; > > =A0 =A0 =A0 =A0 component ibufg port ( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 O : out STD_LOGIC; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 I : in =A0STD_LOGIC); > =A0 =A0 =A0 =A0 end component; > > =A0 =A0 =A0 =A0 attribute box_type : string; > =A0 =A0 =A0 =A0 attribute box_type of ibufg : component is "black_box"; > > =A0 =A0 =A0 =A0 temporary : ibufg port map (I =3D> clock2, O =3D> clock2a= ); > > From the manual: "The IBUFG can be routed to your choice of logic > to allow the use of the dedicated clock pins for general logic." > Am I using it the correct way? > > I've also tried variations of buffer_type, no luck either. > =A0 =A0 =A0 =A0 attribute buffer_type: string; > =A0 =A0 =A0 =A0 attribute buffer_type of clock2: signal is "bufgp"; > > Even if I get it to work on this small example, ISE always > complains on the complete project. > > Currently, I connect clock two 2 pins, GCK and a IOB, but this > can probably be avoided. How? First, what do you mean by "complains"? ISE throws lots of warnings that can be ignored if you know what you're doing. For example, your dual use of a global clock input will result in non-optimal routing for use as a logic input. However if you can deal with the additional delay you can ignore the warning. You can check with FPGA editor to see how the signal is routed. In spartan 2, routing a global signal to a LUT or flip-flop input requires the use of a switch box near the edge of the die. This is very bad if the flip-flop or LUT is in a cell in the middle of the die. You can however instantiate the IBUFG followed by a BUFG in spartan 2. It's not intuitive, but an IBUFG in these parts is not a global buffer, just an input buffer of a type only available on the dedicated global clock input pins. The output of the IBUFG can route to logic as well as the input of the BUFG. This should reduce your warnings and help with routing delays. You can also build a clocked structure to take global clock signals in a Spartan 2 located anywhere in the die and make them usable for fabric logic. This structure consists of two flip-flops and an exclusive OR gate. for example: if rising_edge (global_clock_net) then flop1 <=3D NOT flop2; if falling_edge (global_clock_net) then flop2 <=3D flop1; So after the rising edge of the clock, flop1 and flop2 will be different. After a falling edge of the clock flop1 and flop2 will be the same. Then the XOR of flop1 and flop2 reproduces the global_clock_net with some delay that is based on the clock to Q and LUT delays of the fabric, but not on the routing distance to the edge of the die. Regards, GaborArticle: 135857
Hello, please can someone tell me if is possible to configure a Spartan 3 XC3S1500 from a common parallel flash memory as M29W160(16 Mb)? I'm able to program in circuit the flash by means of a cpld and the parallel port of my pc, in xapp137 a similar application,referred to Virtex fpga is showed,Are there links about an analog method applied to Spartan3 family? Many thanks DiegoArticle: 135858
muthu...@gmail.com wrote: > Hi, > > My design uses Synchronous reset for all the Flip-Flops. When I > Synthesis and see the "Technology view" schematics in Synplify_pro; > some FFs are infered using FDR and some used FD primitives. FDR - Has > Synchronous reset input. FD - Do not have Synchronous reset input, and > the Reset is added in the "D" path of FD primitive. > > Why such differences? > > I have read in some places that Xilinx recommend Synchronous reset for > high performance. What is this mean, if FD is used in some places and > having Reset in "D" path of the Flip-flop. > > Please clarify. > > Thanks in advance, > Muthu Having the reset in the logic cone feeding the D input is still synchronous! It's a matter of optimization. The synthesis in SynplifyPro doesn't appear to be written to push strongly for the sync reset whereas other synthesizers might try to force the issue. As long as your synchronous reset is dominant, there shouldn't be a logic reason to keep things separate. If you have some critical paths, however, there could be improvements by optimizing these paths into their own control over FDR, FDRS, FDE primitives, etc., but not an FD. There's an attribute to try to force the clock enable - syn_direct_enable - but no equivalent for reset. Aside from some registers able to pack together and some not, do you believe there's any functionality difference? The reset is still distributed with general routing resources so there's no advantage from global reset resources, for instance. - John_HArticle: 135859
Fred wrote: > On 17 Oct, 05:56, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: >> On 2008-10-17, Fred <fred__blo...@lycos.com> wrote: >> >>> scrambled, when and how. They are also very fussy in only accepting >>> data with a correct checksum! >> I was trying to debug an ethernet interface five years ago or so. At >> that time I wasn't sure if I was sending the correct CRC or not. To >> make a long story short, I modified the Linux driver for my Ethernet card >> so that it ignored the bad CRC bit. In that way I managed to look at my >> packets even though I normally wouldn't. >> >> Not that it helped though, my CRC was still bad and I still needed to >> figure out the correct way to send the CRC :) But perhaps this can be of >> some help to you while debugging your solution. >> >> /Andreas > > I have found some software Colasoft Packet Builder which nicely tells > you what the checksum would be. I have already done this for 10Base-T > and generate packets in the FPGA and drive a fast RS485 driver IC. > However 100Base-TX is somewhat more complex, with it's scrambling and > 4B/5B encoding. > > I'm not familiar with Linux and use Windows <ducks to avoid remarks> > We can only be expert in so many things at once! > > I don't really want to throw in the towel and buy PHYs! > > Many thanks for your reply. Hi Fred, Having worked at National in 10/100/1000BT PHY line, I would recommend you getting a PHY and avoid headaches. Even if you could get it to communicate, you'll run into issues when things change: even a new or longer/shorter cable will make your connection unreliable. my .02c Cheers, -P@Article: 135860
Hello, we are thinking of implementing linux on the PPC core of the FXT family. It would need to run quite sophisticated stuff at high datarates on one core and DSP alike functions at same high rates on the other core. I would implement 2 separate blocks of DDR2 memory and a big flash device for processor code (and configuration too). How much memory (DRAM and Flash) is required to run this application smoothly? Thanks, LucArticle: 135861
I have a B.S.E.E. with basic vhdl/verilog knowledge and currently unemployed. I'm trying to break into the industry and need advice getting/looking for an entry-level fpga job. I'm considering taking some fpga classes from xilinx to give me an edge, but not sure if the material covered will be worth the cost. I was also thinking of working on my own fpga projects to have my resume/ skillset stand out. Does anyone have some advice breaking into the fpga engineering industry? Also, it seems like plenty of entry level engineering/programming jobs are being outsourced to India/China. Is this true for fpga jobs as well? side note: as far as working on my own fpga projects I am interested in: cell phone technology wireless technology video/audio processing sonar/radarArticle: 135862
On 18 Okt., 01:38, "blisca" <bliscachiocciolinatiscalipuntoit> wrote: > Hello, > please can someone tell me if is possible to configure a Spartan 3 XC3S1500 > from a common parallel flash memory as M29W160(16 Mb)? > > I'm able to program in circuit the flash by means of a cpld and the parallel > port of my pc, > in xapp137 a similar application,referred to Virtex fpga is > showed,Are there links about an analog method applied to Spartan3 family? > > Many thanks > > Diego I'm will probably work as is with the spartan3, the current Xilinx fpgas are very similar when it comes to configuration. -LasseArticle: 135863
On 18 Okt., 09:42, lbrae...@gmail.com wrote: > It would need to run quite sophisticated stuff at high > datarates on one core > How much memory (DRAM and Flash) is required to run this application > smoothly? I think that for quite sophisticated stuff exactly some GBs or more should be OK. Maybe you can modify the algorithm so that it only is somewhat sophisticated to get away with less memory. For really sophisiticated stuff you need more, of course. Regards, KoljaArticle: 135864
On Oct 17, 4:33=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > On Fri, 17 Oct 2008 00:52:22 -0700 (PDT), Fred > > <fred__blo...@lycos.com> wrote: > >The output MLT-3 is also > >feasible. =A0For some reason the IEEE 802 docs don't mention MLT-3 > >either, I suspect it's in there under another description. > > Yes, MLT-3 is described in TP-PMD not in 802.3. And MLT-3 output has > some relatively strict slew control requirements so it would be > difficult to generate a compliant signal if that's something > important. > Thanks for the info, I'm surprised it's not included in the 802.3 specs. To be honest, I don't feel limiting slew is going to be important, obtaining enough may be! We'll also be using off the shelf magnetics. > >I accept that the driver for the line and magnetics has to be snappy, > >but was trying to get away from buying a PHY when all the other things > >can be done in the FPGA. =A0In essence it would be nice to have an > >example stream to start with, even just in waveform. =A0The notes I read > >so far is that different scrambling is used for idle and I need to > >read up more about it. > > Not really. There is 4b/5b encoding to go from 4 bits at 25 MHz (ie > 100mb/s) and then there is a scrambler at 125 MHz. This scrambler is a > self-synchronizing one and there is no CRC associated with it. At 4bit > stage if there is no packet data (ie if MAC is not sending anything) a > 5 bit IDLE code is inserted in the bitstream continuously. > I've come across 4b/5b encoding elsewhere and don't feel it's going to be an issue, the legal codes, the Start and End of Stream Delimiter should be easy to code. Not sure what you mean by self-synchronizing. This is something I need to look into further. I though the 5 bit idle code was all 1's but that these were also scrambled? > >I do know I have an obvious source of data, ie a real ethernet adaptor > >but it's not the same as a waveform down on paper, explaining what is > >scrambled, when and how. =A0They are also very fussy in only accepting > >data with a correct checksum! > > The checksum is only at the MAC packet level so it's still the same as > that in the 10bt standard. After you assemble the packet correctly you > send it down to be processed for 100b-tx signalling. > I've already got a 10Base-T system up and running so feel this part ought to be lower risk!! Many thanks for your thoughts.Article: 135865
> However if you can deal with the additional delay
> you can ignore the warning.
I just don't like to see any warnings from ISE.
The warning is (was):
MapLib:95 - IBUF symbol "RD_IBUF" (output signal=RD_IBUF1)
is promoted to indicate the use of GCLKIOB site.
> You can also build a clocked structure to take global clock
> signals in a Spartan 2 located anywhere in the die and make
> them usable for fabric logic. This structure consists of two
> flip-flops and an exclusive OR gate.
This is great! Thanks Gabor! I've built this clocked structure
and it works fine now.
As for the IBUFG + BUFG..
I've read about that before, but there were
no VHDL examples, and my tests have failed.
Can you change the following code to use IBUFG + BUFG:
----------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is Port (
DBUS : out STD_LOGIC;
clock1 : in STD_LOGIC;
clock2 : in STD_LOGIC;
data1 : in STD_LOGIC;
data2 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end test;
architecture Behavioral of test is
begin
process (clock1, clock2)
begin
if falling_edge(clock2) then
out2 <= data2;
end if;
if clock2='0' then out1 <= 'Z'; -- this line you must change
elsif falling_edge(clock1) then out1 <= data1;
end if;
end process;
DBUS <= data1 when clock2='0' else 'Z'; -- and also this one
end Behavioral;
----------------------------------------
Article: 135866Andreas Ehliar wrote: > Most of our students do some small microcoded CPU as their project in this > course. Typically at least two CPLDs are used. One CPLD for the microcode and > one for the ALU plus some registers like an accumulator and a program counter. Depending on how far you push them, one pathway we looked at for CPLD education etc was to start with the venerable MC14500, which was a boolean CPU from Motorola, and the core alone fits in ~8 macrocells. [Did anyone ever see a commercial design using this?] This naturally leads onto IEC61131 Instruction List (IL). Full-blown IL is rather type agnostic, and has an inferred stack, but you can chose a single type to keep the HW simpler. The Maxim MAX1464 is a Sensor interface, with a very simple CPU which closely models IEC61131-IL, mapped onto 16 registers. Has a 4 bit OpcodeID field, and a 4 bit register field, in a 8 bit opcode. I think Maxim have assemblers for this simple core. -jgArticle: 135867
On Sat, 18 Oct 2008 13:33:33 -0700 (PDT), Fred <fred__bloggs@lycos.com> wrote: >> Not really. There is 4b/5b encoding to go from 4 bits at 25 MHz (ie >> 100mb/s) and then there is a scrambler at 125 MHz. This scrambler is a >> self-synchronizing one and there is no CRC associated with it. At 4bit >> stage if there is no packet data (ie if MAC is not sending anything) a >> 5 bit IDLE code is inserted in the bitstream continuously. >> > >I've come across 4b/5b encoding elsewhere and don't feel it's going to >be an issue, the legal codes, the Start and End of Stream Delimiter >should be easy to code. > Yes, there is nothing interesting about the encoding in the transmitter. >Not sure what you mean by self-synchronizing. This is something I >need to look into further. > Sorry about the confusion, I meant that the descrambler at the receiver is self-synchronizing. The scrambler at the transmitter is just a standard scrambler. >I though the 5 bit idle code was all 1's but that these were also >scrambled? Yes the idle code is 5 bits of 1 which is inserted in between actual packet data encoded with 4b5b. Then the resulting 125 Mb/s bit stream is scrambled and mlt-3 encoded before being driven to the wire. Muzaffer Kal ASIC/FPGA Design Services DSPIA INC. http://www.dspia.comArticle: 135868
cid <nihonshuu@gmail.com> wrote: >I have a B.S.E.E. with basic vhdl/verilog knowledge and currently >unemployed. I'm trying to break into the industry and need advice >getting/looking for an entry-level fpga job. > >I'm considering taking some fpga classes from xilinx to give me an >edge, but not sure if the material covered will be worth the cost. I >was also thinking of working on my own fpga projects to have my resume/ >skillset stand out. I'd rather hire someone that has build some projects in his/her spare time than someone who followed some classes. Perhaps in your case it is good to do both. Also do some investigation on which hdl (vhdl or verilog) is most popular in the area you live in so you can focus on that. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 135869
Finally found out how to do it. You have to use the I/O elements when specifying the TNMs for the clock domains you want to be unrelated : NET "clkin_IBUFG" TNM_NET="clock_system"; # instead of NET "clkin" NET "pci_clk_OBUF" TNM_NET="clock_pci"; # instead of NET "pci_clk" TIMESPEC "TSpci_async1"=FROM "clock_system" TO "clock_pci" TIG; TIMESPEC "TSpci_async2"=FROM "clock_pci" TO "clock_system" TIG; No idea why, though.Article: 135870
<langwadt@fonz.dk> ha scritto nel messaggio news:e73d5674-a807-467e-abcf-018e4a1dcf64@q9g2000hsb.googlegroups.com... > On 18 Okt., 01:38, "blisca" <bliscachiocciolinatiscalipuntoit> wrote: > > Hello, > > please can someone tell me if is possible to configure a Spartan 3 XC3S1500 > > from a common parallel flash memory as M29W160(16 Mb)? > > > > I'm able to program in circuit the flash by means of a cpld and the parallel > > port of my pc, > > in xapp137 a similar application,referred to Virtex fpga is > > showed,Are there links about an analog method applied to Spartan3 family? > > > > Many thanks > > > > Diego > > I'm will probably work as is with the spartan3, the current Xilinx > fpgas are very similar when it comes to configuration. > > -Lasse ThanksArticle: 135871
Dear all,
What are the smartest way to make a solo FPGA project capable of field
updates? I'm very new in the FPGA world so I don't much about the
practical use of them. Normally when I uses microcontrollers I make them
updateble via USB, serial or SD cards.
What techniques are possible when I want to avoid having a uP in the
project.
My target is a Xilinx Spartan 3A or 3AN
Regards
Jan
Article: 135872Hi, I started learning FPGA's and Verilog and seem to run into problems every day :-) I'm trying to use dual-port RAM for buffering data between a serial link and a 32-bit CPU bus. I wrote two separate always blocks, one which receives data from the serial link and writes it in RAM and another one which talks to the CPU bus and allows reading of the RAM. When I try to compile this design (using quartus ii), the compiler "never" finishes and I believe it's trying to build the RAM array out of logic gates. If I make the RAM small enough, the compiler succeeds (although it takes a long time). I did a similar thing for serial link transmission and it worked as expected (and the compiler used real RAM for the buffer, not logic gates). Is it wrong to access the same memory in two separate always blocks? The serial link and the CPU bus are independent and the bus has no clock, so I'm trying to make an async design. I'm getting no error messages about RAM from the compiler, so I'm not sure what I'm doing wrong. (Quartus II is usually pretty verbose, complaining about everything from unused pins to the color of my socks, but this time it isn't helping at all.) I would try putting the RAM stuff inside one always block, but it seems a bit difficult to do.. (or, I still can't think FPGA - my brain always seems to enter software mode when opening a text editor). I'd appreciate pointers or examples which would get me unstuck. ;-) Thanks, -jmArticle: 135873
Jan wrote: > Dear all, > > What are the smartest way to make a solo FPGA project capable of field > updates? I'm very new in the FPGA world so I don't much about the > practical use of them. Normally when I uses microcontrollers I make them > updateble via USB, serial or SD cards. > > What techniques are possible when I want to avoid having a uP in the > project. > > My target is a Xilinx Spartan 3A or 3AN You may find it very hard to safely avoid a uC entirely. If your power can fail at any time, you need to avoid a path-of-no-return. That might mean two copies in the loader memory, one default boot copy, and a second runable-if-ok copy. -jgArticle: 135874
Jan <1@2.3> wrote: >Dear all, > >What are the smartest way to make a solo FPGA project capable of field >updates? I'm very new in the FPGA world so I don't much about the >practical use of them. Normally when I uses microcontrollers I make them >updateble via USB, serial or SD cards. > >What techniques are possible when I want to avoid having a uP in the >project. > >My target is a Xilinx Spartan 3A or 3AN It is possible to do partial (re-) configuration on Xilinx devices through JTAG. However I don't know if the FPGA could program itself. Xilinx has some application notes on this subject. If it turns out to be possible, you can have a small amount of logic (for example includign a picoblaze cpu) which can load the rest of the FPGA from configuration memory and update this memory through a serial port (the picoblaze package comes with a UART). -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)
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