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Hi im using EDK 9.1i
when i give Generate libraries and BSps in SDK im getting this error
Running post_generate for OS'es, Drivers and Libraries ...
ERROR:MDT - standalone () - child process exited abnormally
while executing
"exec bash -c "$archiver -d ../../lib/libxil.a
_interrupt_handler.o""
(procedure "::sw_standalone_v1_00_a::post_generate" line 14)
invoked from within
"::sw_standalone_v1_00_a::post_generate 38539448"
ERROR:MDT - Error while running "post_generate" for processor
microblaze_0...
make: *** [microblaze_0/lib/libxil.a] Error 2
Done!
Can any1 tell me what this is..........??????
It also pops up a message like this..
"The procedure entry point_argz_count could not be located in dynamic
link library cygwin1.dll"
I had an earlier cygwin version installed, but i copied everything
from EDK cygwin to my cygwin home directory now...
Article: 135926On 2008-10-22, Tobias <tobi_wan@gmx.de> wrote: > Does anyone of you know of any other design security supporting fpgas i > might have missed? Virtex-II and Virtex-II Pro also supports bitstream encryption. Actel also claims that many of their other devices are hardened against reverse engineering, for example their antifuse based devices. /AndreasArticle: 135927
i know its is not so interesting to everyone...Article: 135928
On Tue, 21 Oct 2008 16:54:03 -0700 (PDT), Jeff Brower <jbrower@signalogic.com> wrote: >All- >When we look at the Pad Report, we can't see any pins other than 3.3V >(with exception of pre-defined VCCINT, VCCO_X, and VCCAUX pins). >There are no LVCMOS25 pins listed. In the .ucf file, we did not >define any LVCMOS25 pins and included IOSTANDARD = LVCMOS33 for all >used pins. Try the mapper report file (.mrp) which should list all the I/O pins including their I/O standards near the end of the file. - BrianArticle: 135929
Hello newsgroup,
currently I'm trying to create an overview on fpgas (and to a lesser
extent cplds) that support "design security" in some way, thereby
preventing cloning/reverse engineering. The mechanisms mostly used are
security bits/disable readback on non-volatile fpgas and encrypted
bitstreams on volatile fpgas. So far I have found the following:
Actel: ProASIC3, ProASICplus
Altera: Stratix 2-4, Max2
Xilinx: CollRunner 2, Virtex 4-5, Spartan 3AN
Lattice: ispXPGA, ECP2/ECP2M
Does anyone of you know of any other design security supporting fpgas i
might have missed?
Thanks in advance.
Best Regards,
Tobias
Article: 135930Tobias <tobi_wan@gmx.de> wrote in news:gdn6s3$b7s$1@news.ett.com.ua: > Hello newsgroup, > > currently I'm trying to create an overview on fpgas (and to a lesser > extent cplds) that support "design security" in some way, thereby > preventing cloning/reverse engineering. The mechanisms mostly used are > security bits/disable readback on non-volatile fpgas and encrypted > bitstreams on volatile fpgas. So far I have found the following: > > Actel: ProASIC3, ProASICplus > Altera: Stratix 2-4, Max2 > Xilinx: CollRunner 2, Virtex 4-5, Spartan 3AN > Lattice: ispXPGA, ECP2/ECP2M > > Does anyone of you know of any other design security supporting fpgas i > might have missed? > > Thanks in advance. > > Best Regards, > Tobias > Virtex 2 Pro, but only with special order codes originally. I understand the regular order code was the same die, but with the security feature untested. About half a year ago they removed the special order code, and all parts now support the security feature. Regards, AllanArticle: 135931
I want to use 14 GTPs on a Virtex 5 each running a separate Aurora interface. The Aurora code from Coregen produces a clock_module process amongst all the others which contains a DCM. Previous experience of Virtex II Pro implementations allowed 1 clock module to be used with multiple Auroras. The Virtex 5 clock module is different in that it takes its clock input from the GTP Dual PLL together with a Lock signal. What's the best approach in this situation? A) Use 1 clock_module (DCM) per GTP_Dual i.e. 2 Auroras B) Use 1 clock_module for all the Auroras with it being driven from one arbitrary GTP (same idea as the Virtex II Pro days). C) Use 2 clock_modules for the top and bottom GTPs, again driven arbitrarily from 1 GTP in each half. Any help gratefully received. Roger.Article: 135932
Hello ! I have created an interface between sfifo and sopc avalon MM slave.The interface is just realized by define the avalon MM slave signals are outside the niosii cpu. The 32x32 sfifo was created using altera megafunction(optimzed by area,with overflow and empty protection),the device i use ia cyclonII EP2C20. I define the IORD and IOWR macO(just the same as the way to visit the avallon MM SLAVE component inside the nios cpu) to write and read the sfifo in nios IDE, but i alwayse read zero, with the embeded sigtap logic analyzer, ,i found the sinals from the avalon MM slave interface which is outside the nios cpu are good(write,read ,chip-select,address,writedata),but the output of the sfifo(q and usedw) are always zero,no matter the times that i write and read in nios IDE!! I DON'T know why ,i need your help. please contact my eamil: zhenyujiel@yahoo.com.cn ,thank you!Article: 135933
On Oct 22, 7:25=A0am, knight <krshe...@gmail.com> wrote: > i know its is not so interesting to everyone... You could have an old copy of the cygwin DLL in your windows system32 directory. Did you "install" the EDK cygwin or just copy the files?Article: 135934
On Oct 21, 8:43 pm, hanumaa...@gmail.com wrote: > Hi, Im new to DSP stuff and have a very simple question. > > Since the multiplier in virtex 5 dsp is 2's complement ... does that > mean when using the std_logic_unsigned library, the maximum number of > bits A input can have is 24 instead of 25 and 17 instead of 18 for B > input? > > Whereas I can use 25 bits for A and 18 for B by using the > std_logic_signed library? > > thanks. In the Virtex 5 FPGA XtremeDSP Design Considerations document, it's stated that unsigned multiplication is performed by setting the MSB of the inputs to 0, thus only giving you 24 and 17 bits. Regardless of which library you use, that is the hard limit for each multiplier, but you can perform larger unsigned multiplies if you're willing to build them out of multiple XtremeDSP slices or the general FPGA logic fabric, though of course you'll consume a lot of generic logic to produce multipliers. The logic synthesizer will infer the number of multipliers required to implement a given multiply operation as defined in your VHDL so you don't have to restrict the size of the operands, though of course you should be aware of your resource usage. Darol KlawetterArticle: 135935
On Oct 19, 11:45 am, Jukka Marin <jma...@pyy.embedtronics.fi> wrote: > Hi, > > I started learning FPGA's and Verilog and seem to run into problems every > day :-) > > I'm trying to use dual-port RAM for buffering data between a serial link > and a 32-bit CPU bus. I wrote two separate always blocks, one which > receives data from the serial link and writes it in RAM and another one > which talks to the CPU bus and allows reading of the RAM. > > When I try to compile this design (using quartus ii), the compiler "never" > finishes and I believe it's trying to build the RAM array out of logic > gates. If I make the RAM small enough, the compiler succeeds (although > it takes a long time). > > I did a similar thing for serial link transmission and it worked as expected > (and the compiler used real RAM for the buffer, not logic gates). > > Is it wrong to access the same memory in two separate always blocks? The > serial link and the CPU bus are independent and the bus has no clock, so > I'm trying to make an async design. I'm getting no error messages about > RAM from the compiler, so I'm not sure what I'm doing wrong. (Quartus II > is usually pretty verbose, complaining about everything from unused pins > to the color of my socks, but this time it isn't helping at all.) > > I would try putting the RAM stuff inside one always block, but it seems a > bit difficult to do.. (or, I still can't think FPGA - my brain always > seems to enter software mode when opening a text editor). > > I'd appreciate pointers or examples which would get me unstuck. ;-) > > Thanks, > > -jm I can't see your code, but I can imagine that Quartus would have a hard time with the memory split between two blocks. Two things to try: 1) Make the memory very very small, (small enough to complete) and look at the results. 2) Instantiate a dual port memory directly, get the rest of the code working, then go back and try inferred RAM. Alex. From rgaddi@technologyhighland.com Wed Oct 22 09:43:21 2008 Path: flpi142.ffdc.sbc.com!flpi088.ffdc.sbc.com!prodigy.com!flpi089.ffdc.sbc.com!prodigy.net!newshub.sdsu.edu!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local02.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 22 Oct 2008 11:43:18 -0500 Date: Wed, 22 Oct 2008 09:43:21 -0700 From: Rob Gaddi <rgaddi@technologyhighland.com> Newsgroups: comp.arch.fpga Subject: Re: Virtex 5 DSP. Message-Id: <20081022094321.b200dea6.rgaddi@technologyhighland.com> References: <a0cb5eb6-0638-40e4-8f04-f1684cbc161e@u40g2000pru.googlegroups.com> <gdmhrc$soj$1@aioe.org> Organization: Highland Technology, Inc. X-Newsreader: Sylpheed 2.5.0 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 26 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-4JFDZp1JhZ1bd01AXy0a8zGKQJJmqM8mHpOKXjNMsmodOcdZm1i/Gcxy2xLE1pMmRWp4xFCfboIIwCS!Hq4KsfGvLJTJqKs63UNZRY+cADe+GuK/fk5e+NhAWkoeg4Jbc8aJ0a/6lF0BZ6a7ILH5d3NLBRH8!Pv0vYy6L8/ToTqB6EnQ= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: prodigy.net comp.arch.fpga:148801 X-Received-Date: Wed, 22 Oct 2008 12:43:20 EDT (flpi142.ffdc.sbc.com) On Wed, 22 Oct 2008 07:39:23 +0100 "Symon" <symon_brewer@hotmail.com> wrote: > > <hanumaan81@gmail.com> wrote in message > [snip] > > Dear 'new to DSP stuff', > > Although this doesn't answer your question, you should be using > numeric.std > > http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf > > HTH., Syms. > > Though this leads me back to a question that, while I'm sure it's been asked before, still confuses me. Does anyone know why Xilinx in both their documentation and auto-templatey-thingies continues to push people towards std_logic_arith and its kin rather than numeric_std? -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 135936
"Rob Gaddi" <rgaddi@technologyhighland.com> wrote in message news:20081022094321.b200dea6.rgaddi@technologyhighland.com... >> > > Though this leads me back to a question that, while I'm sure it's been > asked before, still confuses me. Does anyone know why Xilinx in both > their documentation and auto-templatey-thingies continues to push > people towards std_logic_arith and its kin rather than numeric_std? > Rob, http://www.safetycenter.navy.mil/Articles/a-m/monkeys.htm HTH., Syms.Article: 135937
Rob Gaddi wrote:
> Though this leads me back to a question that,
> while I'm sure it's been asked before,
Yes:
http://groups.google.com/groups/search?q=library+madness+zhiquan
> Does anyone know why Xilinx in both
> their documentation and auto-templatey-thingies continues to push
> people towards std_logic_arith and its kin rather than numeric_std?
1. Old habits die hard.
2. Old examples never die.
3. The margins on devices are better
than the margins on tools.
Actually, std_logic_arith is the least evil
of the old synopsis libraries, because it
at least allowed signed and unsigned vectors
to be used in the same expression.
It also left the std_logic_vector
comparison functions alone.
Problems arise when I try to use a
library like std_logic_signed
or std_logic_unsigned
that declare conflicting math and comparison functions
for std_logic_vector.
Details here:
http://www.vhdl.org/rassp/vhdl/guidelines/vhdlqrc.pdf
http://www.vhdl.org/rassp/vhdl/guidelines/1164qrc.pdf
-- Mike Treseler
Article: 135938On Oct 22, 4:18=A0am, Muzaffer Kal <k...@dspia.com> wrote: > On Tue, 21 Oct 2008 16:23:00 -0700 (PDT), Fred > > <fred__blo...@lycos.com> wrote: > >> Yes the idle code is 5 bits of 1 which is inserted in between actual > >> packet data encoded with 4b5b. Then the resulting 125 Mb/s bit stream > >> is scrambled and mlt-3 encoded before being driven to the wire. > >> Muzaffer Kal > > >> ASIC/FPGA Design Services > >> DSPIA INC.http://www.dspia.com > > >I'm rapidly coming to the conclusion that the purchase of a PHY, given > >their cost, might be a smart move. =A0Sad really because I would have > >liked to have coded the whole system in a FPGA. =A0A VHDL test bench > >would have been ideal!! > > Believe me that's the right choice. Also if you have to receive in > addition the transmitting, you have to deal with clock recovery and > equalization (not to mention blw correction) at the receiver which are > much more difficult problems than transmitting mlt3 signal. A 125 (or > 250 depending on how you do things) ADC probably at 8 bits (if you > have to do blw in digital) probably costs the same as a PHY so go with > that and save yourself a world of trouble. > I see DigiKey have a Micrel part for les than =A31 in 100s. Given the trouble I'd have to go to I'm convinced!! I doubt I'd need anything like an 8 bit device but as you say there's an awful lot of code which would need writing!Article: 135939
Muzaffer Kal wrote: (snip) > Sorry about the confusion, I meant that the descrambler at the > receiver is self-synchronizing. The scrambler at the transmitter is > just a standard scrambler. Well, there is a certain symmetry between the two. A self-synchronizing descrambler requires the appropriate logic in the scrambler. -- glenArticle: 135940
Fred wrote: (snip) > For some reason the IEEE 802 docs don't mention MLT-3 > either, I suspect it's in there under another description. http://en.wikipedia.org/wiki/MLT-3 As I understand it, it was borrowed from FDDI and so 802 just references the appropriate FDDI standard. -- glenArticle: 135941
Jim Granville wrote: (snip) >> circuit with built in NBCD decoder (the 9368), so if you want to compare >> your solution to mine you might want to output NBCD coded numbers out >> of your >> CPLD. > Surely the 9368 should be part of the CPLD ? If I remember the 9368, it has constant current outputs for direct drive to LED displays. If you can get them, it is probably easier than other ways to drive LEDs. Well, another choice is the 75491 and 75492, which still requires current limiting resistors, and I believe something like a 12V power supply. I still have a clock based on the NS5311 that I built many years ago. Six digit clocks are rare these days. -- glenArticle: 135942
If you really want a fixed delay using internal FPGA resources, I suggest
making a hard macro (.nmc file) using the "fpga_editor" command. You can
hand route it in fpga_editor and see what delays you are getting. It's not
too hard to do (after the first time) and you get to see at a very low level
how Xilinx FPGAs work.
This is not a compensated delay, so it will vary as the FPGA heats up, but
it will be stable over short times. Also expect jitter from other logic in
the fpga and ground bounce on the external pins. If you care about ps
jitter, use differential I/O and/or have nothing else in the FPGA.
Next option is one my favorite class of chips: time delay vernier chips such
as SY604.
Next is get a different FPGA, either newer Virtex-4 (IDELAY, 5 ns max) or
Startix-3/Cyclone-3 (altiobuf, 1.1 ns max) which have compensated variable
delay lines in their I/O pads. The way to make these work is to feed your
clock into two otherwise identical chains of delays, with one set to zero
and the other to 10 ns. Then use the 0 delay one as your new undelayed
clock. This removes the effects of the uncompensated routing delays. Still
this will be difficult to implement, since you want the tool to always
generate a consistent routing delay, which is hard to do.
I don't know about Xilinx, but you can ask for min and max routing delays
from pin to pin with Altera's TimeQuest. So a final easy thing to try is
use put a bunch of multi-input xor gates in series and try to constrain
them. Tie the unused inputs of the xor gates to separate input pins to
prevent the tool from optimizing them out (it doesn't know that you are
going to tie them all high externally).
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 135943Roger wrote: > I want to use 14 GTPs on a Virtex 5 each running a separate Aurora > interface. The Aurora code from Coregen produces a clock_module process > amongst all the others which contains a DCM. > > Previous experience of Virtex II Pro implementations allowed 1 clock > module to be used with multiple Auroras. The Virtex 5 clock module is > different in that it takes its clock input from the GTP Dual PLL > together with a Lock signal. > > What's the best approach in this situation? > > A) Use 1 clock_module (DCM) per GTP_Dual i.e. 2 Auroras > B) Use 1 clock_module for all the Auroras with it being driven from one > arbitrary GTP (same idea as the Virtex II Pro days). > C) Use 2 clock_modules for the top and bottom GTPs, again driven > arbitrarily from 1 GTP in each half. You could do any and it would be fine, with caveats: a) you'd use 7 DCMs, lots of BUFGs and more power. b) the 'arbitrary' GTP_DUAL that is able to clock them all is the one in the middle (ie. Y3) c) it's ok, just uses double clocking resources than b) Check out the RocketIO User Guide for more info. Cheers, -P@ > Any help gratefully received. > > Roger.Article: 135944
Hello newsgroup! I=92m going to implement my FPGA based SoC with embedded processor. Now I=92m trying to choose soft processor. The main feature for me it=92s a good CAD performance and ease to use. I start to work with Xilinx EDK, and the questions is : Can I integrate my EDK processor system in some top-level schematic, like a component, such as I can do this in Quartus. There are many threads about problem of choose a software processor: Nios vs MicroBlaze and others, but it=92s interesting to hear opinions the people who work with both of them, or who study this problem more thoroughly. What are the advantages and disadvantages of every cores?Article: 135945
On 23 Oct, 10:50, adventurer <hry...@gmail.com> wrote: > Hello newsgroup! > > I=92m going to implement my FPGA based =A0SoC with embedded processor. No= w > I=92m trying to choose soft processor. The main feature for me it=92s a > good CAD performance =A0and ease to use. I start to work with Xilinx > EDK, and the questions is : Can I integrate my EDK processor system in > some top-level schematic, like a component, such as I can do this in > Quartus. There are many threads about =A0 problem of choose a software > processor: =A0 Nios vs MicroBlaze and others, but it=92s interesting to > hear opinions the people who work with both of them, or who study this > problem more thoroughly. What are the advantages and disadvantages =A0of > every cores? Would you really choose either Xilinx or Altera FPGAs based on Nios vs MicroBlaze? If not, then why compare the two? Mico32 for me anyway ;-) JonArticle: 135946
"PatC" <pato@REMOVETHISpatocarr.com> wrote in message news:CmWLk.6188$Zd.903@newsfe10.iad... > Roger wrote: >> I want to use 14 GTPs on a Virtex 5 each running a separate Aurora >> interface. The Aurora code from Coregen produces a clock_module process >> amongst all the others which contains a DCM. >> >> Previous experience of Virtex II Pro implementations allowed 1 clock >> module to be used with multiple Auroras. The Virtex 5 clock module is >> different in that it takes its clock input from the GTP Dual PLL together >> with a Lock signal. >> >> What's the best approach in this situation? >> >> A) Use 1 clock_module (DCM) per GTP_Dual i.e. 2 Auroras >> B) Use 1 clock_module for all the Auroras with it being driven from one >> arbitrary GTP (same idea as the Virtex II Pro days). >> C) Use 2 clock_modules for the top and bottom GTPs, again driven >> arbitrarily from 1 GTP in each half. > > You could do any and it would be fine, with caveats: > a) you'd use 7 DCMs, lots of BUFGs and more power. > b) the 'arbitrary' GTP_DUAL that is able to clock them all is the one in > the middle (ie. Y3) > c) it's ok, just uses double clocking resources than b) > > Check out the RocketIO User Guide for more info. > > Cheers, > -P@ > > >> Any help gratefully received. >> >> Roger. Thanks Pat, that's one 'unknown' tackled. I'm regretting the day I started this as the Core Gen Aurora wizards (still don't know why there are 2) won't produce multiple independent Auroras. I have to specify a single lane version instead but that's particularly annoying as a GTP_dual is instantiated but only the ports of the GTP that's used are brought out. This, and the clocking issue, mean there's loads of hand editing to do which is disappointing and completely defeats the object of having Core Gen in the first place. Thanks for your help with the clocking though. Rog.Article: 135947
> You could have an old copy of the cygwin DLL in your windows system32 > directory. =A0Did you "install" the EDK cygwin or just copy the files? hi... what you have told is exactly right......... i had an old copy of cygwin.dll in system32 i have replaced with new.. its working perfectly.. lot of thanks...Article: 135948
Brian- Brian Drummond wrote: > On Tue, 21 Oct 2008 16:54:03 -0700 (PDT), Jeff Brower > <jbrower@signalogic.com> wrote: > > >All- > > >When we look at the Pad Report, we can't see any pins other than 3.3V > >(with exception of pre-defined VCCINT, VCCO_X, and VCCAUX pins). > >There are no LVCMOS25 pins listed. In the .ucf file, we did not > >define any LVCMOS25 pins and included IOSTANDARD = LVCMOS33 for all > >used pins. > > Try the mapper report file (.mrp) which should list all the I/O pins > including their I/O standards near the end of the file. > > - Brian Many thanks for your help. As per your suggestion, I eliminated any "unused IBUF" warnings and made sure those pins were used / combined to create valid output signals. Also I made sure there are no "OBUFs with no load". Basically every pin that is LOC'd is a) used, b) doesn't show any warning anywhere in the XST process, and c) has an IOSTANDARD = LVCMOS33 attribute. And I've checked the map report file carefully (repeatedly). But still no luck. The "seven 2.5V outputs" are still there, and I can find no clues as to which pads XST is referring. Why is there 7... what are the actual pins... XST reports soooo much stuff, why not this. Do you think it could be pins that are not used; i.e. not LOC'd or referred to at all? There are several of those. -JeffArticle: 135949
"Jeff Brower" <jbrower@signalogic.com> wrote in message news:9cf3f6ae-59d7-4dc3-aaa5-5924f79ed3c0@64g2000hsu.googlegroups.com... > > Do you think it could be pins that are not used; i.e. not LOC'd or > referred to at all? There are several of those. > > -Jeff Are there seven of them? Cheers, Syms.
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