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Melanie Nasic wrote: > Hi Pete, > > I want the compression to be lossless and not based on perceptional > irrelevancy reductions. By stating 1 kb I meant 1024 bits and that's just > about half the line data. Your recommendation "1d predictor, non-linear > quantizer and entropy coder" sound interesting. COuld you please elaborate > on that? How is it done? Where can I find some exemplary codes? How can it > be achieved with hardware (VHDL sources?) > > Thank you a lot. > > Bye, Mel. > > Hi Mel, you can calculate the delta of two subsequent pixels an then Huffman code this result. This should archive almost 2:1 if there are not much large brightness steps in the picture. Regards Thomas > > "Pete Fraser" <pfraser@covad.net> schrieb im Newsbeitrag > news:11qg5v3q9plph0a@news.supernews.com... > >>"Melanie Nasic" <quinn_the_esquimo@freenet.de> wrote in message >>news:do9206$1m4$1@mamenchi.zrz.TU-Berlin.DE... >> >>>Hello community, >>> >>>I am thinking about implementing a real-time compression scheme on an >>>FPGA working at about 500 Mhz. Facing the fact that there is no >>>"universal compression" algorithm that can compress data regardless of >>>its structure and statistics I assume compressing grayscale image data. >>>The image data is delivered line-wise, meaning that one horizontal line >>>is processed, than the next one, a.s.o. >>>Because of the high data rate I cannot spend much time on DFT or DCT and >>>on data modelling. What I am looking for is a way to compress the pixel >>>data in spatial not spectral domain because of latency aspects, >>>processing complexity, etc. >> >>Are you hoping for lossless, or is lossy OK? >> >> >>>Because of the sequential data transmission line by line a block matching >>>is also not possible in my opinion. The compression ratio is not so >>>important, factor 2:1 would be sufficient. What really matters is the >>>real time capability. The algorithm should be pipelineable and fast. The >>>memory requirements should not exceed 1 kb. >> >>That's 1024 bits, or bytes? >>Is it enough for one line? >>You don't say what your resolution and frame rate are. >> >> >>>What "standard" compression schemes would you recommend? Are there >>>potentialities for a non-standard "own solution"? >> >>If you don't have a line of storage available, that restricts you a lot. >>I don't understand this though. If you're using a 500MHz FPGA, it's >>presumably recent, and presumably has a decent amount of storage. >> >>How about a 1d predictor, non-linear quantizer and entropy coder? >>If you have more memory available, look at JPEG-LS. >>It can do lossless, or variable mild degrees of loss. >> >>>Thank you for your comments. >>> >>>Regards, Melanie >>> >> >> > >Article: 93826
wtxwtx@gmail.com wrote: > Hi Robert, > I checked USPTO and found you hold 5 patents. > > I like to listen to your advices, experiences and lessons all ears. > > Several things for me to file patents are: > 1. The circuits must be novel, and it will be applied in the industry > without doubt. > > For example, they must be dramatic advantages over current ones in one > of following respects: speed, performance, saving power or saving > logic. > > 2. The 'novel' circuit must have potential buyers to make money. > > 3. History will keep your invention as a record and the circuit can go > into textbooks. > > But basically, making money is the most important factor to file a > patent. > > Weng > Well, *dramatic* advantages are not really necessary; making the device more useable or practical is sufficient. Check my website oil4lessllc.com and look at the Mosley patent and then at the two i put into PD as an example. If one wants to be nasty, the item patented does not have to be practical, does not have to be buildable by ordinary means. Hell, i have seen numerous patents on things that were obvious to even those *not* skilled in the particular art (ie: legally speaking the patent should not have been awarded). And i have seen patents that were almost exact copies of one another (up to three!). One patent i saw was intriguing; it purported to be a patent on a plastic coated bike sprocket, but really was a chemical patent "hiding" in a different classification. Do your own patent search for background and interference (of idea); patent lawyers are very expensive and if the one chosen lacks a background in the field of art that your idea covers, then their search will not be as wide or deep as needed. The Patent Clearing house in Sunnyvale CA is the best in the nation - mainly because they have *all* of the cross reference material that is available. If and when you do go for a patent lawyer, make sure that they do have the relevant background (5 years or more). And have the whole patent written up; even format it the same way as required for submittal. Have those you trust go over wording of the claims, suggest added ones, check spelling, etc. If there is a term commonly used in similar patents but is not standard english, use the "patent-ese" not English. For example, in the pump patent, note the term "depending" is used, where English would use "descending".Article: 93827
wtxwtx@gmail.com wrote: > Hi, > I am following patent 6,914,453 by IBM to write claims. > > I would like to ask another question: > What is the difference between 'providing' and 'applying' in > a patent claim area for electronic circuit? > > In the above patent, it writes: > 1. A method ... > providing a clock input to the logic circuits; > providing one or more static signal inputs to the logic circuit; <-- > generating one or more dynamic signal inputs ... > applying the one or more dynamic signal input to the circuit; > ... > 4. The method of claim 1, further comprising the step of > applying one or more static signal inputs to the logic circuit. > >>From the above descriptions, I am confused about why claim 4 > repeats a step that has already been described, but insead of > using 'providing', it uses 'applying' this time. > > Thank you. > > Weng > If you look closely at claim #1, note the use of providing, generating, applying, precharging, evaluating, holding, and converting are all used (listed in order of occurrence). In #4, "applying" would appear to mean that an external signal is used (applied). In #1, "providing" appears to be a modifier of the action "step". I ain't no engrish hexpert, nor familiar with "patentese" related to logic circuits, so i could be very wrong in those assessments. Look at at least a dozen patents direcly related to the field of interest - and keep an eye out for similar or identical constructs like those you mentioned. That is how i discovered that "depending" was patentese for the engrish term "descending".Article: 93828
On Fri, 30 Dec 2005 05:06:47 -0800, wtxwtx wrote: > Hi Robert, > I checked USPTO and found you hold 5 patents. > > I like to listen to your advices, experiences and lessons all ears. > > Several things for me to file patents are: > 1. The circuits must be novel, and it will be applied in the industry > without doubt. > > For example, they must be dramatic advantages over current ones in one > of following respects: speed, performance, saving power or saving > logic. No, they don't have to show anything "dramatic" at all. A patent only has to show uniqueness and workability. > 2. The 'novel' circuit must have potential buyers to make money. Making mony is irrelevant to a patent, though since one has to pay money to get a patent, it's a good idea. > 3. History will keep your invention as a record and the circuit can go > into textbooks. History? Publication will prevent (in an honest world) someone else from patenting your idea. You'll still need a lawyer and a pile of money if someone else does patent your idea. > But basically, making money is the most important factor to file a > patent. There are many reasons to file a patent. Making money is only one. -- KeithArticle: 93829
On Sun, 1 Jan 2006 11:27:34 -0800, "luiguo" <luiguo@gmail.com> wrote: >Hi all: > I download my design(A 5 pipeline CPU) to FPGA(Altera Stratix), But >it runs diff with what I expected. Some signals in a bus were delayed by a >stage in FPGA(I see those signals in SignalTap), but it works well when >simulation. When you say it works well when simulation do you mean that you have done a back-annotated simulation or just your rtl simulation. Back annotated simulation is where you take the .vo file from quartus (verilog output) and the SDF file generated by quartus (the file with all the actual delays) and simulate that design and see if it works as expected. Of course the better way is to put in good timing constraints and do a thorough timing analysis which ensures that you are catching all timing errors not just the ones which appear for your specific simulation.Article: 93830
"Tim Wescott" <tim@seemywebsite.com> wrote in message news:xLSdnUIS0pfE9yrenZ2dnUVZ_sednZ2d@web-ster.com... > drg wrote: > >> Hi all, I'm new to FPGA stuff... i have an idea of making an audio >> spectrum analyzer implemented on a fpga, displaying data on a VGA >> monitor (spartan-3 starter kit). I guess I will need to filter the >> audio data in some way (band pass filters for each channel?), and I >> want to do it with the FPGA. That is, I'll get some ADC and plug it to >> the FPGA, and then process the audio, first some basic filters for >> audio manipulation (low pass, "bass boost", etc), and then move on to >> something more complex.. >> Does anyone have some pointers of how to implement this kind of >> filtering with FPGAs? >> > This is basic DSP stuff. At its most basic you're just implementing the > math on an FPGA; in reality you're going to be doing a bunch of messing > around with the details of the process. > > You really need to know three things: DSP, FPGA design, and optimizing > FPGA designs for DSP. For the DSP part of it I recommend "Understanding > Digital Signal Processing" by Rick Lyons. I learned logic design by > osmosis, so I can't recommend any one text. When you get to the part of > merging the two onto a real, live FPGA I'd check the Xilinx web site for > app notes. > > -- Alternatively use Altera instead where the DSP tools come fitted as standard. You can create your own filter specification by specifying number of bits/filter type/number of stages/sample rate etc. The tool will then plot the actual achieved response which you can then tweak dynamically. Code is then generated which you then drop into your design. Simplicity itself really if you do not want to get deep into the math. SlurpArticle: 93831
Hi all, I'm currently working on a FPGA design including a microbalze (as a sub-system). When simulating my design everything seems to be ok but what's bothering me is the following: the time from when I pull down my reset signal until the time the "actual" program start executing is about 100 clk cycles. in thses 100 cycles the PC (program counter) is running almost consecutively. I would realy appritiete it if any of you can either explain or direct me to an explanation regarding the microblaze program intialization sequence I'm wondering what is it doing "for all this time" .. p.s. - my design includes an external interrupt handler(maybe it's related). Thanks in advance, MotiArticle: 93832
Hi Moti, Two places to look are page 170, Initialization Files, in http://www.xilinx.com/ise/embedded/est_rm.pdf and page 9, Boot Code, in http://www.xilinx.com/ise/embedded/oslibs_rm.pdf Good Luck. Paul Moti Cohen wrote: > > Hi all, > I'm currently working on a FPGA design including a microbalze (as a > sub-system). When simulating my design everything seems to be ok but > what's bothering me is the following: > the time from when I pull down my reset signal until the time the > "actual" program start executing is about 100 clk cycles. in thses 100 > cycles the PC (program counter) is running almost consecutively. > > I would realy appritiete it if any of you can either explain or direct > me to an explanation regarding the microblaze program intialization > sequence I'm wondering what is it doing "for all this time" .. > > p.s. - my design includes an external interrupt handler(maybe it's > related). > > Thanks in advance, MotiArticle: 93833
yes, that's my problem, the maths. I'm still in college (systems engineering), but I have yet to learn all that advanced math to understand even the most basic DSP text. These are all full of huge formulas and complex numbers... I'm not trying to sound lazy but I don't think it has to be that complicated. I just need a routine, and to learn how to use it (I seem to have found it at opencores (http://www.opencores.org/projects.cgi/web/biquad/overview) along with DSPlay to generate the coefficients. Regards, hjfArticle: 93834
drg <drgenio@gmail.com> wrote:
> Hi all, I'm new to FPGA stuff... i have an idea of making an audio
> spectrum analyzer implemented on a fpga, displaying data on a VGA
I'm not quite sure but spectrum analyzer sounds like FFT.
> want to do it with the FPGA. That is, I'll get some ADC and plug it to
> the FPGA, and then process the audio, first some basic filters for
> audio manipulation (low pass, "bass boost", etc), and then move on to
> something more complex..
> Does anyone have some pointers of how to implement this kind of
> filtering with FPGAs?
I suggest you start doing all this at a higher level, let's
say Ada or C#. You can do your researches without dealing with
FPGAs and so on.
You already know that this is DSP stuff, but it doesn't matter
if you use your normal CPU or a real DSP (probably as VHDL).
You'll see that (in general) a DSP is just a processor which
is good for MAC: multiply-and-accumulate, so to say "*" and "+",
but you can also do this with your Athlon ;)
Have a look at PCM to understand how audio data is represented
for processing, what a sample is and why PCM is almost Wave.
You can compare your results by looking at
<http://adi.thur.de/index.php?show=asound>.
Then start writing your code in a highlevel language and
use normal wave-files (or raw PCM) to feed your software
audio processor. You can write some basic effects like
"echo" by filling a buffer, dividing (lowering volume) and
adding it to the main signal after some delay (sidechain-FIFO).
You can change the volume by multiplying the signal with
a scalar.
After you've done all this, you can get a real ADC, a soft-IP DSP,
poke everything to your FPGA and use your new hardware to do
the job ;) Until then, read/write from/to wave files or
your soundcard.
I suggest you use Linux, have a look at the "sox" manpage, play
with sox -x -t raw/wav and so on. If your CPU is fast enough,
you can read vom /dev/dsp, calculate some functions and write
the results back to /dev/dsp. I usually read from wave files
and write to /dev/dsp to get an immediate impression of what
goes wrong... ;)
There is also some more audio processing software for Linux,
most of it is open source, so you can see how to implement
the FFT for your spectrum analyzer, filter effects (see LADSPA)
and so on.
I haven't ever tried a real DSP, but some datasheets claim
FFT-optimization, so it might be possible to pass a buffer
to a special asm-function, returning the FFT-transformed
of the input.
One word left: you'll probably implement your filters
in your DSP's assembler. So to say: it is all about
software and it is hardware specific. That's why you
can use a highlevel language to understand what's going
on. Filtering is more or less easy, have a look at
your opencores example:
y[n] = b10*x[n] + b11*x[n-1] + b12*x[n-2] + a11*y[n-1] + a12*y[n-2]
where x[n] represents the current input, x[n-1] is the previous
sample, y[n-1] is the previous output sample and all "a"s and "b"s
are simple coefficients for fitting the desired curve. y[n] is
your current output.
With libao, one can write this program in less than 10 minutes,
it goes like this:
procedure iir is
b10 : constant Float := 1.2345;
b11 : constant Float := 2.3456;
b12 : constant Float := 3.4567;
a11 : constant Float := 4.5678;
a12 : constant Float := 5.6789;
x, x1, x2, y, y1, y2 : Float := 0.0;
begin
loop
x := Get_Input; -- however
y := b10 * x + b11 * x1 + b12 * x2 + a11 * y1 + a12 * y2;
Output (y); -- however
y2 := y1; -- prepare for next cycle
y1 := y;
x2 := x1;
x1 := x;
end loop;
end iir;
The convolution of the input signal with this mask isn't
that hard, all the trick is in the mask. I'm currently
doing some digital image processing with C++, in most
cases this means looping over the image, consider the
pixels in the neighbourhood and somehow adding them
to the current pixel. This is pretty much how audio
processing works: look at current, some older and perhaps
some newer samples, take them in consideration and output
something according to this consideration ;)
Get a book or google for digital signal processing.
HTH
--
mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver
Lieber ein Busenwunder als ein wunder Busen
Article: 93835Totally_Lost schrieb: > The FpgaC internal algorithm is pretty generic, and just decideds > pretty early on to force all internal functions to 4-LUTs. This makes > it difficult to decide to use support logic like H-LUTs on XC4K, or F5 > muxes on Virtex parts, or the carry logic on any of these. > > I'm looking for papers which discuss/descript alternative fitting > algorithms to better use vendor assist logic in FPGAs, particularly for > scheduling logic expressions across multiple LUTs for both space and > time specific tradeoffs. Probably the most important thing is to recognize all addition networks and map them to carry logic. You can do this in a preprocessing step. I think there is a paper by Stoffel/Kunz/Wedler on identifying arithmetic elements in gate level netlist. Alternatively you can preserve that information from RTL. H-LUTs with inputs independant from the F and G LUTS are not even supported by Xilinx software. Not even if you instantiate hardmacros. I suggest that you handle the H-Lut as a F5 mux. No use to put to much effort into obsolete hardware. The problem is that with special cases you kill the nice properties of the flow map algorithm. You need to experiment wether your optimal 4-LUT result is better or worse than a heuristic result for 4-LUTs plus muxes. Supporting a mix of 4, 5 and 6-luts using the muxes can probably done quite elegantly but this leaves out all the wide input functions. Kolja SulimmaArticle: 93836
Hi all:
I download my design(A 5 pipeline CPU) to FPGA(Altera Stratix), But
it runs diff with what I expected. Some signals in a bus were delayed by a
stage in FPGA(I see those signals in SignalTap), but it works well when
simulation. All optimization options was turn off in Quartus II, No efferct
were taken. Can someone help?
Thanks!
-luiguo
luiguo@gmail.com
Article: 93837Hi Robert, Thank you for your good advice. WengArticle: 93838
"Antti Lukats" <antti@openchip.org> wrote in message news:dp40cs$65f$02$1@news.t-online.com... > They looked nice but when actually having > them in my hands, well I instantly wanted to check something out. > And I did, and I liked the easyness and fun I had, here is the story > > http://xilant.com/content/view/33/55/ That's an interesting read Antti, a couple of questions.... "Cutting out some pages from an stupid catalog (the normal office paper is no good). Replacing the paper in Laser printer with the catalog paper." I presume here that you're trying to use glossy paper so when you reverse it and iron it onto the copper clad board what's printed will transfer better than with normal paper? I also presume that you run it through a laser printer? Any tips on the best sort of paper to use? What about glossy photo paper? "Now taking 100ml water and a little from that fine-acid thing." What do you mean by 'that fine-acid thing'? This sounds like a useful technique, recently there have been a couple of occaisions when I would have like to have been able to knock together a _really_ simple PCB to help with some proto-typing/testing. Nial.Article: 93839
Hello Herman, Number of choices.... 1....Altera DSP Builder 2....Xilinx Coregen 3....Tyder IP Code Generator 4....Google Regards Bob drg wrote: > Hi all, I'm new to FPGA stuff... i have an idea of making an audio > spectrum analyzer implemented on a fpga, displaying data on a VGA > monitor (spartan-3 starter kit). I guess I will need to filter the > audio data in some way (band pass filters for each channel?), and I > want to do it with the FPGA. That is, I'll get some ADC and plug it to > the FPGA, and then process the audio, first some basic filters for > audio manipulation (low pass, "bass boost", etc), and then move on to > something more complex.. > Does anyone have some pointers of how to implement this kind of > filtering with FPGAs? > > Regards, > Hernan > > PS. Happy new year! (31/12/2005 9:51 PM here)Article: 93840
Yahoo group for making PCBs: http://groups.yahoo.com/group/Homebrew_PCBs/ LeonArticle: 93841
If it fits your terms of reference, you could also consider a software-only application, using (for example) the Infineon TriCore (TC1796) CPU. There's a development board for it (TriBoard). This beastie runs 150MHz clock, has 12-bit fast ADC's on board, and hardware addressing for FFT bit-reversal, etc. Oh, and (single precision) hardware floating point. stenasc@yahoo.com wrote: > Hello Herman, > > Number of choices.... > > 1....Altera DSP Builder > 2....Xilinx Coregen > 3....Tyder IP Code Generator > 4....Google > > Regards > Bob > drg wrote: > >>Hi all, I'm new to FPGA stuff... i have an idea of making an audio >>spectrum analyzer implemented on a fpga, displaying data on a VGA >>monitor (spartan-3 starter kit). I guess I will need to filter the >>audio data in some way (band pass filters for each channel?), and I >>want to do it with the FPGA. That is, I'll get some ADC and plug it to >>the FPGA, and then process the audio, first some basic filters for >>audio manipulation (low pass, "bass boost", etc), and then move on to >>something more complex.. >>Does anyone have some pointers of how to implement this kind of >>filtering with FPGAs? >> >>Regards, >>Hernan >> >>PS. Happy new year! (31/12/2005 9:51 PM here) > >Article: 93842
I simulated in RTL, not back-annotated. I do not set any timing constraints before, Maybe that's the problem. Thanks a lot! "mk" <kal*@dspia.*comdelete> wrote in message news:lq5fr195cql9js033iei6qsfb8bf1bed3r@4ax.com... > On Sun, 1 Jan 2006 11:27:34 -0800, "luiguo" <luiguo@gmail.com> wrote: > >>Hi all: >> I download my design(A 5 pipeline CPU) to FPGA(Altera Stratix), But >>it runs diff with what I expected. Some signals in a bus were delayed by a >>stage in FPGA(I see those signals in SignalTap), but it works well when >>simulation. > > When you say it works well when simulation do you mean that you have > done a back-annotated simulation or just your rtl simulation. Back > annotated simulation is where you take the .vo file from quartus > (verilog output) and the SDF file generated by quartus (the file with > all the actual delays) and simulate that design and see if it works as > expected. Of course the better way is to put in good timing > constraints and do a thorough timing analysis which ensures that you > are catching all timing errors not just the ones which appear for your > specific simulation.Article: 93843
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> schrieb im Newsbeitrag news:43b84d3c$0$29577$da0feed9@news.zen.co.uk... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:dp40cs$65f$02$1@news.t-online.com... >> They looked nice but when actually having >> them in my hands, well I instantly wanted to check something out. >> And I did, and I liked the easyness and fun I had, here is the story >> >> http://xilant.com/content/view/33/55/ > > > That's an interesting read Antti, a couple of questions.... > > "Cutting out some pages from an stupid catalog (the normal office paper is > no good). Replacing the paper in Laser printer with the catalog paper." > > > I presume here that you're trying to use glossy paper so when you > reverse it and iron it onto the copper clad board what's printed will > transfer better than with normal paper? I also presume that you > run it through a laser printer? > > Any tips on the best sort of paper to use? What about glossy photo paper? > > > "Now taking 100ml water and a little from that fine-acid thing." > > What do you mean by 'that fine-acid thing'? > > This sounds like a useful technique, recently there have been a couple > of occaisions when I would have like to have been able to knock together > a _really_ simple PCB to help with some proto-typing/testing. > > > Nial. > Hi Nial I found this 'direct toner' method from 'platinen' forum at german site http://www.mikrokontroller.net there was reference to a real great manual (unfortnatly in german) http://thomaspfeifer.net/ go 'trickkiste' thee is picture and long story with many pictures some english links can be found google PCB DIY toner http://www.michaeladams.org/?Electronics:PCBs have fun! this was my first testing with that method and really worked I spent at www.conrad.de 2 EUR for the fine aetz kristall (for acid making) 3 EUR for 20 bx 30 cm PCB 2 for plastik thing where to put the acid in thats it. I have almost all the PCB and acid overleft so can make more boards within a few hours from idea to ready board Antti PS I will post the picture of my first board to my website as soon as get shotArticle: 93844
drg wrote: > yes, that's my problem, the maths. I'm still in college (systems > engineering), but I have yet to learn all that advanced math to > understand even the most basic DSP text. These are all full of huge > formulas and complex numbers... I'm not trying to sound lazy but I > don't think it has to be that complicated. > > I just need a routine, and to learn how to use it (I seem to have found > it at opencores > (http://www.opencores.org/projects.cgi/web/biquad/overview) along with > DSPlay to generate the coefficients. > > Regards, > hjf > Heh. The math will come in handy when (not if) you design doesn't work correctly. You really need to build a basic understanding of what you are trying to do first. How else are you going to find out what's wrong when things start to misbehave ? What you are trying to do sounds like a very interesting - but also very complex - project. I would guess that you need to go through the following steps - Note that you can shortcut the process a lot of places by using already existing modules. This of course will get you to your goal faster, but you will learn less in the process - YMMV: 1) You need to buy/make an A/D converter module for the starter kit, since it does not come with one. 2) Design a filter bank. For spectrum analysis a 3rd octave bank is probably what you want. You can get plenty of references for how to design that on Google. This will involve IIR filters - so knowing the math (and how to implement them in fixed point) will be useful unless you shortcut the process and grab some already-made implementation from somewhere. It will REALLY help you debugging your system if you have a known-to-work high level implementation (Matlab, Numerical Python or C as a last resort) that you can compare your results to. 3) Get the filter bank implemented in some HDL (I prefer Verilog but others prefer VHDL). Here a book like "Digital Signal Processing With Field Programmable Gate Arrays" by Uwe Meyer-Baese might come in handy. Alternatively Mathworks and others will happily compile your high-level implementation directly to your FPGA to the tune of big $$$. But again - you will learn less in the process. If you choose to implement yourself I can recommend using the free Xilinx tools to do implementation and simulation. 4) A filter bank does not a spectrum analyzer make. You need to present this on the VGA output. This means building a graphics frame buffer structure for outputting the graphics, and then some kind of processor structure to fill the frame buffer in a sensible way based on the filter bank output. Here I guess that the best way to go would be to get an already made processor core like the picoblaze and use that to do the presentation. For the frame buffer you will be able to find examples on the web. Have fun - I mean it - I for one find it to be a very interesting project, that you will learn a lot from if you choose to dwelve into all the topics involved. -- BrianArticle: 93845
Thanks for your explanations. The clock is not that high, 60 MHz is the maximum frequency. Moreover, the problems come out for internal signals, slice to slice propagation time. I really don't understand how ModelSim estimate the propagation time... I know that backannotation usually provides worst-case timing into the simulation but why I cannot find the same propagations times on the .SDF file? Maybe the .SDF file is not the only input that ModelSim use for timing estimation? Dan.Article: 93846
Paul, many thanks for your help I did the following to get the disassembly code from the compiler: 1) I used the mb-gcc to generate a .o file format. 2) I used the "mb-objdump -d app_name.o > dump_file.dat" command. Regadrs, Moti.Article: 93847
Hello All,,
I need to implement Ethernet Multiplexer in FPGA.
I need to draft the requirement specifications also.
Can any body guide me on what Ethernet Multiplexers are actually
used for ....?
Any core area of application for Ethernet Multiplexers (FPGA
Based).
Please suggest me some good documents, data sheets, URLs, books
what ever you can.
Thanks in Advance
Kedar
Article: 93848
Hello
Must I always include an reset signal to force all used flip flops to a zero
condition?
If I write an entity that defines a counter like this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_0_to_255 is
Port ( clk : in std_logic;
d : out std_logic_vector(7 downto 0));
end counter_0_to_255;
architecture beh of counter_0_to_255 is
signal cnt : std_logic_vector(7 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
cnt <= cnt + 1;
end if;
end process;
d <= cnt;
end beh;
Is the signal cnt always initiated to "00000000" at start up (or some random
value)? Or do I have to include a reset signal? What is best, an a
asynchronous reset or a synchronous reset?
The FPGA that I'm using is a Spartan 3.
Article: 93849"bill" <bill@telia.se> schrieb im Newsbeitrag news:43b8fa90$0$15787$14726298@news.sunsite.dk... > Hello > > Must I always include an reset signal to force all used flip flops to a > zero > condition? > > If I write an entity that defines a counter like this: > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity counter_0_to_255 is > Port ( clk : in std_logic; > d : out std_logic_vector(7 downto 0)); > end counter_0_to_255; > > architecture beh of counter_0_to_255 is > signal cnt : std_logic_vector(7 downto 0) := (others => '0'); > begin > > process(clk) > begin > if rising_edge(clk) then > cnt <= cnt + 1; > end if; > end process; > > d <= cnt; > end beh; > > Is the signal cnt always initiated to "00000000" at start up (or some > random > value)? Or do I have to include a reset signal? What is best, an a > asynchronous reset or a synchronous reset? > > > > The FPGA that I'm using is a Spartan 3. > your counter will be initially 0 after fpga is released from config -- Antti Lukats http://www.xilant.com -- Antti Lukats http://www.xilant.com
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