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MK, Great! I love it. Nice analogy. I like to tell folks that FPGAs are the only chips that wake up everyday and say "Who I am going to be today?" Austin mk wrote: > On 5 Jan 2006 08:17:58 -0800, fourbeans@gmail.com wrote: > > >>I've known lots of ASIC designers that name their device something cool >>like vader or dilbert. Do people name their FPGA designs as well? >>Anyone know how or why this got started other than the fact that EEs >>are geeks? Was is driven by marketings folks, or maybe the mood the >>designer was in at the time of the design such as ATI's Rage? > > > ASICs are like your children, it takes such a long and ardious time to > make them and once you tape them out you can really never get rid of > them and you can only fix their small mistakes by making small minor > changes without touching their base. You just learn their quirks, make > changes in other pieces of their environment (fix firmware, change > pcb, etc) to accomodate them. That's why people name their ASICs. > FPGAs are at most like a pet you buy for one of your children. If it > becomes too much of a hassle, you just return it or flush it down the > drain and get another one. That's why you don't find named FPGA > designs too often.Article: 94101
So I need some help getting started with programmable logic and VHDL.
In the past all I have done in the programmable logic area are 16V8 and
22V10 PALs.
I actually feel kind of stupid about the simple questions I am about to
ask, since it isn't like I don't know a lot about electonics. I have a
BSEE and in the past I've designed DSP boards and motor controllers
that control hundreds of amps and make electric forklifts able to lift
thousands of pounds. Pretty fun stuff actually.
But I am stumped by a few simple things with VHDL, Xilinx ISE 7.1, and
the Xilinx XC9536XL experimenter board I am using.
I've gone through ALDEC's Evita VHDL tutoral end to end and I think
I've learned the basics of the language.
So my project was to write a program to take a step and direction input
and output the proper sequences to control a stepper motor. But the
logic output sequences I got didn't make sense, so I decided to walk
before I run and just programmed up a couple very simple programs.
More on that later.
So what I've got is an XC9536XL board I bought on eBay. I connected a
4 position dip switch with 4 pull up resistors connected so that when
you turn on a switch the input is grounded and read as a zero. Turn
off the switch and the pullup pulls high and it's read as a one. I
know this works because I can measure the correct logic signal right at
the CPLD.
I also connected 4 LEDs. The 4 LEDs are each connected to Vcc through
a current limiting resistor. The other end of each LED is connected to
an output of the CPLD. So sending a logic zero to the output should
sink current and turn on the LED. The LEDs work because I can unplug
them from the socket header and connect each to ground and the LED
lights as expected.
The first "simple" program I wrote was to read the switch inputs and
output them to the LEDs, using the following VHDL code in Xilinx ISE
7.1:
----------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Test1 is
Port (SWITCH_IN : in std_logic_vector(3 downto 0);
LEDS_OUT : out std_logic_vector(3 downto 0));
end Test1;
architecture Behavioral of Test1 is
begin
LEDS_OUT <= SWITCH_IN;
end Behavioral;
----------------------
This code shows that the LEDs and switches work. I can flip the
switches and the LEDs change state. But here is the first problem.
The LEDs light opposite what I expect. The LEDs light when the
corresponding switch is set to input a high into the CPLD. It's like
either the inputs or outputs are being inverted inside the CPLD.
So I thought I'd try something simpler -- to turn on all the LEDs by
outputting "0000" to the four pins the LEDs are connected to. I
changed the LEDS_OUT assignment to LEDS_OUT <= "0000"; expecting the
LEDs to turn on. They didn't. So I figured maybe the outputs are
what's being inverted. I changed it to LEDS_OUT <= "1010"; thinking
that this way, inverted or not, two LEDs would light and two wouldn't.
The problem is none of the LEDs light. Remember that I showed that
both the switches and LEDs can change state with LEDS_OUT <=
SWITCH_IN;, just backwards from what I expected.
So I remembered from the tutorial that lots of code in VHDL is
triggered by changes in inputs, so I changed the LEDS_OUT assignment to
the following:
LEDS_OUT <= "101" & (SWITCH_IN(3) and SWITCH_IN(2) and SWITCH_IN(1)
and SWITCH_IN(0));
This should kill two birds with one stone. It will show me if I can
assign pins directly to values when it is part of an equation that
includes inputs that can change state. I thought mabye my previous
attempts didn't work since there was nothing to "trigger" the equation.
Also, with ANDing the switches and outputting that to one LED, I can
tell if it is the inputs or the outputs that are being inverted inside
the CPLD. If it is the inputs, I would have to set the switches to all
input a zero before the AND will be active and change the state of the
LED. "0000" will be the input that causes a different output then the
other 15 combinations, insted of "1111." If it is the output being
inverted, I'd have to set the inputs all to one, but the LED will light
opposite of what I expect, turning on with the inputs all set to one
(remember the output sinks current from the LED and therefore the LED
lights when a zero is output).
The result is that the upper 3 LEDs still all remain off, despite
directly setting two outputs to a one and one output to a zero. My
logic probe shows a high on those three CPLD pins. Apparently I can't
directly set a pin even when it is part of an equation.
The last LED lights when all four switch inputs are set to input a
high. This indicates that the inputs are not being inverted in the
CPLD. But the LED lights when the switches are all set high and I can
measure a logic low, 0V, on that LED's pin. This would indicate that
the outputs are being inverted from the way the assignment equation
would indicate.
My next experiment was to do something simple - a 4 bit counter right
from the Xilinx language templates. I ended up with the following VHDL
code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter1 is
Port ( CLK_IN : std_logic;
SWITCH_IN : in std_logic_vector(3 downto 0);
LEDS_OUT : out std_logic_vector(3 downto 0));
end Counter1;
architecture Behavioral of Counter1 is
signal count : std_logic_vector(3 downto 0) := "0000";
begin
process (CLK_IN)
begin
if CLK_IN = '1' and CLK_IN'event then
if SWITCH_IN(0)='1' then
count <= count + 1;
else
count <= count - 1;
end if;
end if;
end process;
LEDS_OUT <= count;
end Behavioral;
In the simulator this counter works fine, but when I run this code the
output sequence I get is not a straight count from 0 to 15. I get the
sequence 0,1,14,3,12,5,10,7,8,9,6,11,4,13,3,15. It is perfectly
repeatable, and the sequence reverses when I flip SWITCH_IN(0). After
some looking at the binary for that count sequence, I noticed that
every second number is the inverse of the previous, instead of the
expected number (14 is 1110, inverse of 0001 that preceeded it, not
0010 as expected next). I don't get it.
So my questions are:
1. When I do LEDS_OUT <= SWITCH_IN; why does there appear to be an
inversion happening somewhere inside the CPLD, apparently at the
outputs?
2. Why can't I just set outputs to a zero and have a LED light? Any
pin I directly assign to a value stays high.
3. Why doesn't my counter count?
It shouldn't be this difficult...
This ended up a lot longer than I expected, so if you made it this far,
thanks for reading it, and thanks for any help you can provide...
cdsmith
Article: 94102Peter Alfke napisał(a): > Jerzy, if you check with a high-impedance oscillosope probe, you cannot > detect the difference between an active High (10 Ohm) or 3-stated with > a weak pull-up (multi-kilohms). > To see the difference, load the pin with a kilohm to ground... > Peter Alfke > Thanks all of you. It's great pleasure to have answers so soon. I work on this project whole last year, so belive me, I've read V2 datasheets :) It's almost finished. We have problems with other chip which is partially controlled by V2. And there I use scope on that line where I saw what I wrote in my previos post. So... 1. It was scope, 2. I didn't try to check it by resistor pulldown, 3. HSWAP_EN='1' or NC - must check it on schema at work, but not before next tuesday :( 4. Checked lines was V2-outputs/others chips inputs - not pulled/up/down externally. 5. M2='1' M1='1' M0='0'. - Slave SelectMap mode. As I wrote earlier I'll be at work next tuesday, and I'll try to use your advices. I'll post results on this topic. Thank you once more. Best Regards Jerzy GburArticle: 94103
Hello all, Trying to track down availability of some XC3S500E parts (or 100/250 3E's) in PQ208 package. I've tried Avnet and NuHorizons and they both have month+ lead times. Unfortunately I am not Xilinx 's #1 Volume customer, I am just an average guy trying to purchase this, it is not related to my engineering work, so I can not probably leverage my workplace to get them. I'm trying to find a place where I can just order small quantity of 3E (1-4 of them). Am I out of luck? Anyone know where I can purchases these in small or single quantity today for eval? (I am aware people are shipping Dev boards, but I do not wish to buy one of these, I intend to design/layout my own board for my application). If anyone has any suggestions, I am all ears. I fear I may have to wait several months until Mouser or Digikey picks up some stock. -JoelArticle: 94104
hitsx@hit.edu.cn wrote: > Now I want to design a RISC cpu for study the cpu architecture, and I > am puzzled about how to start? > Whether should I start with a RISC 16 bit cpu, including just serveral > instructions like add, substract, multiply and divide? > And I wonder whether I should introduce the pipeline and superscalar > into the architecture? The Lattice Mico8 is open source, & FPGA optimised, so makes a good starting point - and you are free to move it to any fabric, or extend it. It is also quite similar to the PicoBlaze. (which is not open source?) -jgArticle: 94105
cdsmith69@gmail.com wrote: > So I need some help getting started with programmable logic and VHDL. > > In the past all I have done in the programmable logic area are 16V8 and > 22V10 PALs. > > I actually feel kind of stupid about the simple questions I am about to > ask, since it isn't like I don't know a lot about electonics. I have a > BSEE and in the past I've designed DSP boards and motor controllers > that control hundreds of amps and make electric forklifts able to lift > thousands of pounds. Pretty fun stuff actually. > > But I am stumped by a few simple things with VHDL, Xilinx ISE 7.1, and > the Xilinx XC9536XL experimenter board I am using. What did you use to design the 16V8/22V10's ? Why not use ABEL, for the 9536 ? -jgArticle: 94106
For the batch mode you need synplify_pro license! Don't ask me why. -- AmalArticle: 94107
cdsmith69@gmail.com wrote:
> So I need some help getting started with programmable logic and VHDL.
>
> In the past all I have done in the programmable logic area are 16V8 and
> 22V10 PALs.
>
> I actually feel kind of stupid about the simple questions I am about to
> ask, since it isn't like I don't know a lot about electonics. I have a
> BSEE and in the past I've designed DSP boards and motor controllers
> that control hundreds of amps and make electric forklifts able to lift
> thousands of pounds. Pretty fun stuff actually.
>
> But I am stumped by a few simple things with VHDL, Xilinx ISE 7.1, and
> the Xilinx XC9536XL experimenter board I am using.
>
> I've gone through ALDEC's Evita VHDL tutoral end to end and I think
> I've learned the basics of the language.
>
> So my project was to write a program to take a step and direction input
> and output the proper sequences to control a stepper motor. But the
> logic output sequences I got didn't make sense, so I decided to walk
> before I run and just programmed up a couple very simple programs.
> More on that later.
>
> So what I've got is an XC9536XL board I bought on eBay. I connected a
> 4 position dip switch with 4 pull up resistors connected so that when
> you turn on a switch the input is grounded and read as a zero. Turn
> off the switch and the pullup pulls high and it's read as a one. I
> know this works because I can measure the correct logic signal right at
> the CPLD.
>
> I also connected 4 LEDs. The 4 LEDs are each connected to Vcc through
> a current limiting resistor. The other end of each LED is connected to
> an output of the CPLD. So sending a logic zero to the output should
> sink current and turn on the LED. The LEDs work because I can unplug
> them from the socket header and connect each to ground and the LED
> lights as expected.
This is typically how LEDs are connected to a CPLD. VCC should be +3.3
volts, since the XC9536XL is a 3.3 volt part (with 5-volt tolerant
I/O's). So, in order to turn on an LED, the CPLD needs to ground the
LED's lead. (BTW: the LED is -->|-- )
so: [+3.3]-----[R]--->|---- [CPLD pin, or ground.]
LED
>
> The first "simple" program I wrote was to read the switch inputs and
> output them to the LEDs, using the following VHDL code in Xilinx ISE
> 7.1:
>
> ----------------------
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> entity Test1 is
> Port (SWITCH_IN : in std_logic_vector(3 downto 0);
> LEDS_OUT : out std_logic_vector(3 downto 0));
> end Test1;
>
> architecture Behavioral of Test1 is
> begin
> LEDS_OUT <= SWITCH_IN;
> end Behavioral;
> ----------------------
If you had inverted the switches, then you should have seen the
expected behaviour:
LEDS_OUT <= not SWITCH_IN;
>
> This code shows that the LEDs and switches work. I can flip the
> switches and the LEDs change state. But here is the first problem.
> The LEDs light opposite what I expect. The LEDs light when the
> corresponding switch is set to input a high into the CPLD. It's like
> either the inputs or outputs are being inverted inside the CPLD.
>
> So I thought I'd try something simpler -- to turn on all the LEDs by
> outputting "0000" to the four pins the LEDs are connected to. I
> changed the LEDS_OUT assignment to LEDS_OUT <= "0000"; expecting the
> LEDs to turn on. They didn't. So I figured maybe the outputs are
> what's being inverted. I changed it to LEDS_OUT <= "1010"; thinking
> that this way, inverted or not, two LEDs would light and two wouldn't.
> The problem is none of the LEDs light. Remember that I showed that
> both the switches and LEDs can change state with LEDS_OUT <=
> SWITCH_IN;, just backwards from what I expected.
>
> So I remembered from the tutorial that lots of code in VHDL is
> triggered by changes in inputs, so I changed the LEDS_OUT assignment to
> the following:
>
> LEDS_OUT <= "101" & (SWITCH_IN(3) and SWITCH_IN(2) and SWITCH_IN(1)
> and SWITCH_IN(0));
>
> This should kill two birds with one stone. It will show me if I can
> assign pins directly to values when it is part of an equation that
> includes inputs that can change state. I thought mabye my previous
> attempts didn't work since there was nothing to "trigger" the equation.
>
> Also, with ANDing the switches and outputting that to one LED, I can
> tell if it is the inputs or the outputs that are being inverted inside
> the CPLD. If it is the inputs, I would have to set the switches to all
> input a zero before the AND will be active and change the state of the
> LED. "0000" will be the input that causes a different output then the
> other 15 combinations, insted of "1111." If it is the output being
> inverted, I'd have to set the inputs all to one, but the LED will light
> opposite of what I expect, turning on with the inputs all set to one
> (remember the output sinks current from the LED and therefore the LED
> lights when a zero is output).
>
> The result is that the upper 3 LEDs still all remain off, despite
> directly setting two outputs to a one and one output to a zero. My
> logic probe shows a high on those three CPLD pins. Apparently I can't
> directly set a pin even when it is part of an equation.
>
> The last LED lights when all four switch inputs are set to input a
> high. This indicates that the inputs are not being inverted in the
> CPLD. But the LED lights when the switches are all set high and I can
> measure a logic low, 0V, on that LED's pin. This would indicate that
> the outputs are being inverted from the way the assignment equation
> would indicate.
>
> My next experiment was to do something simple - a 4 bit counter right
> from the Xilinx language templates. I ended up with the following VHDL
> code:
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> entity Counter1 is
> Port ( CLK_IN : std_logic;
> SWITCH_IN : in std_logic_vector(3 downto 0);
> LEDS_OUT : out std_logic_vector(3 downto 0));
> end Counter1;
>
> architecture Behavioral of Counter1 is
> signal count : std_logic_vector(3 downto 0) := "0000";
> begin
> process (CLK_IN)
> begin
> if CLK_IN = '1' and CLK_IN'event then
> if SWITCH_IN(0)='1' then
> count <= count + 1;
> else
> count <= count - 1;
> end if;
> end if;
> end process;
> LEDS_OUT <= count;
> end Behavioral;
>
>
> In the simulator this counter works fine, but when I run this code the
> output sequence I get is not a straight count from 0 to 15. I get the
> sequence 0,1,14,3,12,5,10,7,8,9,6,11,4,13,3,15. It is perfectly
> repeatable, and the sequence reverses when I flip SWITCH_IN(0). After
> some looking at the binary for that count sequence, I noticed that
> every second number is the inverse of the previous, instead of the
> expected number (14 is 1110, inverse of 0001 that preceeded it, not
> 0010 as expected next). I don't get it.
>
>
> So my questions are:
> 1. When I do LEDS_OUT <= SWITCH_IN; why does there appear to be an
> inversion happening somewhere inside the CPLD, apparently at the
> outputs?
> 2. Why can't I just set outputs to a zero and have a LED light? Any
> pin I directly assign to a value stays high.
You should be able to assign a 0 to each LED pin, and that should
cause each LED to lite.
LEDS_OUT <= "0000"; or LEDS_OUT <= (others => '0');
> 3. Why doesn't my counter count?
Hmm... I'm a bit puzzled by this, too. Try making an up counter.
Modify your code to count up only, and to not check the switch. Also,
the perferred way to act on a rising edge clock is
if rising_edge( CLK_in ) then
Also:IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED are non-standard
libraries. You're better off using IEEE.NUMERIC_STD, instead.
Out of curiousity, where does CLK_in come from and what is its
frequency?
And do you know that your LEDS_OUT CPLD pins are actually connected to
the LEDs and not something else?
After you've synthesized the code, look at the FITTER report. At the
end of the report, it shows list of chip pins and the name that has
been assigned to each chip pin. If they are wrong, you will need a UCF
(User Constraint File).
The simplest way to do this is to find the UCF that came with you
board, and then select PROJECT->ADD Source and supply the name of the
UCF.
If there is no UCF file, then you'll have to create one. The Process
box should show USER CONTRAINTS. Click on the [+] to expand it and
click on ASSIGN PACKAGE PINS. This will bring up another screen that
shows a drawing of the chip, plus a list of signals. It's then an easy
matter of assigning your signals to the chip so that the signal match
up with how the chip is wired on the board.
>
> It shouldn't be this difficult...
>
> This ended up a lot longer than I expected, so if you made it this far,
> thanks for reading it, and thanks for any help you can provide...
>
> cdsmith
"thanks for reading it" You're welcome. I had a lot of problems like
this when I was just starting out, too. And who knows, perhaps the
board you bought from eBay has problems.
HTH
-Dave Pollum
Article: 94108
cdsmith69@gmail.com wrote:
> So I need some help getting started with programmable logic and VHDL.
>
> In the past all I have done in the programmable logic area are 16V8 and
> 22V10 PALs.
>
> I actually feel kind of stupid about the simple questions I am about to
> ask, since it isn't like I don't know a lot about electonics. I have a
> BSEE and in the past I've designed DSP boards and motor controllers
> that control hundreds of amps and make electric forklifts able to lift
> thousands of pounds. Pretty fun stuff actually.
>
> But I am stumped by a few simple things with VHDL, Xilinx ISE 7.1, and
> the Xilinx XC9536XL experimenter board I am using.
>
> I've gone through ALDEC's Evita VHDL tutoral end to end and I think
> I've learned the basics of the language.
>
> So my project was to write a program to take a step and direction input
> and output the proper sequences to control a stepper motor. But the
> logic output sequences I got didn't make sense, so I decided to walk
> before I run and just programmed up a couple very simple programs.
> More on that later.
>
> So what I've got is an XC9536XL board I bought on eBay. I connected a
> 4 position dip switch with 4 pull up resistors connected so that when
> you turn on a switch the input is grounded and read as a zero. Turn
> off the switch and the pullup pulls high and it's read as a one. I
> know this works because I can measure the correct logic signal right at
> the CPLD.
>
> I also connected 4 LEDs. The 4 LEDs are each connected to Vcc through
> a current limiting resistor. The other end of each LED is connected to
> an output of the CPLD. So sending a logic zero to the output should
> sink current and turn on the LED. The LEDs work because I can unplug
> them from the socket header and connect each to ground and the LED
> lights as expected.
This is typically how LEDs are connected to a CPLD. VCC should be +3.3
volts, since the XC9536XL is a 3.3 volt part (with 5-volt tolerant
I/O's). So, in order to turn on an LED, the CPLD needs to ground the
LED's lead. (BTW: the LED is -->|-- )
so: [+3.3]-----[R]--->|---- [CPLD pin, or ground.]
LED
>
> The first "simple" program I wrote was to read the switch inputs and
> output them to the LEDs, using the following VHDL code in Xilinx ISE
> 7.1:
>
> ----------------------
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> entity Test1 is
> Port (SWITCH_IN : in std_logic_vector(3 downto 0);
> LEDS_OUT : out std_logic_vector(3 downto 0));
> end Test1;
>
> architecture Behavioral of Test1 is
> begin
> LEDS_OUT <= SWITCH_IN;
> end Behavioral;
> ----------------------
If you had inverted the switches, then you should have seen the
expected behaviour:
LEDS_OUT <= not SWITCH_IN;
>
> This code shows that the LEDs and switches work. I can flip the
> switches and the LEDs change state. But here is the first problem.
> The LEDs light opposite what I expect. The LEDs light when the
> corresponding switch is set to input a high into the CPLD. It's like
> either the inputs or outputs are being inverted inside the CPLD.
>
> So I thought I'd try something simpler -- to turn on all the LEDs by
> outputting "0000" to the four pins the LEDs are connected to. I
> changed the LEDS_OUT assignment to LEDS_OUT <= "0000"; expecting the
> LEDs to turn on. They didn't. So I figured maybe the outputs are
> what's being inverted. I changed it to LEDS_OUT <= "1010"; thinking
> that this way, inverted or not, two LEDs would light and two wouldn't.
> The problem is none of the LEDs light. Remember that I showed that
> both the switches and LEDs can change state with LEDS_OUT <=
> SWITCH_IN;, just backwards from what I expected.
>
> So I remembered from the tutorial that lots of code in VHDL is
> triggered by changes in inputs, so I changed the LEDS_OUT assignment to
> the following:
>
> LEDS_OUT <= "101" & (SWITCH_IN(3) and SWITCH_IN(2) and SWITCH_IN(1)
> and SWITCH_IN(0));
>
> This should kill two birds with one stone. It will show me if I can
> assign pins directly to values when it is part of an equation that
> includes inputs that can change state. I thought mabye my previous
> attempts didn't work since there was nothing to "trigger" the equation.
>
> Also, with ANDing the switches and outputting that to one LED, I can
> tell if it is the inputs or the outputs that are being inverted inside
> the CPLD. If it is the inputs, I would have to set the switches to all
> input a zero before the AND will be active and change the state of the
> LED. "0000" will be the input that causes a different output then the
> other 15 combinations, insted of "1111." If it is the output being
> inverted, I'd have to set the inputs all to one, but the LED will light
> opposite of what I expect, turning on with the inputs all set to one
> (remember the output sinks current from the LED and therefore the LED
> lights when a zero is output).
>
> The result is that the upper 3 LEDs still all remain off, despite
> directly setting two outputs to a one and one output to a zero. My
> logic probe shows a high on those three CPLD pins. Apparently I can't
> directly set a pin even when it is part of an equation.
>
> The last LED lights when all four switch inputs are set to input a
> high. This indicates that the inputs are not being inverted in the
> CPLD. But the LED lights when the switches are all set high and I can
> measure a logic low, 0V, on that LED's pin. This would indicate that
> the outputs are being inverted from the way the assignment equation
> would indicate.
>
> My next experiment was to do something simple - a 4 bit counter right
> from the Xilinx language templates. I ended up with the following VHDL
> code:
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> entity Counter1 is
> Port ( CLK_IN : std_logic;
> SWITCH_IN : in std_logic_vector(3 downto 0);
> LEDS_OUT : out std_logic_vector(3 downto 0));
> end Counter1;
>
> architecture Behavioral of Counter1 is
> signal count : std_logic_vector(3 downto 0) := "0000";
> begin
> process (CLK_IN)
> begin
> if CLK_IN = '1' and CLK_IN'event then
> if SWITCH_IN(0)='1' then
> count <= count + 1;
> else
> count <= count - 1;
> end if;
> end if;
> end process;
> LEDS_OUT <= count;
> end Behavioral;
>
>
> In the simulator this counter works fine, but when I run this code the
> output sequence I get is not a straight count from 0 to 15. I get the
> sequence 0,1,14,3,12,5,10,7,8,9,6,11,4,13,3,15. It is perfectly
> repeatable, and the sequence reverses when I flip SWITCH_IN(0). After
> some looking at the binary for that count sequence, I noticed that
> every second number is the inverse of the previous, instead of the
> expected number (14 is 1110, inverse of 0001 that preceeded it, not
> 0010 as expected next). I don't get it.
>
>
> So my questions are:
> 1. When I do LEDS_OUT <= SWITCH_IN; why does there appear to be an
> inversion happening somewhere inside the CPLD, apparently at the
> outputs?
> 2. Why can't I just set outputs to a zero and have a LED light? Any
> pin I directly assign to a value stays high.
You should be able to assign a 0 to each LED pin, and that should
cause each LED to lite.
LEDS_OUT <= "0000"; or LEDS_OUT <= (others => '0');
> 3. Why doesn't my counter count?
Hmm... I'm a bit puzzled by this, too. Try making an up counter.
Modify your code to count up only, and to not check the switch. Also,
the perferred way to act on a rising edge clock is
if rising_edge( CLK_in ) then
Also:IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED are non-standard
libraries. You're better off using IEEE.NUMERIC_STD, instead.
Out of curiousity, where does CLK_in come from and what is its
frequency?
And do you know that your LEDS_OUT CPLD pins are actually connected to
the LEDs and not something else?
After you've synthesized the code, look at the FITTER report. At the
end of the report, it shows list of chip pins and the name that has
been assigned to each chip pin. If they are wrong, you will need a UCF
(User Constraint File).
The simplest way to do this is to find the UCF that came with you
board, and then select PROJECT->ADD Source and supply the name of the
UCF.
If there is no UCF file, then you'll have to create one. The Process
box should show USER CONTRAINTS. Click on the [+] to expand it and
click on ASSIGN PACKAGE PINS. This will bring up another screen that
shows a drawing of the chip, plus a list of signals. It's then an easy
matter of assigning your signals to the chip so that the signal match
up with how the chip is wired on the board.
>
> It shouldn't be this difficult...
>
> This ended up a lot longer than I expected, so if you made it this far,
> thanks for reading it, and thanks for any help you can provide...
>
> cdsmith
"thanks for reading it" You're welcome. I had a lot of problems like
this when I was just starting out, too. And who knows, perhaps the
board you bought from eBay has problems.
HTH
-Dave Pollum
Article: 94109mk wrote: > On 5 Jan 2006 08:17:58 -0800, fourbeans@gmail.com wrote: > > >>I've known lots of ASIC designers that name their device something cool >>like vader or dilbert. Do people name their FPGA designs as well? >>Anyone know how or why this got started other than the fact that EEs >>are geeks? Was is driven by marketings folks, or maybe the mood the >>designer was in at the time of the design such as ATI's Rage? > > > ASICs are like your children, it takes such a long and ardious time to > make them and once you tape them out you can really never get rid of > them and you can only fix their small mistakes by making small minor > changes without touching their base. You just learn their quirks, make > changes in other pieces of their environment (fix firmware, change > pcb, etc) to accomodate them. That's why people name their ASICs. > FPGAs are at most like a pet you buy for one of your children. If it > becomes too much of a hassle, you just return it or flush it down the > drain and get another one. That's why you don't find named FPGA > designs too often. With attitudes like that, its no wonder why 1000 cats/month are euthanized at the San Jose animal shelter alone.Article: 94110
akhailtash@gmail.com writes: > For the batch mode you need synplify_pro license! Don't ask me why. Not only that, you need a floating license. We have an Amplify fixed license with USB dongle. It does not support batch mode. I think it's a really bad thing to associate other features to the floating/fixed license :-( Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 94111
>What did you use to design the 16V8/22V10's ? >Why not use ABEL, for the 9536 ? >-jg Most commonly was ICT pals with their WinPlace software, but I did use some AMD pals and their ABEL software, way back in about 1995. Neither of these programs will work for the 9536.Article: 94112
I need to know the expected signal skew inside the XC2VP30 (FF1152 package) for the various types of routing resources. Eg. the trace delay in units of time/distance. Has anyone encounter this spec? Additionally, do any of tools provided with ISE 7.1 allow for simulation of an array of synchronous F/F's with all inputs tied to the same net such that SOME F/F's will capture a logic '1' while others will capture a '0' due to the propagation delay of the route?Article: 94113
First, thank you xilinx for moving the functionality previously available in Base-X to the free WebPack. I was somewhat confused by the literature on the website, but a call to support confirmed that the ISE 8.1 WebPack will support all Base-X devices, including the Virtex-4 FX12. However, no one I talked to could confirm if it was possible to use the Virtex-4 hard EMAC primitive without coregen (which is unavailable in WebPack); I have managed to instantiate the "EMAC" in my VHDL design and get synthesis to run, but since I don't have silicon in front of me yet I can't "test" my design. So, is it possible to just use the EMAC primitive like that, without coregen at all? I also can't simulate the part, as the SWIFT simulation models require an advanced ($$$) simulator, but that's a restriction I'm willing to live with. ...EricArticle: 94114
Austin Lesea wrote: > Beanut, > > Typically companies (and government agencies) have provided names for > their internal projects. This seems to be fairly common. > > Mercury, Gemini, Apollo, etc.... > > I have heard some say that this is meant to keep secret/confuse > competition, as saying you are working on 'Pinatubo' gives very little > information as to what you are really working on. It may be for security, but I think it's more that if boards, programs, chips etc. have names everyone involved instantly know what you are talking about > > Personally, I like to think that by calling it something innocuous, it > leaves room for Marketing to decide what they really want to call their > new product. And they often use something boring like xyz123400 and they may decide that they want to sell a reduced version of the same thing with a name xyz123401 > > Artists, mountains, novels, minerals, politicians, movies, anything is > fair game. And related names often mean related projects > > I used titles of novels for one string of releases. It was actually > quite amusing to send out the "Dr. Faustus" release, followed by the > "Paradise Lost" release. > > AustinArticle: 94115
but it's very difficult to get off the ground in a dark, remote place where you don't know anyone and don't speak their language :PArticle: 94116
Jan Decaluwe wrote: > Jim Granville wrote: > >> Do you have any Simulation benchmark indications, > > > Simulation performance is basically limited by the Python > interpreter. Compared to mainstream HDL simulators, I > expect a performance degradation similar to Python versus C. > Therefore, raw simulation performance is not a good argument > in favor of MyHDL at this point. Fortunately, there are > many other good reasons :-) You might be surprised, which was why I was curious. There are functional simulation, and timing simulation tasks, - you might not be as slow as you think, on the functional areas, where higher levels can help. > > > and any > >> simple, example 'complete' side-by-side projects ? >> By simple, I mean things like 16/24/32 bit Up/Dn/ReLoad counter, >> perhaps a DDS as well, and since it seems to have good ROM/RAM >> support, a 7 segment display counter ? > > > No, but it seems like a good idea to set up such a page on > the web site. Perhaps you have a pointer to Verilog/VHDL > code for such relevant designs? I'll see what I can find, and email some to you. Such simple examples are not as common as they should be, on vendors web sites. -jgArticle: 94117
In the current release (ispLEVER v5.1) the MachXO device family does require a Verilog HDL or VHDL synthesis front-end like Precision RTL or Synplify. You can use the schematic editor, however, there's currently no library for gate-level design so it's best used as a block-diagram editor. In the design flow the schematic editor produces a structural model that's read by logic synthesis. I use it today with the latest FPGA families (including XO):to organize RTL modules or those modules generated from IPexpress the module/IP core manager. Meanwhile another option for someone who's trying to migrate a 74xx-class design is a 3rd party EDA schematic front-end like Aldec, Altium (Protel), or Orcad which can also generate EDIF 2 0 0 or structural HDL you can import into FPGA tools. Altium in particular is focused on making this "board-level" design style easy. Troy Scott Lattice Semiconductor TMEArticle: 94118
Hi, PicoBlaze is open source. MicroBlaze is not. JaaCArticle: 94119
On Thu, 05 Jan 2006 13:56:07 -0800, Kunal Shenoy <kunal.shenoy@xilinx.com> wrote: >mk wrote: >> On 5 Jan 2006 08:17:58 -0800, fourbeans@gmail.com wrote: >> >> >>>I've known lots of ASIC designers that name their device something cool >>>like vader or dilbert. Do people name their FPGA designs as well? >>>Anyone know how or why this got started other than the fact that EEs >>>are geeks? Was is driven by marketings folks, or maybe the mood the >>>designer was in at the time of the design such as ATI's Rage? >> >> >> ASICs are like your children, it takes such a long and ardious time to >> make them and once you tape them out you can really never get rid of >> them and you can only fix their small mistakes by making small minor >> changes without touching their base. You just learn their quirks, make >> changes in other pieces of their environment (fix firmware, change >> pcb, etc) to accomodate them. That's why people name their ASICs. >> FPGAs are at most like a pet you buy for one of your children. If it >> becomes too much of a hassle, you just return it or flush it down the >> drain and get another one. That's why you don't find named FPGA >> designs too often. > >With attitudes like that, its no wonder why 1000 cats/month are euthanized at the San Jose animal shelter alone. We have no pets and have no interest in supporting an industry which is about breeding, selling, destroying all the animals and all the feed which goes to them. Did you hear about the couple which left their pets to pet sitters and their two boys home alone to gamble in LV ? There are millions of children in Africa who get AIDS from their mother because they can't afford the drugs necessary to prevent the transmission. My extra money goes to support that and my time for lobbying the government to restrain the pharma companies who protect their IP in sub-saharan Africa.Article: 94120
I've got to get a real newsreader set up insted of using google groups. :-) > so: [+3.3]-----[R]--->|---- [CPLD pin, or ground.] > LED Yup, this is now it is wired. I did that because I noticed that the 9536 can sink a lot more current than it can source. >If you had inverted the switches, then you should have >seen the expected behaviour: > LEDS_OUT <= not SWITCH_IN; I realize that, but I hate doing things like that without understanding why it needs to be done. In the old days when I did PALs the software I used then allowed you to specify a pin as active low, and when an equation came out true, the pin would go low. If I saw something in the documenation like that I would be satisfied and would throw in the not... :-) >You should be able to assign a 0 to each LED pin, and >that should cause each LED to lite. > LEDS_OUT <= "0000"; or LEDS_OUT <= (others => '0'); I tried LEDS_OUT <= "0000" thinking they would all light, but they didn't. I then tried LEDS_OUT <= "1111" thinking that would work if the outputs were being inverted. No dice. So I tried LEDS_OUT <= "1010" thinking two would light and two wouldn't, I don't care which for now, I just want to see something light up. But nothing happens. :-( >> 3. Why doesn't my counter count? >Hmm... I'm a bit puzzled by this, too. Try making an up counter. Will do, tonight. > Also, the perferred way to act on a rising edge clock is > if rising_edge( CLK_in ) then I'll switch to that and see if it makes a difference. I did it the other way because that is what they always did it in the ALDEC VHDL tutorial I learned from. >Also:IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED are non-standard >libraries. You're better off using IEEE.NUMERIC_STD, instead. Those were thrown in there by the Xilinx software when I created a new project. Being new to VHDL, I don't really understand what comes from what libraries yet. :-) >Out of curiousity, where does CLK_in come from and >what is its frequency? It comes from my function generator. Square wave output set to 3.3V. Looks clean on my oscilloscope. I had the frequency low enough that I could watch the count sequence on the LEDS, like around 1Hz. >And do you know that your LEDS_OUT CPLD pins are actually >connected to the LEDs and not something else? Because the expected LEDS do light when I flip switches with "LEDS_OUT <= SWITCH_IN. It's just the polarity in opposite what I expect. Plus, I looked at the board layout to be sure, and took an ohm meter right from the CPLD pins to the header and it measured connected properly. I did do a UCF to assign the pins because I had already wired everything up before I even wrote the program. Which brings up another question. Does it matter if I put CLK on one of the global clock pins? I didn't at first, but moved to to one later. It didn't seem to make any difference on the counter's behavior. >And who knows, perhaps the >board you bought from eBay has problems. Yeah. The company I bought it from has been selling it for years, but I guess that doesn't mean it's guaranteed to work right. I was looking at it since my original post and I realized that it doesn't really have proper bypass capacitors on it. There's just one 100uF electrolytic cap near the CPLD. I suppose if that is causing power problems then I might see issues with things like counters, but not with simple things like running the switches right to the LEDS. I think I'm going to tack solder a few bypass caps to the bottom and see if that changes anything. Thanks for the help. If I figure it all out I'll post here so everyone knows what was wrong.Article: 94121
6-8 week lead times are very common for any IC not just Xilinx FPGA's.... Wecome to the world of semiconductor purchasing. Even #1 Volume customers have to wait that long. 3E parts are just too new for you to expect to pick up 4 of them in less than 1 month.Article: 94122
On Wed, 4 Jan 2006 09:49:21 -0800, "Brendan Illingworth" <billingworth@electrascan.com> wrote: >Hi All, > >I am new to VHDL and am attempting to create an object similar to a parallel >load register. Each FF loads its input from the same signal and all are >clocked by the same signal. In my "entity" definition I desire only the two >inputs as I don't want to use any more IOB's. In the architecture block I >declare a signal that is an N-bit vector (say N=8). However Xilinx ISE 7.1 >seems to optimize out the F/F's becuase they are logically not required. >Here is the question; how does one declare a set of F/F's to be instantiated >in "slices" not "IOB's" whose outputs are not used (to be manually routed >later)? > You can attach an attribute to the signal, (in the architecture part of the VHDL code) that tells the tools not to optimise it away. Depending on the synthesis tool you are using, the attribute can have value "no_opt" or "keep" or "preserve_signal". Check the tool documentation for details. - BrianArticle: 94123
cdsmith69@gmail.com wrote: > So I need some help getting started with programmable logic and VHDL. > > It shouldn't be this difficult... My guess is that you haven't defined which pin on the outside of your CPLD is connected to which signal on the inside of your CPLD. You've ended up with random signals to random pins, defined by the fitting tool to whatever made it's life easiest. The mapping will change every time you modify and resysnthesise the code. You need to add a .ucf file to your project with the signal->pin mappings in it. It's just a text file, the format should look something similar to the following: # DSP bus interface NET "XA<0>" LOC = "p128"; NET "XA<1>" LOC = "p102"; NET "XA<2>" LOC = "p89"; NET "XINT1" LOC = "p130"; NET "CSn" LOC = "p100"; NET "RDn" LOC = "p103"; The .ucf file is also where you add your timing constraints, you should at least have one for your clock (when you're using one). That section will look like: # Timing constraints NET "CLOCK" TNM_NET = "CLOCK"; TIMESPEC "TS_CLOCK" = PERIOD "CLOCK" 8 ns HIGH 50 %; NET "CLOCK" USELOWSKEWLINES; These constraints have been cut from an FPGA project .ucf file, but I'm pretty sure that the syntax is the same for CPLDs. Hope this helps! Cheers, JamesArticle: 94124
On 5 Jan 2006 14:10:02 -0800, langwadt@ieee.org wrote: > >Austin Lesea wrote: >> Beanut, >> >> Typically companies (and government agencies) have provided names for >> their internal projects. This seems to be fairly common. >> >> Mercury, Gemini, Apollo, etc.... >> >> I have heard some say that this is meant to keep secret/confuse >> competition, as saying you are working on 'Pinatubo' gives very little >> information as to what you are really working on. > >It may be for security, but I think it's more that if boards, programs, > >chips etc. have names everyone involved instantly know what you are >talking about ..and of course most projects will be started long before the Marketing Dept. have thought up a flashy name, researched to check that it doesn't clash with an existing product, doesn't mean anything rude or embarrasing in other languages (Like the Mitsubishi Pajero in Spanish, the Toyota MR2 in French etc.) so it needs to be called something in the mantime, and as this initial name will not usually reach the outside world, why not use something silly/amusing/rude etc.
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