Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"Rich Grise, but drunk" wrote:
>
> On Sun, 22 Jan 2006 02:58:27 +0000, Michael A. Terrell wrote:
>
> > No problem. I am starting to lose my close-up eyesight to diabetes,
> > and have to depend on the spell checker. I have severe carpal tunnel
> > (The VA and Shands hospital doctors tell me the surgery won't help me)
> > so I have to type with just a couple fingers. That causes me a lot of
> > spelling errors. I get so busy trying to make sure the spelling is
> > correct that I sometimes forget to check the syntax.
>
> Michael, I think you need some serious therapy to root out these self-
> hatred issues.
Now this is almost funny.
> It's quite difficult to give oneself "carpal tunnel syndrome" - you really
> have to work at it for a long time, while ignoring the pain from your
> wrist. There's an exceedingly simple cure for this - if it hurts, stop.
Yeah, and now you are practicing medicine without a license,
> I've been sitting at a keyboard pretty much all of my waking life for
> about 30 years, and the only time I ever got a _hint_ of "carpal tunnel"
> was when I was holding the mouse in a very awkward position - when my
> wrist said, "This Hurts!" I changed the position of my arm. Voila! No
> "carpal tunnel syndrome"!
So you don't have it. The first signs I got were both hands going
numb while driving, to the point that I couldn't hold onto the steering
wheel. The wrist pain came about a year later. Not everyone notices
the problem right away. As far as stopping when I am in pain, I would
have had to quit working when I was in my early 20s. I don't recall a
day since then that I wasn't in pain, and all of your drunken ranting
won't change that. I also have nerve damage in my left arm that feels
like a small, but constant electrical shock. Unlike you, I didn't try
to self medicate with booze and drugs. I worked as long as I could, but
when I finally threw in the towel, the VA decided that I was 100%
disabled about 40 days from the day I filed. Their paperwork states
that I will never be able to work full time again, so I think they know
about medicine, and my health problems than you do.
>
> You'll get much better when you learn why you hate yourself so much.
There you go with your twisted logic. I don't hate myself, but there
are a few people trying to make that list. The only thing I do hate is
the inability to work 10 to 16 hours a day like I did most of my life. I
couldn't wait for the next challenge to learn new skills and have that
warm feeling of doing something most other people couldn't. I used to
read databooks to relax, and to find inspiration for new projects. Now I
have to use the electronic versions because I have trouble reading the
small print used in the printed versions.
Since you love to push that URL, here is a quote of the day for you
to ponder.
Proverbs 23:9
Speak not in the ears of a fool:
for he will despise the wisdom
of thy words.
--
Service to my country? Been there, Done that, and I've got my DD214 to
prove it.
Member of DAV #85.
Michael A. Terrell
Central Florida
Article: 95551fpga_t...@yahoo.com wrote: > As long as the project didn't inadvertently compile and disclose the > routing > database as the JHDLbits project did, things are probably ok. As Phil > notes though, and others have suggested, one set of tools that would > be interesting would be ones capable of fixing bad nets, and that would > require a database of chip capabilities and architecture that is > currently > only visible from the floor planner and device editors. Extracting that > data and archiving it in a format useable for third party tools is > pretty > much what got the JHDLbits project shut down. This team boldly set out to provide open source access similar to what is proposed before getting shut down by Xilinx. References are a dead sourceforge project, and some papers: http://www.ccm.ece.vt.edu/papers/poetter_2004_ERSA04_jhdlbits.pdf http://www.ccm.ece.vt.edu/papers/poetter_2004_FPL04_jhdlbits.pdf Plus see the teams thesis work: http://www.ccm.ece.vt.edu/papers/Article: 95552
GaLaKtIkUs™ wrote: > Xilinx promised for ISE8.1i a "free add-on module for partial > reconfiguration". But I still don't see it. > Can anybody give me some precisions? > > Mehdi > I guess you are talking about the bus macros used to interconnect static and reconfigurable modules. These are available as .nmc files (placed-and-routed macros) in the XAPP290 reference design files. The appnote also explains why they are required. Kunal@XilinxArticle: 95553
"Chris Hills" <chris@phaedsys.org> wrote in message news:CS+SXxCtVX1DFA+8@phaedsys.demon.co.uk... >>> Ironically as a Chartered Electrical Engineer I am no longer able to do >>> household wiring. You have to be a licensed electrician (it's been the >>> same for domestic Gas fitters for years) . >>> >> >>That is really weird. > > Not really. Qualifications for a professional Electrical Engineer are > not the same as for am electrician. I can design electronics such as RF > transceivers and MCU systems but don't know the (legally required) > Electrical wiring regs for houses. Recently I had a living room dimmer switch die on me (here in the UK). While waiting (10 days) for a qualified electrician, I became tired of the darkness in the living room, bought new dimmer, and fitted it. Despite 40 years of farting around with electrickery, I felt like a very naughty boy. I'd done the calcs, but I mostly work with microamps and nanoseconds. Weirdly enough, I can see the logic. I once lived in a house that a non-techy friend had re-wired. I stayed close to the windows. Steve http://www.fivetrees.comArticle: 95554
Steve at fivetrees wrote: > "Chris Hills" <chris@phaedsys.org> wrote in message > news:CS+SXxCtVX1DFA+8@phaedsys.demon.co.uk... > >>>>Ironically as a Chartered Electrical Engineer I am no longer able to do >>>>household wiring. You have to be a licensed electrician (it's been the >>>>same for domestic Gas fitters for years) . >>>> >>> >>>That is really weird. >> >>Not really. Qualifications for a professional Electrical Engineer are >>not the same as for am electrician. I can design electronics such as RF >>transceivers and MCU systems but don't know the (legally required) >>Electrical wiring regs for houses. > > > Recently I had a living room dimmer switch die on me (here in the UK). While > waiting (10 days) for a qualified electrician, I became tired of the > darkness in the living room, bought new dimmer, and fitted it. Despite 40 > years of farting around with electrickery, I felt like a very naughty boy. > I'd done the calcs, but I mostly work with microamps and nanoseconds. > > Weirdly enough, I can see the logic. I once lived in a house that a > non-techy friend had re-wired. I stayed close to the windows. There are alternative ways for the government to handle these issues and still provide for a safe environment. I live in the US and I installed a 50 ampere, 240 volt subpanel in my garage by myself and I am neither a licensed electrician or engineer. The city required me to file and get approval of a permit, which was a simple drawing showing wire types and sizes and the grounding scheme. After I did the work, an inspector came out and checked it. I had to write the city a check for about $50 for the permit and inspection. A good deal considering I would have had to pay a "professional" somewhere between $750-$1000 in labor to do the job. Do you guys still go around and turn off all the outlets at night?Article: 95555
"Jim Stewart" <jstewart@jkmicro.com> wrote in message news:opWdnQhub9UdD0jeRVn-ug@omsoft.com... >> >> Weirdly enough, I can see the logic. I once lived in a house that a >> non-techy friend had re-wired. I stayed close to the windows. > > There are alternative ways for the government > to handle these issues and still provide for > a safe environment. > > I live in the US and I installed a 50 ampere, > 240 volt subpanel in my garage by myself and > I am neither a licensed electrician or engineer. > > The city required me to file and get approval > of a permit, which was a simple drawing showing > wire types and sizes and the grounding scheme. > After I did the work, an inspector came out > and checked it. I had to write the city a check > for about $50 for the permit and inspection. > A good deal considering I would have had to pay > a "professional" somewhere between $750-$1000 > in labor to do the job. It used to be (here in the UK) that a) *.* would do the wiring, then b) an official from the Electrickery Board would come around and sign it off, for a "nominal fee". In theory, great. In practice, said official would be unlikely to raise floorboards - some would, some just wanted to get off down the pub. > Do you guys still go around and turn off all > the outlets at night? Nah. Nowadays I have kWh meters on the outlets. If I turn them off, they start over. Steve http://www.fivetrees.comArticle: 95556
In article <pan.2006.01.23.22.45.01.221529@example.net>, Rich Grise, but drunk <yahright@example.net> wrote: [....] >> We have detected a flu that is unusually nasty. It isn't the same as last >> year. People have worried for a long time about diseases get around the >> world easily. Now there is one that looks like it could do it. >> > >"We"? You and your research partners? You and your lab assistants? No we as in the part of the human race that keeps up on the news about such things. [....] >Can you say, "Media Hyps"? Yes and I can also use google to look up the information needed to show why the situation today is different. I suggest you give it a try. -- -- kensmith@rahul.net forging knowledgeArticle: 95557
Roger wrote:
> The part is Virtex IIPro. It's not the DCI I'm looking for, it's the on-chip
> 100R termination.
>
What version of ISE?
Are you using the unisim library like this:
library unisim;
use unisim.vcomponents.all;
Or, defining the component yourself?
Instead of using the named suffix I/O buffer, try sticking an
IO_STANDARD of LVDS_25_DT on an input buffer of type IBUF{G}DS
See also Answer Record 17244
Brian
Article: 95558Joerg wrote: > Hello Paul, > > > > > The PE 's giving you refeence/verification do NOT have to be EEs. I just was > > approved to take the exam this April and 2 of my references were licensed > > mechanical PEs, not EE. Don't let this deter you....you can find PEs of any > > field and use for reference. > > > > Interesting. Then I would already know two (civil engineers). Was that > in California? > > I just re-checked the application form here in CA. It looks like it's up > to four refs now and says "These individuals must be licensed as > professional engineers in the discipline for which you are applying". > That would rule out my CE friends. Also, it says you must have been > "engaged" with them, meaning a work relationship. Well, I never designed > any bridges for them ;-) > > That would make it all toast I guess. I never worked with any PEs, just > with one EIT. Sounds like a closed 'cosy club' to me. GrahamArticle: 95559
Thanks for the suggestions. -Jeremy "Jeremy" <jeremy.lees@hotmail.com> wrote in message news:1137829341_9019@sp6iad.superfeed.net... > Greetings, > I've used the Altera/Quartus II tool set for a previous project, and my > next project will likely use the Xilinx/ISE toolset. In Quartus II there > is the ability to define I/O in the top module as virtual pins. This > prevented logic from being synthesized away and having the I/O assigned to > a real pin on the device. Does anybody now how to do this in the > Xilinx/ISE tool set? > > Regards, > Jeremy > > > > ----== Posted via Newsfeeds.Com - Unlimited-Unrestricted-Secure Usenet > News==---- > http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ > Newsgroups > ----= East and West-Coast Server Farms - Total Privacy via Encryption > =---- > ----== Posted via Newsfeeds.Com - Unlimited-Unrestricted-Secure Usenet News==---- http://www.newsfeeds.com The #1 Newsgroup Service in the World! >100,000 Newsgroups ---= East/West-Coast Server Farms - Total Privacy via Encryption =---Article: 95560
In comp.arch.fpga Piotr Wyderski <wyderski@mothers.against.spam-ii.uni.wroc.pl> wrote: > John Larkin wrote: > > > Do you really think Cuba's literacy rate is 99%? > > Yes, I do; I would even say that this rate is very low. Problem is that having a higher than 99% literacy (or a 99.3% iirc) is very hard to impossible to achieve. And the problem is not so much the education system but peopel who have medical conditions that make it impossble for them to ever become fully literate and those who have willfully avoided the educational system or it fruits. > > Best regards > Piotr Wyderski > -- Sander +++ Out of cheese error +++Article: 95561
"Rich Grise, but drunk" <yahright@example.net> wrote in message news:pan.2006.01.23.21.11.10.407271@example.net... > On Mon, 23 Jan 2006 17:11:30 +0100, Frithiof Andreas Jensen wrote: > > "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message > ... > >> Is it our destiny to be rich and well fed, while the rest of the world > >> stays poor and hungry? > > > > Sure - for as long as the rest of the world insist on their right to > > choose a looser culture! > > Looser than what? Gawd - a speling flame !! > And what's a "loose" culture anyway? One where people aren't oppressed > by the authoritarians? In that case, the US is supposed to have the > loosest culture there's ever been on the planet! ;-D Go to "the secular democracy" Turkey, remind them of the Armenians I am sure they will explain in a robust and summary manner how wrong you are. In only a few weeks you will be back on a diplomatic flight. That is the ways of a luser culture!! Boosh want them very same Turks in the EU - Why?? Well, on this side of the water we have come to understand that what Boosh wants is what is good for Boosh not necessarily anyone else. The Europeans O.T.O.H. knows that if one cannot integrate even a few million Turks in the EU, then 50 Million++ is going to be ...err... a challenge. I.O.W. what Boosh really wants is to eliminate a potential competitor bidding for The Oil (and probably suck up to some Saudi islamist claim on Europe up till Vieanna, which is how hide the tide reached last time we kicked them out).Article: 95562
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1138066068.871693.120610@g43g2000cwa.googlegroups.com... > > Antti Lukats wrote: >> " >> if nothing helps open webcase, ie the usual path.well as WebCase support >> is >> now done from China I doubt if that brings anything. > > Antti, you are smart, energetic, and imaginative, but why do you write > such nonsense? > You have no reason to assume that TechSupport for US or Europe would > come out of China. You just made that up, didn't you ? Hurts your > credibility! > Peter Alfke > You right Peter, I am not fair. The life isnt either. But I am not making anything up. This is something I do not do. (Sure I am wrong sometimes, that has happened). 1) All my latest WebCase's are handled from China or at least from people with chinese names. 2) someone else (I assume from US) reported the same for his 3 last WebCases, he also called and reached answer machine in chinese. So thats why I assumed that the _global_ WebCase support has been moved to China/chinese. What I said was/is true for me as to my best knowledge of the time of my writing. I did not pay attention to the WebCase email names until someone else pointed my attention to it, then I looked at my cases and I had to agree that its all handled by chinese now. Maybe it isnt, and it was just a co-incident. And sure a superior suport could also be provided from china. Nothing wrong with. All I was about to say is that I have even less trust (in timely resolved issues) from Xilinx websupport then before (before == when EU support was handled from Ireland and not from China). Maybe China support will be better, only time can tell that, but for the time being I feel that I am my best Xilinx FAE as in vast majority of cases I have had to fix the Xilinx related issues myself. Like yesterday - I take OPB_SPI core, I set SPI clock ratio, send out 2 bytes to SPI. Works with loopback testing. But with external SPI flash it doesnt work. After hours and hours troubleshooting I connect oscilloscope onto SPI clock and what I see? 7 clocks are normal with programmed clock width then clock pulse of 20 nanoseconds, then again 7 normal clocks and again 20 nanoseconds pulse. Sure this works with loopback test code provided with Xilinx. For heavens sake there should a way to get something as simple as SPI master to work without the need of connecting an DSO to the FPGA !? I could not belive that 20ns pulse (1 OPB clock). OPB_SPI is part of EDK for long long time, how come this is possible? Has anyone used it before ? Ok, later on I found some xilinx AR as well, talking about clock glitches when data and clock change at the same time. But when I use EDK, and EDK IP cores, I would expect that at least the simplest ones really work, without the need of scoping the signals or searching AR database for related issues. Or is it too much to hope for? If you work with Xilinx products then things like that happen every other day almost. I talked about this thing with the fellow engineers around, their comment was: "well thats how they do it, let you to find and fix their problems". Sure this is how MicroSoft does it. This is why so many hate MicroSoft. I like FPGA's. I like very much. But my tolerance level of accepting bugs and erratas is getting lower and lower. I am not getting paid to find bugs. So arent others who open WebCases and help Xilinx to fix their products and services. I have stated many times that I could be very valuable testing Xilinx software and helping to improve it, I think others here at c.a.f. have made suggestion that I should have early beta test access. I do not. It took me 3 minutes to cause fatal crash close of ISE 8.1 after it was released. If the Xilinx Software goes worse the same rate, I will never install ISE 10.1 on my workstation. So I am getting more and more frustrated seeing more and more issues with Xilinx products and services. Issues that take my time. Time that I would rather spend with my family or just doing my job, which currently isnt bug hunting. I am still energetic, and I would love to use all of my smart imagination to improve Xilinx products, but being on the field and just fighting with the Xilinx bugs (while it isnt my job) is not helping Xilinx much. It hurts. Anyone. I would like to help, but I just dont how. I have setup open public access bug tracker database where I will enter all the bugs with Xilinx products that I will find. In a small hope that it helps others to save their time to avoid the issues or apply workarounds if those are available. -- Antti Lukats http://www.xilant.comArticle: 95563
"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag news:dr3m9c$igc2@xco-news.xilinx.com... > Antti, > > Now that is just not fair. > > -snip- > > ...WebCase support is >> now done from China I doubt if that brings anything. > > That is just not true. > > Austin > Sorry Austin, sometimes I dont know who is inside of me.. I should have self-censored the post, but I am not making anything up. I commented from my current knowledge. See my longer reply to Peter. -- Antti Lukats http://www.xilant.comArticle: 95564
Gabor wrote: > Browsing through the "about" links I found this brief note > on Usenet posting: > > http://groups.google.com/support/bin/static.py?page=basics.html#flamed actually, more readers need to learn more about trolls, and just not feed them. http://kb.iu.edu/data/afhc.html http://en.wikipedia.org/wiki/Internet_trollArticle: 95565
Austin Lesea wrote: > OK, OK. We have heard you. > As I said, Peter and I will do our best to influence "truth in counting." Does that mean we will see either total power or derating curves for LUT/FF toggles to define power and thermal limits as both a percentage of active logic or size of the active design? While you may not see this as important from a perspective of past uses for traditional hardware design, as reconfigurable computing takes off there is a completely different mindset hitting your market. Software tools WILL be packing active algorithms into devices to get the best computational effciency per device. Good packing WILL yield close to 100% active logic in a device, and yeild exactly what you are mocking: > Sure, go ahead and toggle every single flip flop and IO simultaneously > at max frequency, and I will assure you that you will not like the result. Devices that are by design not expected to be more than 10% active will greatly disappoint their customers. You will increasingly see large applications reduced to netlists which have a very high toggle percentage. The user will see that his application compiles to X number of LUTs, and will be buying devices with just over that number of LUTs to run the application. If the user does not encounter a clear warning to derate the device, then we have a truth in advertising problem. Something akin to purchasing a family car advertised to cruise on the freeway at 75mph with an economy of 35mpg. Customers will not find the car acceptable, if it can only be operated at those speeds for 10 minutes, and require a 50 minute inactive period on the side of the road to cool down because some engineer decided to save a few horsepower by removing the water pump and the rest of the cooling system. Cars are assumed to have short term duty cycles in hours, not minutes. While hardware design engineers may have grown used to the omissions in the data sheet about duty cycles for FPGAs, the new reconfigurable computing market is going to be much less tollerant of devices that can only be operated with a 10% duty cycle, or at 10% of rated capacity. If the data sheet says 1M LUTs capable of 800Mhz, then that is what is expected by end users looking at the data sheets to purchase FPGA's for computing. If the device is really only capable of 10% of 1M LUTs at 800Mhz, then from a reconfigurable computer perspective it's really just that, a 100K LUT device, not a 1Mhz LUT device. Likewise, if there is only one routing solution that will achieve 100% utilization of the device, and a typical reconfigurable computing netlist will be route limited at 65% utilizaton, then a 1M LUT device is NOT a 1M usable LUT device, but rather only a 650K LUT device for typical reconfigurable computing uses. So, this is not the 1980's any more, or even the 1990's ... a new emerging primary market for FPGAs is reconfigurable computing and we need devices which are clearly specified for worst case loads that will be typical ... not the exception ... in that market.Article: 95566
Im designing a module working as an fm0-encoder, the clk and max datarate of which are both 640KHz. It is not complicated when the datarate is lower than 320K, the half of clk. But when the datarate of 640K, the clk frequency, is concerned, the problem comes that I have to change the state at both the rising and falling edge of the clk. Now I am using a mothod via combinational output, which is not so good and expansible as registered output using an FSM. I think that an FSM using DET(dual-edge flip-flop) would work, but I am not sure wether it is recommandable to use det and I don't know how to describe a det using synthesizable Verilog? It would be appreciated very much if some of you can *comments about the det method, *the methed about how to describe a det flip-flop thans a lot for any help!Article: 95567
fpga_toys@yahoo.com wrote: > absoulutly true ... but not the whole thread, or even vary many of the > authors in the thread ... the brash branding of the entire thread, even For those that missed it, there is a long wonderful thread in the middle of the junk regarding EE's and PE's by people like Ray that are always generally respected in this forum. The brash branding of the entire thread is knee jerk - ignore the trolls, follow the content.Article: 95568
Hello, I get trouble to run a project(synthetize and p&r) It complete sucessfully all the steps but it doesn't validate it so when I try to remake just one step like the P&R it restarts also the synthetize as it has never been done. Also when I made a step instead of putting a green mark on this step when it have been done , it puts a a point of interrogation ( and not a red cross) for example : I make my project and synthetize it . ISE says me that it have been completed but it keeps the point of interrogation. Then I run the Implement Step and it restarts the synthetize first. As if I have done a a rerun command. If I make a full run (synthetize+translate+map+P&R) It validates all steps when they are finish (but still running the next step) with the green mark but when it finish the run all the step are unvalidate ( by a ? sign) does anyone have already meet these problem? I have already try to reinstall ISE (6.3 sp3) and remake all the project (just keeping the vhd) Thanks you for your answer. alexArticle: 95569
Antti Lukats wrote: <snip> > You right Peter, > > I am not fair. The life isnt either. > > But I am not making anything up. This is something I do not do. (Sure I am > wrong sometimes, that has happened). > > 1) All my latest WebCase's are handled from China or at least from people > with chinese names. > 2) someone else (I assume from US) reported the same for his 3 last > WebCases, he also called and reached answer machine in chinese. > > So thats why I assumed that the _global_ WebCase support has been moved to > China/chinese. What I said was/is true for me as to my best knowledge of the > time of my writing. <snip> That's quite a large leap, Antti, from 'Chinese name' to 'Must live in China' - did you check the email time tags, that often gives a clue to the time zones you are working between ? China <-> EU is not the most natural choice ? -jgArticle: 95570
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:43d60cb2$1@clear.net.nz... > Antti Lukats wrote: > > <snip> >> You right Peter, >> >> I am not fair. The life isnt either. >> >> But I am not making anything up. This is something I do not do. (Sure I >> am wrong sometimes, that has happened). >> >> 1) All my latest WebCase's are handled from China or at least from people >> with chinese names. >> 2) someone else (I assume from US) reported the same for his 3 last >> WebCases, he also called and reached answer machine in chinese. >> >> So thats why I assumed that the _global_ WebCase support has been moved >> to China/chinese. What I said was/is true for me as to my best knowledge >> of the time of my writing. > > <snip> > > That's quite a large leap, Antti, from 'Chinese name' to 'Must live in > China' - did you check the email time tags, that often gives a clue to the > time zones you are working between ? > China <-> EU is not the most natural choice ? > > -jg > maybe I mis-judged. I havent checked the email header time tags. Some else (also having Xilinx issues) was complaining about the answer machine on his WebCase contact to respond in chinese, so I checked the names from emails and found his assumptions about the WebCases now being handled by people with chinese like names to be true. Maybe I am too hard at (Xilinx WebCase support) as my issues are usually not such that the WebCase assigned person has any chances to help. He always needs to contact others and that makes it really long to get some meaningful response. So I do not really have hopes that a WebCase helps if it is not 'accelerated' but then ah, it makes possible more sense to immediate 'accelerate' the issue, and that is something that Xilinx doesnt like of course. But if immediate acceleration of an issue brings the solution even a few hours faster then it is a few hours won. I am pretty sure that there are people at Xilinx who are thinking very seriously how to actually improve the software, support and services so lets hope it will get better. There is lots of space for improvements, in all areas. -- Antti Lukats http://www.xilant.comArticle: 95571
yyqonline schrieb: > Im designing a module working as an fm0-encoder, the clk and max > datarate of which are both 640KHz. It is not complicated when the > datarate is lower than 320K, the half of clk. But when the datarate of > 640K, the clk frequency, is concerned, the problem comes that I have to > change the state at both the rising and falling edge of the clk. Now I > am using a mothod via combinational output, which is not so good and > expansible as registered output using an FSM. I think that an FSM using > DET(dual-edge flip-flop) would work, but I am not sure wether it is > recommandable to use det and I don't know how to describe a det using > synthesizable Verilog? > It would be appreciated very much if some of you can > *comments about the det method, > *the methed about how to describe a det flip-flop > > thans a lot for any help! It is not difficult to driscrobe dual-edge flip-flop in an HDL. The real question is: Can you build them in your target technology? Most FPGAs do not have them and most standard cell libraries do not have them either. Kolja SulimmaArticle: 95572
Frank Bemelman wrote: > "Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> schreef in bericht > news:5uj9t1dkjk5q89v8t977rqi4ts3bag7n6a@4ax.com... > > On Mon, 23 Jan 2006 09:46:44 +0100, the renowned "Frank Bemelman" > > <f.bemelmanq@xs4all.invalid.nl> wrote: > > > > ><bill.sloman@ieee.org> schreef in bericht > > >news:1137987045.839508.7650@o13g2000cwo.googlegroups.com... > > >> > > >> Good for Slovenia! The Netherlands is acquiring a culture of eating > > >> well - we now have three restaurants with three Michelin stars - but > > >> there is a long way to go. It a Dutch person recommends a restaurant to > > >> you, you can be fairly sure that the decor, ambience and service will > > >> all be okay, but the food can be total rubbish. > > > > > >It is indeed a long way to go, if the goal is three Michelin star food > > >for everyone, everyday. > > > > > >Sheesh! > > > > > >;) > > > > Doesn't sound like a bad goal. Instead of food insecurity you'd have > > to worry about the prevalence of gout. > > I'm getting more worried about my wallet, and what's in it. Bill is a > snob of course, as most Michelin star restaurants customers are. I doubt if I qualify as a food snob. I'm a bit too willing to eat a good pizza - particularly since the cute Italian post-doc charmed Nijmegens good pizza place into stocking Amarone (which lead to us paying twice as much for the wine as for the pizza, until the proprietor realised that if his pizzas were good enough to eat with Amraone he could get away with charging more for them). > Last > friday I had the pleasure of a dinner at Ron Blaauw's Palazzo, in > Amsterdam. http://www.egol.de/palazzo/amsterdam/gaenge/e_gaenge_8_a.php > Ron Blaauw is good for 1 star, so the food was excellent. But not too fancy. With two Michelin stars they can do everything perfectly, but are unlikely to surprise you. For three stars, they need to do everything perfectly and be inventive to boot - though three-star restaurants in France can be a bit dissappointing for a few years before the inspectors finally lower the boom. The owner-chef of the restaurant de la Cote d'Or in Saulieu - Bernard Loiseau - shot himself after the Gault Millau guide downgraded him from 19 points to 17, so you can understand the reluctance of the inspectors. > But at this level, > the amount of joy has not much to do with the food. It's a sum of everything > that surrounds it, and probably the most important ingredient of any good > dinner is how you and your guests are feeling themselves. Frank, you very Dutch! The service and the ambience are just the wrapping paper around the food. Of course the joy a group gets out of eating together is only incidentally affected by the food they eat, but the food is what the restaurant is supplying - the joy we have to find for ourselves! <snipped prices> -- Bill Sloman, NijmegenArticle: 95573
Guys Does anyone know whether ISE simulator lite will simulate the RocketIOs on the virtex 4 that webpack supports? I have a simulator that doesn't support smartmodels so I could live with the poor performance of simulator lite just to check the rocket IO bit of my design. regards ColinArticle: 95574
In comp.arch.fpga Rich Grise, but drunk <yahright@example.net> wrote: : But I'm probably biased - I apparently have mostly German Blood, which : is probably why the "Americanized" version of my family name is so hard : to pronounce. I've always wondered, does the American surname Straub originate from a mis-reading of Strauss with an Eszett (German double-s) ? Richard http://www.rtrussell.co.uk/ To reply by email change 'news' to my forename.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z