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Hi, I want to design a development board containing Xilinx Spartan-3 XC3S400. My problem is regarding the number and values of bypass capacitors that I should use for the power supplies. I use 3 power supplies: VCCINT=3D1.2V; VCCAUX=3D2.5V; VCCO=3D3.3V. I took the Spartan-3 Starter Kit Board User Guide (http://direct.xilinx.com/bvdocs/userguides/ug130.pdf) as a refernce, but I fond it contradicts XAPP623 - Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors (http://direct.xilinx.com/bvdocs/appnotes/xapp623.pdf). XAPP623 recommends for every power supply: =3DCapacitor=3D =3DValue Quantity Percentage=3D 470 =B5F to 1000 =B5F 4% 1=2E0 to 4.7 =B5F 14% 0=2E1 to 0.47 =B5F 27% 0=2E01 to 0.047 =B5F 55% Therefore... Bypass caps for VCCINT/VCCAUX (8 pins) according to XAPP623 =3DValue range=3D =3DNo. of Caps=3D 470 =B5F to 1000 =B5F 8 pins x 4%=3D 0.32(0) 1=2E0 to 4.7 =B5F 8 pins x14%=3D 1.12(1) 0=2E1 to 0.47 =B5F 8 pins x27%=3D 2.16(2) 0=2E01 to 0.047 =B5F 8 pins x55%=3D 4.4(5) Bypass caps for VCCO (24 pins) according to XAPP623 =3DValue range=3D =3DNo. of Caps=3D 470 =B5F to 1000 =B5F 24 pins x 4%=3D 0.96(1) 1=2E0 to 4.7 =B5F 24 pins x14%=3D 3.36(3) 0=2E1 to 0.47 =B5F 24 pins x27%=3D 6.48(7) 0=2E01 to 0.047 =B5F 24 pins x55%=3D 13.2(13) _______________ But Spartan-3 Starter Kit Board uses: For VCCINT =3DNo. of Caps=3D 2 x 10uF 6 x 0.01uF 10 x 0.047uF For VCCAUX =3DNo. of Caps=3D 1 x 10uF 16 x 0.01uF For VCCO =3DNo. of Caps=3D 3 x 10uF 32 x 0.047uF I would like to know how the Spartan-3 Starter Kit Board got those calculations and why it didn't use the XAPP623 recommendations and which one is better for me to choose? =20 Thank you very much JJArticle: 107676
First, please note that the Spartan-3 starter kit was not designed by Xilinx. Digilentinc.com is where you should find the trail ending. Just because a manufacturer recommends something doesn't mean board developers are going to follow it. Glancing through XAPP623, it's surprising how many points we've *just* been talking about this last week here on this forum are touched upon. As that discussion went, there's more than one approach to a solution that can work for your needs. One suggestion I'd give regarding your cap numbers: round up. The numbers you have may work very well. There's no guarantee that it's the "best" or most appropriate solution for the board you need. In the XAPP623 example, there's no adjustment to capacitor count for plane spacing demonstrating where "all" the information might not be there. One suggestion: buy a book from a guy named Ritchey. Just search on this group for his name using google or similar search tool and you'll find many posts from this past week. More ideas are presented in those posts. jidan1@hotmail.com wrote: > Hi, > > I want to design a development board containing Xilinx Spartan-3 > XC3S400. My problem is regarding the number and values of bypass > capacitors that I should use for the power supplies. > I use 3 power supplies: VCCINT=1.2V; VCCAUX=2.5V; VCCO=3.3V. > I took the Spartan-3 Starter Kit Board User Guide > (http://direct.xilinx.com/bvdocs/userguides/ug130.pdf) as a refernce, > but I fond it contradicts XAPP623 - Power Distribution System (PDS) > Design: Using Bypass/Decoupling Capacitors > (http://direct.xilinx.com/bvdocs/appnotes/xapp623.pdf). > > XAPP623 recommends for every power supply: > =Capacitor= =Value Quantity Percentage= > 470 µF to 1000 µF 4% > 1.0 to 4.7 µF 14% > 0.1 to 0.47 µF 27% > 0.01 to 0.047 µF 55% > > Therefore... > > Bypass caps for VCCINT/VCCAUX (8 pins) according to XAPP623 > =Value range= =No. of Caps= > 470 µF to 1000 µF 8 pins x 4%= 0.32(0) > 1.0 to 4.7 µF 8 pins x14%= 1.12(1) > 0.1 to 0.47 µF 8 pins x27%= 2.16(2) > 0.01 to 0.047 µF 8 pins x55%= 4.4(5) > > Bypass caps for VCCO (24 pins) according to XAPP623 > =Value range= =No. of Caps= > 470 µF to 1000 µF 24 pins x 4%= 0.96(1) > 1.0 to 4.7 µF 24 pins x14%= 3.36(3) > 0.1 to 0.47 µF 24 pins x27%= 6.48(7) > 0.01 to 0.047 µF 24 pins x55%= 13.2(13) > > _______________ > But Spartan-3 Starter Kit Board uses: > For VCCINT > =No. of Caps= > 2 x 10uF > 6 x 0.01uF > 10 x 0.047uF > > For VCCAUX > =No. of Caps= > 1 x 10uF > 16 x 0.01uF > > For VCCO > =No. of Caps= > 3 x 10uF > 32 x 0.047uF > > I would like to know how the Spartan-3 Starter Kit Board got those > calculations and why it didn't use the XAPP623 recommendations and > which one is better for me to choose? > > Thank you very much > JJ >Article: 107677
see http://groups.google.com/group/comp.arch.fpga?lnk=gschg&hl=en
and look at the thread:
"placing addiional caps across existing caps to reduce noise"
Article: 107678Hi, Is there any method to increase number of verilog modules/instances in a single verilog file, While sythesizing with Xilinx Project navigator? If there are more than about 50 modules in a single verilog file it is not taken by project navigator, and it shows a '?' ahead of these modules. Like the modules are missing but actually they are not. If any one have some solution, please put forward. Thanks n regards, JitenArticle: 107679
Who has once used the fft ip core: xfft v2.0? Can you gave me some advice?Article: 107680
"Andy" <jonesandy@comcast.net> writes: > Take a look at Mentor's Catapult C. Thanks - I shall take another look, it's been a while since I looked at that. Sounds a lot like what AccelDSP does for Matlab scripts. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 107681
"Symon" <symon_brewer@hotmail.com> writes: > I contend that the package impedance of modern FPGAs is such that any > benefit that a board wide power plane's capacitance could provide to your > design, over and above that which you can get from a small local plane and > associated bypass capacitors, is negligible. The caps work up to a few > hundred MHz, just about where the package stops working. Any noise on the > supply above this frequency doesn't get to the silicon anyway. I'll chip in one more point (which I have not data for, but discussion may be enlightening :-).. Even above the frequency at which the die won't see the noise due to the package inductance, the noise on the planes may still cause problems in passing EMC emissions tests, so you still have to be careful at the top end. Out of interest - do you consider how your mini-planes resonate at high frequencies? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 107682
Hi, I am exploring the possibility to use the npi(native port interface) towards the MPMC2(multi port memory controller). I will use the BRAM as FIFO on the write side of the RAM Does anyone have any experience with this ? After reading the documentation(http://www.xilinx.com/esp/wired/optical/xlnx_net/mpmc2/ug253.pdf) I am left with a lot of questions. I am not able to find any other documentation/user experience. I want to use the timing as described in figure 37: Word write My main questions are: 1. How long can the delay between AddrReq and AddrAck be ? If this can be of arbitrary length(as claimed in the documentation) one need to buffer the data before the npi to ensure not to loose data. 2. Our memory has 32 bits datalength, while npi uses 64 bits. How is the data alignment between this two busses ? Any comments/answers will be greatly appreciated !Article: 107683
rickman wrote: > David Brown wrote: >> Thanks for taking the time explaining this - between you and Symon I'm >> hopefully learning something! > > I had written a reply to this post, but I hit a wrong button as I typed > and POOF! So here it is again... > >> However, I've a couple of issues here. First off, I can't see that the >> power planes have much capacitive effect at these frequencies (the >> "planes" being polygons, with other signals on the same layer, and thus >> having plenty of gaps). But I'll happily admit to not having a clear >> idea how to model such planes or polygons. > > If your planes are not designed to have good capacitance, then they > won't. They need to be complete on thier own layer and closely spaced. > It is not hard to get nFs from planes with very low inductance. > > >> Secondly, I understand about different caps working better at different >> frequencies, and obviously have bulk capacitors for the lower >> frequencies (electrolytics near the regulators, and a few 4.7uF ceramics >> around the board). But I still can't find any reason to expect a 0.001 >> uF ceramic 0603 capacitor to be significantly better at higher >> frequencies than a 0.1 uF ceramic (same dialectric) 0603 capacitor. > > It is not just that the caps work at different frequencies, it is how > they work with the power planes. A cap closely coupled to the power > planes will have a resonance (or anti-resonance) which will create a > *higher* impedance in that range of frequencies than either the cap or > plane alone. If you pick a cap of small value and low Q (high ESR) it > will have a low amplitude resonance, high in frequency. This same cap > will require a lot of them to provide effective coupling at lower > frequencies. So you can then use a smaller number of larger value caps > to provide a lowered impedance at lower frequencies. Again it is > important to not use parts with a high Q as this will raise the > amplitude of the impedance peaks due to parallel resonance. By using a > range of cap values the impedance is kept low across a wide range of > frequency and the resonances are kept to a minimum. > I'm now beginning to get a better idea of the parallel resonance problem. In particular, it's the high Q of the plane capacitor that causes the biggest issue. > >> Using the muRata software, I picked a 0603 X7R 100 nF capacitor. The >> software gives it an SRF of 21 MHz, L of 0.63 nH, R of 0.027 O, and an >> impedance of 0.14 ohm at 10 MHz, 0.02 ohm at 20 MHz, 0.16 ohm at 50 MHz, >> 0.38 ohm at 100 MHz, 0.78 at 200 MHz, and 1.97 ohm at 500 MHz. Picking >> a 10 nF cap with the same setup gives an SFR of 67 MHz, and impedances >> at these frequencies of 1.66, 0.77, 0.16, 0.24, 0.71 and 1.95 ohms. In >> other words, it is a better at around 100 MHz, but not vastly better. >> Until we start looking at special 0306 caps for frequencies of several >> hundred MHz, I just don't see the benefit of smaller capacitance values. >> Even then, it is more economical to simply use a few extra caps of the >> same type (assuming the board has space for it). > > But this does not take the parallel resonance into account. If > parallel resonance did not matter we could decouple everything with a > few tantalum caps. > You're right - I've been looking at the capacitors separately rather than how they affect each other. The card is not nearly as advanced as many of the cards made by people in this group - it's highest frequencies are in the 150 MHz range, with relatively few fast traces (there is a databus to an sdram chip, but the only lines I really have to be careful with are the clocks to the sdram chips at 75 MHz), and everything is fairly low power. What you (and Symon) have given me is a number of ideas about the problems on higher speed cards, and possible solutions to the problems, along with a better understanding of what I don't know and need to learn about if I am ever involved in making faster cards. I'm not a specialist in this field (I'm mainly an embedded programmer), and know that cards using the bigger and faster FPGAs would be completely out of my depth, but I appreciate the tips I pick up here for my cards anyway. > >> It doesn't even take that many caps - I've got about a dozen for the >> processor (which as two main supplies and a PLL supply), two or three >> for each of the sdram chips, and one or two for each of the other major >> chips. > > It sounds like this is a simple design, but have you tested worse case? > Try the situation where the address and data bus both change from all > 0s to all 1s at the same moment (assuming this processor can do that). > The DSP I last designed with would switch both data and address busses > at the same time. Put a high speed scope probe (with a very short > ground) on a separate output from this part that is set to a 1 and > watch the glitch, that is your total bounce including the inductance > from the power pins and the plane bounce. Also measure the glitch on a > power pin and you will have just the power plane noise. After you > consider this noise and the other sources such as crosstalk, can you > tell if your design is quiet enough. Testing won't do it unless you > explicitly test your worst cases. > I've done some worst-case (or close to worst case) testing of the databus, but it would probably be a good idea to do some better measurements during such tests. > >> One thing that makes a significant difference is that I'm not driving >> any fast, high current lines - signalling is (almost) all TTL levels. >> Higher current drives would mean more capacitors, but I'd still expect >> to use the same types. > > If you are driving with fast edges, you are driving high current. > Series terminated 3.3 volt CMOS driving a 50 ohm transmission line will > drive 33 mA per line. It will be much higher if it is not series > terminated. Multiply that by 64 and you get 2 Amps! Did you consider > this much current in your decoupling calculations? If you don't supply > the current from the power plane the caps can't really keep up with the > fast rise time of many drivers (< 1 ns). It will create high noise on > the planes and can trigger bounce logic level problems. > I've done some rough calculations, but the drivers are not that fast - although I appreciate the levels of the current spikes. I have not seen any indications of noise problems or bounce, but perhaps I need to do some more careful measurements. > If you are using an MCU with fully internal memory then we are talking > about a different class of design and you can get by with a dozen or so > of single value caps. > The memory is not internal on this MCU, but I agree it's a different class to designs using much higher speed devices and signals. I'm not overly concerned about this design, but perhaps future cards will have DDR memory and need more care.Article: 107684
Symon ha escrito: > > 1) Rick's teacher has presented a way to prevent resonances between bypass > caps and power planes. These resonances can be substantial because of the > high Q of the plane capacitance. He prevents this serious resonance by us= ing > a bunch of different valued capacitors to move and spread out the resonan= ce. > This introduces new parallel resonances between these different valued ca= ps, > but these aren't as bad as the original plane resonance because the caps > have low Q. There is still one thing that I don=B4t fully understand about Rick's method. The resonance of the power plane capacitance with the capacitors inductance depends on the number and package of the capacitors ( the capacitors inductance is related to the package). I don=B4t see how changing the capacitors value (capacitive) can modify the position or peak of that resonce. IMHO 20 0.1uF capacitors will have the same resonance with the power plane as 20 0.001uF capacitors (or even 10 0.01uF plus 10 0.001uF) So far I've been decoupling using different value capacitors because that's the method that Xilinx recomends, but whithout seeing much logic in the use of small value capacitors (if higher value can be used in the same package). Now I think that Simon=B4s metod makes more sense. RegardsArticle: 107685
Peter Alfke wrote > I'll try to get over this, and will fly to Madrid for the European FPL > conference. Safe journey. But before you go, is your HotChips talk about V5 up on the web? TimArticle: 107686
David Brown wrote: > rickman wrote: > > David Brown wrote: > >> Thanks for taking the time explaining this - between you and Symon I'm > >> hopefully learning something! > > > > I had written a reply to this post, but I hit a wrong button as I typed > > and POOF! So here it is again... > > > >> However, I've a couple of issues here. First off, I can't see that the > >> power planes have much capacitive effect at these frequencies (the > >> "planes" being polygons, with other signals on the same layer, and thus > >> having plenty of gaps). But I'll happily admit to not having a clear > >> idea how to model such planes or polygons. > > > > If your planes are not designed to have good capacitance, then they > > won't. They need to be complete on thier own layer and closely spaced. > > It is not hard to get nFs from planes with very low inductance. > > > > > >> Secondly, I understand about different caps working better at different > >> frequencies, and obviously have bulk capacitors for the lower > >> frequencies (electrolytics near the regulators, and a few 4.7uF ceramics > >> around the board). But I still can't find any reason to expect a 0.001 > >> uF ceramic 0603 capacitor to be significantly better at higher > >> frequencies than a 0.1 uF ceramic (same dialectric) 0603 capacitor. > > > > It is not just that the caps work at different frequencies, it is how > > they work with the power planes. A cap closely coupled to the power > > planes will have a resonance (or anti-resonance) which will create a > > *higher* impedance in that range of frequencies than either the cap or > > plane alone. If you pick a cap of small value and low Q (high ESR) it > > will have a low amplitude resonance, high in frequency. This same cap > > will require a lot of them to provide effective coupling at lower > > frequencies. So you can then use a smaller number of larger value caps > > to provide a lowered impedance at lower frequencies. Again it is > > important to not use parts with a high Q as this will raise the > > amplitude of the impedance peaks due to parallel resonance. By using a > > range of cap values the impedance is kept low across a wide range of > > frequency and the resonances are kept to a minimum. > > > > I'm now beginning to get a better idea of the parallel resonance > problem. In particular, it's the high Q of the plane capacitor that > causes the biggest issue. > > > > >> Using the muRata software, I picked a 0603 X7R 100 nF capacitor. The > >> software gives it an SRF of 21 MHz, L of 0.63 nH, R of 0.027 O, and an > >> impedance of 0.14 ohm at 10 MHz, 0.02 ohm at 20 MHz, 0.16 ohm at 50 MHz, > >> 0.38 ohm at 100 MHz, 0.78 at 200 MHz, and 1.97 ohm at 500 MHz. Picking > >> a 10 nF cap with the same setup gives an SFR of 67 MHz, and impedances > >> at these frequencies of 1.66, 0.77, 0.16, 0.24, 0.71 and 1.95 ohms. In > >> other words, it is a better at around 100 MHz, but not vastly better. > >> Until we start looking at special 0306 caps for frequencies of several > >> hundred MHz, I just don't see the benefit of smaller capacitance values. > >> Even then, it is more economical to simply use a few extra caps of the > >> same type (assuming the board has space for it). > > > > But this does not take the parallel resonance into account. If > > parallel resonance did not matter we could decouple everything with a > > few tantalum caps. > > > > You're right - I've been looking at the capacitors separately rather > than how they affect each other. > > The card is not nearly as advanced as many of the cards made by people > in this group - it's highest frequencies are in the 150 MHz range, with > relatively few fast traces (there is a databus to an sdram chip, but the > only lines I really have to be careful with are the clocks to the sdram > chips at 75 MHz), and everything is fairly low power. > > What you (and Symon) have given me is a number of ideas about the > problems on higher speed cards, and possible solutions to the problems, > along with a better understanding of what I don't know and need to learn > about if I am ever involved in making faster cards. I'm not a > specialist in this field (I'm mainly an embedded programmer), and know > that cards using the bigger and faster FPGAs would be completely out of > my depth, but I appreciate the tips I pick up here for my cards anyway. > > > > >> It doesn't even take that many caps - I've got about a dozen for the > >> processor (which as two main supplies and a PLL supply), two or three > >> for each of the sdram chips, and one or two for each of the other major > >> chips. > > > > It sounds like this is a simple design, but have you tested worse case? > > Try the situation where the address and data bus both change from all > > 0s to all 1s at the same moment (assuming this processor can do that). > > The DSP I last designed with would switch both data and address busses > > at the same time. Put a high speed scope probe (with a very short > > ground) on a separate output from this part that is set to a 1 and > > watch the glitch, that is your total bounce including the inductance > > from the power pins and the plane bounce. Also measure the glitch on a > > power pin and you will have just the power plane noise. After you > > consider this noise and the other sources such as crosstalk, can you > > tell if your design is quiet enough. Testing won't do it unless you > > explicitly test your worst cases. > > > > I've done some worst-case (or close to worst case) testing of the > databus, but it would probably be a good idea to do some better > measurements during such tests. > > > > >> One thing that makes a significant difference is that I'm not driving > >> any fast, high current lines - signalling is (almost) all TTL levels. > >> Higher current drives would mean more capacitors, but I'd still expect > >> to use the same types. > > > > If you are driving with fast edges, you are driving high current. > > Series terminated 3.3 volt CMOS driving a 50 ohm transmission line will > > drive 33 mA per line. It will be much higher if it is not series > > terminated. Multiply that by 64 and you get 2 Amps! Did you consider > > this much current in your decoupling calculations? If you don't supply > > the current from the power plane the caps can't really keep up with the > > fast rise time of many drivers (< 1 ns). It will create high noise on > > the planes and can trigger bounce logic level problems. > > > > I've done some rough calculations, but the drivers are not that fast - > although I appreciate the levels of the current spikes. I have not seen > any indications of noise problems or bounce, but perhaps I need to do > some more careful measurements. > > > If you are using an MCU with fully internal memory then we are talking > > about a different class of design and you can get by with a dozen or so > > of single value caps. > > > > The memory is not internal on this MCU, but I agree it's a different > class to designs using much higher speed devices and signals. I'm not > overly concerned about this design, but perhaps future cards will have > DDR memory and need more care. Do you know the edge rate of your drivers on the SDRAM interface? They are likley sub-nanosecond which means you need to consider both the SI issues and the power distribution issues. It was not that long ago that many PC motherboards could not work correctly with a third or fourth SDRAM module plugged in because they did not do their homework on SI issues. Now we are up to DDR2 speeds and are seeing the same problems. But that does not mean you can ignore SDRAM SI issues. The circuits are still the same and the edge rates can get you if you don't give them their proper attention. If you have a working board you can measure the ground/power bounce rather easily. I think I described it before, but here it is again. Write code to switch all the data bus and address bus signals in the same direction at one time. Set some other output near these pins to a constant level. Watch this constant output and see if you get a glitch on this pin when the others change. This is the amplitude of the bounce on your device. There may be additional noise on the power/ground planes that comes from other chips so this may not be the worst case noise the chip will see. On a separate note, I can't believe some of the things we do here. Our digital circuits are part of RF equipment so we are typically very concerned with even low levels of noise in the RF region. To make sure our boards are quiet we have an RF person review the design and board layout. I was assisting on a design for a simple MCU board with an attached GPS receiver. The RF guy was very concerned about various noise sources that had burned him in the past and did a lot of what I thought was overkill in the power distribution. I just found out that he had the 6 layer stackup done with two ground planes and no power plane! I suggested to the layout guy that it would be ok to flood fill the signal layers with power plane and he said they are doing that, but connecting to ground instead of power!!! So there is no effective bypassing on this board above a couple hundred MHz and the freq of the receiver is around 1.5 GHz. Do you think we will see any interference?Article: 107687
Martin Thompson wrote: > "Symon" <symon_brewer@hotmail.com> writes: > > >> I contend that the package impedance of modern FPGAs is such that any >> benefit that a board wide power plane's capacitance could provide to your >> design, over and above that which you can get from a small local plane and >> associated bypass capacitors, is negligible. The caps work up to a few >> hundred MHz, just about where the package stops working. Any noise on the >> supply above this frequency doesn't get to the silicon anyway. > > I'll chip in one more point (which I have not data for, but discussion > may be enlightening :-).. > > Even above the frequency at which the die won't see the noise due to > the package inductance, the noise on the planes may still cause > problems in passing EMC emissions tests, so you still have to be > careful at the top end. > > Out of interest - do you consider how your mini-planes resonate at > high frequencies? > > Cheers, > Martin The data I saw suggested that larger boards have plane resonance issues at lower frequencies. The mini-plane approach would deliver less overall capacitance compared to a full plane but the resonances would be much higher in frequency since the transmission-line effects of the "open" at the board edge have a much shorter quarter-wavelength for a higher frequency before plane resonance.Article: 107688
al82 wrote: > Symon ha escrito: > > > > > 1) Rick's teacher has presented a way to prevent resonances between byp= ass > > caps and power planes. These resonances can be substantial because of t= he > > high Q of the plane capacitance. He prevents this serious resonance by = using > > a bunch of different valued capacitors to move and spread out the reson= ance. > > This introduces new parallel resonances between these different valued = caps, > > but these aren't as bad as the original plane resonance because the caps > > have low Q. > > > There is still one thing that I don=B4t fully understand about Rick's > method. > The resonance of the power plane capacitance with the capacitors > inductance depends on the number and package of the capacitors ( the > capacitors inductance is related to the package). I don=B4t see how > changing the capacitors value (capacitive) can modify the position or > peak of that resonce. > IMHO 20 0.1uF capacitors will have the same resonance with the power > plane as 20 0.001uF capacitors (or even 10 0.01uF plus 10 0.001uF) > > So far I've been decoupling using different value capacitors because > that's the method that Xilinx recomends, but whithout seeing much logic > in the use of small value capacitors (if higher value can be used in > the same package). Now I think that Simon=B4s metod makes more sense. The problem with trying to analyze this sort of design is that the board does what it wants and does not care what you or I think it should do. If you want to understand what is happening, you can read Ritchey's book or you can do some simulations and measurements yourself. Obviously others are not convinced, but what I learned in this course and read in his book has me convinced about the utility of the method. I don't want to criticize anyone else's technique since I can't say for sure what will work and what won't. But analyzing a design on paper can give you a false sense of security until you simulate it or test it. Rather than state an opinion, try it! On the other hand, you should also consider that the SRF of the different value caps is different. So why would they have the same resonance when coupled to a plane?Article: 107689
John_H wrote: > The data I saw suggested that larger boards have plane resonance issues > at lower frequencies. The mini-plane approach would deliver less > overall capacitance compared to a full plane but the resonances would be > much higher in frequency since the transmission-line effects of the > "open" at the board edge have a much shorter quarter-wavelength for a > higher frequency before plane resonance. Yes, if you eliminate the plane altogether you will not have any resonances!!! A resonance is not totally bad. It is only bad if the impedance is above the level that you can tolerate. The goal is to maintain a low impedance over a wide range of frequencies. If you make the plane smaller you may push the resonance higher in frequency, but you also increase the impedance across the high end of the band. At edge rates of a nanosecond or less, the power plane capacitance is the only capacitance that is effective to preserve the edge and to reduce the resulting EMI. If you cut your planes into tiny regions that have a fraction of the capacitance of the total board you will be greatly increasing the impedance at these frequencies. There is no other way to reduce this impedance. The resonance peaks in impedance can easily be minimized by using low Q capacitors. If you avoid C0G type parts and work with a range of capacitance values you should not see a problem. If you use a tiny power plane you will have a high impedance at the higher frequencies and your signal edge rates and EMI will suffer. The only down side to using multiple capacitor sizes is that you have three line items on the BOM in place of one. On most of my BOMs I already have at least two of these values anyway. I like to keep my BOMs clean, but it seems silly to let this goal drive your decoupling solution.Article: 107690
jidan1@hotmail.com wrote: > Hi, > > I want to design a development board containing Xilinx Spartan-3 > XC3S400. My problem is regarding the number and values of bypass > capacitors that I should use for the power supplies. > I use 3 power supplies: VCCINT=1.2V; VCCAUX=2.5V; VCCO=3.3V. > I took the Spartan-3 Starter Kit Board User Guide > (http://direct.xilinx.com/bvdocs/userguides/ug130.pdf) as a refernce, > but I fond it contradicts XAPP623 - Power Distribution System (PDS) > Design: Using Bypass/Decoupling Capacitors > (http://direct.xilinx.com/bvdocs/appnotes/xapp623.pdf). > > XAPP623 recommends for every power supply: ...snip... These general recommendations are just that, general. To know how to bypass a design first requires that you analyze your design to know how much noise you can accept on the power plane and how large the current transitions will be so you can calcualate a target impedance. It is useful if you know how many outputs will be driving at what rate and what length transmission lines. This can be used to get an idea of the current spikes when your outputs change. These can also be analyzed for frequency content. Then to design your power distribution you should provide capacitance of various values to give the required impedance from about 1 kHz (the high end of where the PSU is effective) to the max frequency determined by your edge rates. I recommend that you use tantalums for the low frequency range and several values of ceramic caps to smooth out the impedance at the mid frequencies. Finally the power plane should be closely spaced to the ground plane to provide good high frequency decoupling. If your design has many fast edge rates you may want to simulate the signals as well as the power decoupling. When you read an app note and the vendor says they won't guarantee that the part will work if you don't follow the app note, does that mean if you follow the app note they *do* guarantee your design???Article: 107691
Marco wrote: > Hi, > > for my Spartan3, being the internal pull-ups only good for non > connected pins, which external pull-ups should I place on my output > pins (that go into output buffer, opto and bjt before reaching the > output pin of the board), 10kOhm, 4.7kOhm? Who told you that the internal pullups are only good for unconnected pins? Are you using these outputs as open collector? If they are driving a BJT, why do you need a pullup at all? Just drive through a series resistor to limit the current. Or you can remove the BJT and drive the opto directly. Spartan3 will drive up to 24 ma, no?Article: 107692
1. Your request wll be served based on the selected priority of the NPI port in mpmc2 core. Data itself are buffered in WR and RD fifos inside the mpmc2, and are independend of address cycle. Then you don't need to wait untill AddrAck will be asserted to write the data to mpmc2. 2. Regardless of the memory width look at the NPI that it can store up to 8 bytes in one shot. You can also select which bytes you want to store by PI_BE signals.Article: 107693
Does anyone know what happened to the easics.com site ? I wanted to use their CRC equation generator. This was working great a couple of months ago, but now I realized I needed equations for a 64 bit wide CRC-32 for ethernet, and the site seems to be missing. Alternatively does anyone have these equations handy, or know of another equation generator ? Thanks, -BruceArticle: 107694
"Luhan" <luhanis@yahoo.com> wrote in message news:1156969891.654210.130580@i3g2000cwc.googlegroups.com... > Glowing perfomance reviews and stock options are what companies give > valued employees instead of raises. Actually, they give the most glowing reviews to the duff emplyees in the hope that a competing department will snatch them away thus solving both the performance problem and making the competing project fail ;-) > > Luhan >Article: 107695
KJ ha scritto:
> "tullio" <tullio.grassi@gmail.com> wrote in message
> news:1156946690.228935.57540@b28g2000cwb.googlegroups.com...
> >I found the problem, it was actually in the signed logic.
> <snip>
> > PS: Xilinx should give a bonus to users for finding their bugs...
> > Plus I could not find good guidlines on how XST interpret signed logic.
>
> Opening a service request to Xilinx would be a good first step. Even now
> that you 'know' the solution, Xilinx doesn't know about it until you let
> them know through some mechanism.
>
> KJ
yes i mentioned to a xilinx support guy.
Anyway I went on to test the compatibility with the Verilog standard of
ISE and ModelSim of other signed syntax. I found another violation of
XST. If you do:
output reg [10:0] UregU;
...
UregU <= $unsigned(-4);
// 11111111100 behav with ModelSim, correct;
// 00000000100 post-PAR (XST violates IEEE P1364-2005/D3)
Article: 107696Hi i am designing a PCI-X 64-bit 66 Mhz Device in FPGA, connected with a SBC (without backplane), the Spec says that IDSEL for the first slot be routed to AD32, IDSEL for the 2nd slot is AD31 and so on, does this mean that i don't need to have an I/O assigned for IDSEL in my FPGA? and refer to AD32 for IDSEL during configuration transaction? BTW, i use Xilinx Spartan 3 fpga. Thanks.Article: 107697
Frithiof Andreas Jensen wrote: > Actually, they give the most glowing reviews to the duff emplyees in > the hope that a competing department will snatch them away thus > solving both the performance problem and making the competing project > fail ;-) Was certainly the case for the black single mom 4.0 standford grad with zero work ethic. All references were glowing.Article: 107698
Hello Bill, >> >>Sure they didn't understand. How could they? That's why HR brought the >>whole stack to my office, less the ones with gross typos in there which >>they knew I wouldn't consider anyway. > > And how do you know that? > Know what? What really bad typos indicate? Pretty clear, if someone affords his or her resume that little attention to detail I assume it'll be the same for a design. Can't use that. -- Regards, Joerg http://www.analogconsultants.comArticle: 107699
"rickman" <gnuarm@gmail.com> wrote in message news:1157033949.114464.11360@p79g2000cwp.googlegroups.com... > Yes, if you eliminate the plane altogether you will not have any > resonances!!! You'll have no resonances but the inductance from the caps you have will put a high upper limit on your impedance, agreed totally. What is a problem is that the board when in a geometrical resonance - not an LC issue but a transmission line issue where the open ends of the plane reflect energy back around a quarter wavelgnth - the upper end of the transmission-line resonance is an extremely high impedance. It's these values that very high frequencies can't have plane-level decoupling benefit them. Different areas of the board will experience different resonances and even different resonant modes based on the geometry. These modes can be predicted to help determine "better" places for caps that *can* still help on large geometry boards. > A resonance is not totally bad. It is only bad if the impedance is > above the level that you can tolerate. The goal is to maintain a low > impedance over a wide range of frequencies. If you make the plane > smaller you may push the resonance higher in frequency, but you also > increase the impedance across the high end of the band. Absolutely. There's less distributed plane capacitance because there's less plane. It's an issue of tradeoffs if your point of interest is a geometry-driven resonance that can't easily be quashed with available caps. > At edge rates of a nanosecond or less, the power plane capacitance is > the only capacitance that is effective to preserve the edge and to > reduce the resulting EMI. If you cut your planes into tiny regions > that have a fraction of the capacitance of the total board you will be > greatly increasing the impedance at these frequencies. There is no > other way to reduce this impedance. One way would be to use more esoteric ground/power distribution layers. While the early distributed capacitance solutions beyond simple thin dielectrics produced 2 mil FR4 layers between power and ground, there are other materials available now (none of which I've had the joy to use) down to 8 mil, some using higher dielectric constant materials to increase the distributed capacitance further. The geometry can stay the same with better capacitance or the geometry can be reduced without compromising the distributed capacitance. It's a cost vs. perceived benefit issue here. > The resonance peaks in impedance can easily be minimized by using low Q > capacitors. If you avoid C0G type parts and work with a range of > capacitance values you should not see a problem. If you use a tiny > power plane you will have a high impedance at the higher frequencies > and your signal edge rates and EMI will suffer. The low-ESR C0G (NPO) style caps aren't necessarily a no-no, it's just that the SRFs have to be closer (hence more cap values) in order to reduce the LC resonance peaks between SRFs brought on by high-Q caps. It's probably best to stick with low ESR but there may be some solutions where the higher SRFs (I'm assuming they're better, not certain) may provide better coverage in a specific high frequency range. > The only down side to using multiple capacitor sizes is that you have > three line items on the BOM in place of one. On most of my BOMs I > already have at least two of these values anyway. I like to keep my > BOMs clean, but it seems silly to let this goal drive your decoupling > solution. I would have thought more than 3 line items would be appropriate but the information I saw might not have realized the benefits from low-Q caps. I really like the possibilities with "good" bypassing design.
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