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Phil Tomson wrote: > Here be dragons and I should perhaps not jump into the dragon pit, but > here's an observation: > > One thing I notice is that people who have had exposure to software > development seem to prefer VHDL As a retired computer programmer of 35+ years who has only recently taught myself Verilog during my retirement (as a hobby), I vastly prefer Verilog to what I've seen of VHDL. On the other hand, most of my programming was "down to the metal" device drivers and realtime embedded systems work, so it was very important for me to be able to easily deal with hardware interfaces and to know exactly what code the compiler (if used at all) generated so I could have strict control over the timing of things. I was overjoyed when the C programming language came along because it maps very well to the computer architectures of most machines and allowed me to use a high level language instead of assembly language even when doing bit-twiddling things such as device drivers (I had used assembly and Pascal up until then). The transition from C to Verilog was almost totally painless once I figured out this new concept of "wires" ;-) because of the similarity between the two languages - at least as far as the low level operators and general design philosophy of the languages go. The thing that bothers me most about abstract computer languages such as COBOL, Lisp, ADA, and I will include VHDL in this category) is that the hardware the design is implemented on is *not* abstract at all - it is composed of bits and bytes and elementary operations an ALU can perform, and so if I care anything at all about performance I like to use a relatively low level language. I think it's rather amusing that whenever I do a new Verilog design, I usually begin by coding the algorithm in the Maple computer language. Maple is a very high level arbitrary precision language that can do symbolic algebra, calculus, differential equations, etc. It may be a surprising choice as a design language for Verilog, but it works quite well because Maple allows me to do pretty much whatever I want without regard to implementation specifics. When I wrote the Verilog implementation of Lenstra's Elliptic Curve Factoring method (ECM), I started by writing a Maple program from the algorithm described in a textbook, and then gradually decomposed each of the higher level operations into simpler operations until I had something that could be implemented easily in Verilog. :-) Ron P.S. My Verilog ECM factoring design for the RSA-704 challenge number is now in its 178'th hour of synthesis (CPU hours), and shows no signs of finishing any time soon. I'm using Xilinx 5.1 Foundation software targeted at a Xilinx XCV2000E FPGA, and running on a Pentium 4 with 1.5 GB of RAM.Article: 103226
shabana_rizvi@yahoo.com schrieb: > Hi! > > I am facing a problem regarding Xilinx CPLD Readback. One of our > engineers left the country who designed the system back in 2000 and is > out of touch now. I have no idea where are the original design files > and the JEDEC files. > > However I do have two or 3 boards which have the working CPLD with the > code I need. I have no experience with a readback feature. Can anyone > help in this regard? I have a Xilinx PC4 cable and the ISE software. > Can I use it to readback the Jedec file from the CPLD? I have read in Yes, if it is not read protected. > the data sheet of XC9572 that it has data protection features. What > will I get if the device is protected? Rubbish or an error messeage. If the protection feature is set, you are lost. And guys, no discussion here on reverse engineering. For such a device, its most probably ways faster and cheaper to redesign the CPLD (using the other system documents etc.) than to reverse engineer the CPLD by probing, etching etc. Regards Falk P.S. Tststs, lost the source files AND the JEDEC. Not quite ISO 9000 compliant. SCNR.Article: 103227
For presynthesized core components create pcores/data/my_peripheral.mdd In this file specify which neltlists to include (must be in pcores/netlist) for example: Files async_fifo.edn clocker.ngc Only EDN and NGC files are supported! The last important thing: include in MPD the following line: OPTION STYLE = MIX to tell the XPS to search for DDB and netlists. Have fun, GuruArticle: 103228
Hi SAVS, Why do you actually need two busses? That is pretty difficult task for a beginner. For a start find out how to add a second bus to your design. Then I suggest you build a peripheral that connects to a single OPB bus (without the Create/Import peripheral wizard). Then serach for a way to connect to bus no 2.Article: 103229
Hi All, Has someone figured out how (or if) it is possible to store netlists used in an ISE design in other directories than the main project directory. I'd like to keep my netlists in a ./source/netlist directory or similar, in the same way I keep my VHDL-files in a ./source/vhdl directory. It makes the ISE projects much cleaner and portable. Regards Johan -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 103230
Hi John, I'll try it, thanks so much. MarcoArticle: 103231
Ben Jones wrote: > Plenty of people would pay good money to have their compile > times dropped from 12 hours to 12 minutes if the technology were available. Wow, I wish I had computers as powerful as yours. I've had a design synthesizing using Xilinx Foundation 5.1 for 178 CPU hours thus far on a Pentium 4 with 1.5 GBs RAM, and it's showing no signs of completing anytime soon. Looks like I need to upgrade to a dual Opteron with many gigs of RAM or something. Unfortunately those are *not* cheap. Can anyone recommend a computer system configuration (h/w and s/w) specifically targeted at FPGA design and synthesis for under $5,000 or so? A Sun Sparc workstation used to be considered top of the line, but I'm not sure that's true anymore. RonArticle: 103232
Johan Bernspång wrote: > Hi All, > > Has someone figured out how (or if) it is possible to store netlists > used in an ISE design in other directories than the main project > directory. I'd like to keep my netlists in a ./source/netlist directory > or similar, in the same way I keep my VHDL-files in a ./source/vhdl > directory. It makes the ISE projects much cleaner and portable. > > Regards > Johan > > > Nevermind, I found out how to do it myself. /Johan -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 103233
Could somebody explain the use of lines AD[1:0] during address phase, for transfers to the I/O space.Article: 103234
On 28 May 2006 06:15:01 -0700, "Derek Simmons" <dereks314@gmail.com> wrote: >Are you trying to initialize for 720 x 576 at 25 Hz frame rate with a >29.5 Mhz clock? Clock : 27Mhz >And, how are you initializing the SD registers? Mode select reg (subadr: 0x01) - val=0x03 // SD only SD mode reg (subadr: 0x40) - val=0xED // PAL B,D... and filters I also set color bars in SD mode reg 3 Timing is set to PAL: Fsc0 to Fsc4 >Are you designing your own core and licensing a commercial core? I've got Xilinx VIODC and trying get test color bar. martaArticle: 103235
Have a look at our Raggedstone1 product. RS1-400 has Spartan-3 XC3S400 on it at GBP=A350 + VAT (if applies). RS232 (stock) and Ethernet interfaces(stock next week) modules are available. Basic details here http://www.enterpoint.co.uk/moelbryn/raggedstone1.html. John AdairArticle: 103236
Hi, I've a question regarding in-system programming of prom devices using the JTAG (ieee 1532) protocol. I implemented a programming algorithm based on the JTAG TAP controller state diagram (i.e. shown in xilinx app. note XAPP503). The implemented command sequences (i.e. for erase, program, read-prom, etc.) are taken from SVF files generated by the XILINX Impact tool and the corresponding BSDL-file based informations. Everything works fine (JTAG chain: with several XILINX FPGAs and corresponding serial & parallel config. proms [xcf04s, xcf16p]). The only problem is performance: its terribly slow. One point for optimization are the wait cycles given in the SVF, for example: 'RUNTEST 80000000 TCK;' means 80 seconds wait time for the erase command (which is very conservative). If I use the Impact tool the same command needs just a few seconds. Thus, there must be a method to observe the device status. In some other Xilinx papers I found the so called 'Instruction Capture Values' as part of the 'Instruction Scan Sequence' but I don't know how to implement the instruction scan sequence. Does a dedicated Instruction-code exist ? I can't find one in the BSDL file. Does anyone know how I can poll the device status (... or how I can get the 'Instruction Capture Values') ? Thank you in advance RalfArticle: 103237
John, your boards are EXCELLENT for the money they cost but this time the OP asked for 'uclinux' ready boards. the requirement for uclinux is 1) xilinx FPGA S2-200 or larger, S3-1000 or larger preferred 2) 4MB RAM 3) some way to load boot image 2MB flash or some media load the image from Raggestone1 does not have a option with 4MB ram ASFAIK so its not an option for the OP AnttiArticle: 103238
there is a command to check if device is erased. not sure if impact uses it to check on erase status possible not I had some trouble also with the XCF08P but it worked at the end. not very fast as I had not correct timing info so partially the timing was figured out by experiments AnttiArticle: 103239
Petter Gustad wrote: > ngdbuild will store the files in its current working directory. If you > run ngdbuild from a shell you can change the current working directory > to source/netlist and then run ngdbuild. > > Petter It was possible to specify the path to the directory in ISE as well. /Johan -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 103240
Johan Bernspång <xjohbex@xfoix.se> writes: > Has someone figured out how (or if) it is possible to store netlists > used in an ISE design in other directories than the main project ngdbuild will store the files in its current working directory. If you run ngdbuild from a shell you can change the current working directory to source/netlist and then run ngdbuild. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 103241
MikeShepherd564@btinternet.com wrote: > >>That, of course, is called "time sharing", and is what we used 30 years > >>ago, before PCs arrived. Back to the future... > > > There's no point pretending that processing power and RAM are still > expensive. They're cheap. They're very cheap. That's why we now > have it locally. Do you want a server to render your graphics images, > too? Apparently rendering graphics is still done by the X11 server on Linux. X11 was a cool thing 20 years ago when graphics workstations cost as much as a Ferrari. I don't know why this dinosaure (X11) still exists today.Article: 103242
http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/index.htm Looking at Virtex-5 capabilities at Xilinx web site I didn't find Rocket I/O. Is it gone? Why? Any hope for re-introduction in "Virtex-5 GX" ?Article: 103243
To be honest. Linux support for these boards is work in progress. There is a 32MByte Flash memory to host the boot image. There is a compact flash interface on the board. Jiri Gaisler is AFAIK working on a way to boot linux from a compact flash. Additionally there is a DDR RAM interface that should give access to memory sizes of up to 1 GByte. So the hardware support for very capable linux systems is ready on the board. The software support is being worked on. Stefan.Article: 103244
On a sunny day (29 May 2006 06:45:33 -0700) it happened wv9557@yahoo.com wrote in <1148910332.991842.13020@u72g2000cwu.googlegroups.com>: >Apparently rendering graphics is still done by the X11 server on Linux. >X11 was a cool thing 20 years ago when graphics workstations cost as >much as a Ferrari. I don't know why this dinosaure (X11) still exists >today. X11 is a fine system, Unix is about networking. Maybe you think simple and want to go back to MSDOS. Nobody is stopping you.Article: 103245
Hi,
I'm trying to add an IP(FFT), generated by Coregen, to an EDK project.
I have created a new custom IP in EDK and added the vhdl code of FFT into
user_logic.vhd file, and imported it to the EDK project, but I got three
errors:
ERROR:NgdBuild:604 - logical block 'fft_ip_0/fft_ip_0/USER_LOGIC_I/fft/U3'
with
type 'fft128' could not be resolved. A pin name misspelling can cause
this, a missing edif or ngc file, or the misspelling of a type name.
Symbol 'fft128' is not supported in target 'virtex2p'.
ERROR:NgdBuild:455 - logical net 'plb_bram_if_cntlr_1_port_BRAM_Clk' has
multiple driver(s):
pin PAD on block
plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_port_BRAM_Clk
with type PAD,
pin O on block dcm_0/dcm_0/CLK0_BUFG_INST with type BUFG
ERROR:NgdBuild:924 - input pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' is
driving non-buffer primitives:
pin C on block reset_block/reset_block/core_cnt_en with type FD,
pin C on block reset_block/reset_block/Bus_Struct_Reset_0 with type
FD,
pin C on block reset_block/reset_block/Rstc405resetchip with type
FD,
pin C on block reset_block/reset_block/Peripheral_Reset_0 with type
FD,
pin C on block reset_block/reset_block/Rstc405resetsys with type FD,
pin C on block reset_block/reset_block/Core_Reset_Req_d3 with type
FD,
pin C on block reset_block/reset_block/CORE_RESET/q_int_0 with type
FDRE,
pin C on block reset_block/reset_block/CORE_RESET/q_int_1 with type
FDRE,
pin C on block reset_block/reset_block/CORE_RESET/q_int_2 with type
FDRE,
pin C on block reset_block/reset_block/CORE_RESET/q_int_3 with type
FDRE,
pin C on block reset_block/reset_block/Core_Reset_Req_d2 with type
FD,
pin C on block reset_block/reset_block/EXT_LPF/lpf_exr with type
FDSE,
pin C on block reset_block/reset_block/EXT_LPF/lpf_asr with type
FDSE,
pin
C on block reset_block/reset_block/EXT_LPF/asr_lpf_1 with type FD,
pin C on block reset_block/reset_block/EXT_LPF/exr_lpf_1 with type
FD,
pin C on block reset_block/reset_block/EXT_LPF/asr_lpf_2 with type
FD,
pin C on block reset_block/reset_block/EXT_LPF/exr_lpf_2 with type
FD,
pin C on block reset_block/reset_block/EXT_LPF/asr_lpf_3 with type
FD,
pin C on block reset_block/reset_block/EXT_LPF/exr_lpf_3 with type
FD,
pin C on block reset_block/reset_block/EXT_LPF/exr_lpf_0 with type
FD
NGDBUILD Design Results Summary:
Number of errors: 3
Number of warnings: 77
I don't know what exactly these errors mean. Can anyone help to resolve
these problems?
Article: 103246sure I know, but it isnt ready yet. leon can run linux and it can run on the lattice board, *when* it is ported and tested. AnttiArticle: 103247
the "T" prefix is for the parts with rocketio but all those parts are coming into town sometimes in 2007 so there is no info on them yet AnttiArticle: 103248
I'm using different approach and it works. Install first 71 in the c:\xilinx folder. Then manually rename it to, let say xilinx_71, and install 81 in the c:\xilinx folder. Whenever I need another ver i just rename them manually.Article: 103249
Hi, you need to add the search path to the edif in ISE so that it can find the netlist. Andi
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Compare FPGA features and resources
Threads starting:
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