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Borge wrote: > Is there a dedicated power-on reset function in Verilog? What I want to > achieve is that my own reset functionality will be executed when the > FPGA (Xilinx Spartan3/400) undergoes power-on reset. > > Maybe power-on reset is available as a Xilix core, but I haven't been > able to find anything like that. > > I was hoping to avoid external POR circuitry. > > > Thanks, > > Borge > > P.S. Cross-posted to comp.lang.verilog > Xilinx comes up in a programmable known state. You can instantiate the ROC primitive to make your design take advantage of it (unless explicitly told otherwise, all the flip-flops come up cleared).Article: 111876
kanglc@gmail.com wrote: > Thanks Ray. > > I tried that, generating 2 seperate edf files for the top and > lower-level module. And I put // synthesis syn_black_box on the stub > module in the modified top-level design. But when I put both edf files > into ise, it complains cannot have 2 source files. I must have missed > out something, probable due to my limited Verilog. > > Just to confirm. Is it true that, no matter it's hdl or edf top-level, > we can have hierarchical structure in the lower levels described in > either hdl or edf, right? I mean in ISE. > You are close. In ISE you only specify the top level design's edif. The rest of the edifs have to be in the directory pointed to by the path property (I think that is under the translate properties). Make sure the edifs have the same name as the name of the black box and are in that directory. If you do that, then ISE will stitch them into the design.Article: 111877
I am new to FPGA design so I'm sure this is a very basic question.
Is there a rule of thumb when using these constraints? For example
If I have a 50 mhz clock with a 20 ns period is there a general rule as
to what my pad to setup and clock to pad should be in order to keep
things in sync with the system clock?
Any help would be appreciated.
Article: 111878
I am new to FPGA design so I'm sure this is a very basic question.
Is there a rule of thumb when using these constraints? For example
If I have a 50 mhz clock with a 20 ns period is there a general rule as
to what my pad to setup and clock to pad should be in order to keep
things in sync with the system clock?
Any help would be appreciated.
Article: 111879Does anyone know where to find the XC9500 Jtag programming instructions? I have one for the XCR3000 (cool runner) and looking for the equivalence for XC9500 The XCR3000 jtag spec has detail info down to the TMS/TDI/TDO level. I am sure there is one for XC9500 somewhere. I can't even find the XCR3000 on xilinx's web anymore.Article: 111880
linnix <me@linnix.info-for.us> wrote: > Does anyone know where to find the XC9500 Jtag programming > instructions? I have one for the XCR3000 (cool runner) and looking for > the equivalence for XC9500 The XCR3000 jtag spec has detail info down > to the TMS/TDI/TDO level. I am sure there is one for XC9500 somewhere. > I can't even find the XCR3000 on xilinx's web anymore. Did you look in the BDSL files in the webpack xc9500xl/data/ directory? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 111881
"pete o." <portisi@comcast.net> wrote in message news:1163343998.901642.121850@m7g2000cwm.googlegroups.com... >I am new to FPGA design so I'm sure this is a very basic question. > Is there a rule of thumb when using these constraints? Yes, the rule of thumb is to thumb through the data sheets for the device(s) to which your FPGA will be communicating. If a device requires a 5 ns setup time of one signal relative to some other signal than the clock to output delay of those two signals coming out of your FPGA must meet that requirement. Repeat this for every signal that enters or exits your FPGA design. Most of these constraints can be directly coded as constraints to your FPGA synthesis tool Ones that can not must still be guaranteed to be met by your design and you must verify that they are. As a general guideline setup times of an external device will translate into clock to output delay requirement for the FPGA. Clock to output delays of an external device will translate into input setup time requirements for the FPGA. Both of these will translate in roughly the following manner: Tsu (requirement) = Clock Period - Tco (specification) - Clock Skew - PCB prop delays differences > For example > If I have a 50 mhz clock with a 20 ns period is there a general rule as > to what my pad to setup and clock to pad should be in order to keep > things in sync with the system clock? The actual clock cycle is not relevant to how you go about performing the task. KJArticle: 111882
When the Nios reset vector points into Altera-provided CFI flash SOPC
builder automayically adds following lines to the system ptf file:
WIZARD_SCRIPT_ARGUMENTS
{
MAKE
{
MACRO
{
FLASH_FLASHTARGET_ALT_SIM_PREFIX =
"$(FLASH_FLASHTARGET_TMP1:0=)";
FLASH_FLASHTARGET_TMP1 =
"$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
}
MASTER cpu
{
MACRO
{
BOOT_COPIER = "boot_loader_cfi.srec";
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x0";
}
}
TARGET delete_placeholder_warning
{
flash
{
Command1 = "rm -f
$(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET flashfiles
{
flash
{
Command1 = "@echo Post-processing to create $(notdir
$@)";
Command2 = "elf2flash --input=$(ELF) --flash=
--boot=$(shell
$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir
$(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)
--outfile=$(FLASH_FLASHTARGET_ALT_SIM_PREFIX)flash.flash
--sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x1FFFFFF
--reset=$(CPU_RESET_ADDRESS) ";
Dependency = "$(ELF)";
Target_File =
"$(FLASH_FLASHTARGET_ALT_SIM_PREFIX)flash.flash";
}
}
TARGET sim
{
flash
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir
$(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled
for the target SOPC Builder system. Skipping creation of hardware
simulation model contents and simulation symbol files. \\(Note: This
does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
}
Later on when Nios2 IDE discovers that the text section has to be
copied/relocated it adds the required commands to the makefile. That's
nice because this way we never forget to run elf2flash utility at the
end of the make process and at the same time could take full advantage
from other aspects of automatic makefile generation in Nios2 IDE
(pretty much the only useful feature of the whole thing. A big fan of
Eclipse I am not).
Now the question is: how do I get the same functionality for custom
non-volatile memory component?
I looked at the file class.ptf in the
\kits\nios2_51\components\altera_avalon_cfi_flash directory and didn't
find anything resembling the required lines. Do we see a built-in SOPC
builder wizardry at action once again treating custom components as 3rd
class citizens?
Article: 111883This used to work! I've had it put away for a couple of weeks, and now when I plug in the Platform cable it tries to reinstall the driver and when it gets to the second stage (after installing the firmware loader), Windows says that a service installation section in the INF file was invalid. Anyone ever seen this before?! How do I fix it?Article: 111884
I did try to reinstall the Cygwin, but when I launch the EDK shell it hangs at the Add registry entries for C:\Xilinx\EDK\cywin\ My notebook has only 512 MB Ram, is it the primary problem of can not run the EDK? Waiting for your response. Thang NguyenArticle: 111885
Thanks Ray, but http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0373_357.html says the ROC is used for VHDL simulation, not for Verilog or synthesis. I was perhaps a bit unclear. The power-on-reset is something I will need for synthesis. I wonder if the Xilinx part has a power-on detection circuit with a logical output that I could OR with my (active high) reset input. I don't mind the gates resetting to '0', but I'm using some random number generators that have constant, nonzero seeds set up in my code. Regards, B=F8rge Ray Andraka wrote > Xilinx comes up in a programmable known state. You can instantiate the > ROC primitive to make your design take advantage of it (unless > explicitly told otherwise, all the flip-flops come up cleared).Article: 111886
Ray Andraka wrote: > Xilinx comes up in a programmable known state. You can instantiate the > ROC primitive to make your design take advantage of it (unless > explicitly told otherwise, all the flip-flops come up cleared). Actually, any FDP, FDPE, FDS, or FDSE primitives come up set unless explicitly told otherwise, at least in the Spartan-N(E) families I've used. The FD, FDR, FDRS, FDC, FDCP, FDE, FDRE, FDRSE, FDCE, and FDCPE primitives all come up cleared as expected unless explicitly told otherwise. All BlockRAM and CLB SelectRAM (including SRLs) come up cleared by default but can be overridden as well.Article: 111887
>"Borge" <borge.strand@gmail.com> wrote in message >news:1163352825.751658.268890@k70g2000cwa.googlegroups.com... >Thanks Ray, > >but http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0373_357.html >says the ROC is used for VHDL simulation, not for Verilog or synthesis. >I was perhaps a bit unclear. The power-on-reset is something I will >need for synthesis. I wonder if the Xilinx part has a power-on >detection circuit with a logical output that I could OR with my (active >high) reset input. >I don't mind the gates resetting to '0', but I'm using some random >number generators that have constant, nonzero seeds set up in my code. >Regards, >Børge +++++++++++++++++++++++++++++++++++++++++++++++ As all the FPGA's FF's are reset to zero on powerup, why not create a counter that inhibits itself after reaching a suitable a preset value when clocked with one of your system clocks? Use the terminal count decode as your POR (adjusting polarity as appropriate). SlurpArticle: 111888
Good idea! Or perhaps even better, have a register with no reset value be counted up towards a preset and let the local reset be active between preset one and preset two. After reaching preset two there's no more counting. If we can KNOW that the register is reset to either 0xFF or 0x00, and not the preset values, this should generate a local reset pulse. So, for example, a 4-bit register could count up from 0 (or F) to 2, activate reset, count to 4 and then deactivate reset and stop counting. I love your abbreviations, but how would you declare the 4-bit register in practical, synthesizable Verilog? Thanks, Borge Slurp skrev:> As all the FPGA's FF's are reset to zero on powerup, why not create a > counter that inhibits itself after reaching a suitable a preset value when > clocked with one of your system clocks? > Use the terminal count decode as your POR (adjusting polarity as > appropriate). > > > SlurpArticle: 111889
Uwe Bonnes wrote: > linnix <me@linnix.info-for.us> wrote: > > Does anyone know where to find the XC9500 Jtag programming > > instructions? I have one for the XCR3000 (cool runner) and looking for > > the equivalence for XC9500 The XCR3000 jtag spec has detail info down > > to the TMS/TDI/TDO level. I am sure there is one for XC9500 somewhere. > > I can't even find the XCR3000 on xilinx's web anymore. > > Did you look in the BDSL files in the webpack xc9500xl/data/ directory? That would give me the boundary scan registers. What I am looking for is the spec of Flash programming. For example, for XCR3032, I have to shift in 304 data bits and 9 address bits to access the Flash. Would it be the same for XC9536/9572, perhaps a different number of bits? > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 111890
On 2006-11-12, firebird <helluvanengineer@gmail.com> wrote: > However, what is a good > way to deal with the serial clock. The FPGA will act as a master > interfacing with a slave A/D converter that supports SPI interface. > Thus, the FPGA will need to generate the SPI clock. The clock doesn't have to have any particular duty cycle or frequency (other than below the maximum for the slave). It only has to be exist while you're clocking data around. > contain a simple processor implementation. I think the processor clock > can be used to derive the SPI clock, If your AD is slow, you'd probably save resources by bit-banging the SPI from your processor. The memory for the code is probably less expensive in your design than area in the FPGA for a real SPI master. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 111891
ian.peikon@gmail.com wrote: > Hi, > > I've been working on an FPGA project for a month or so now and I have > finally finished the code. Before I began I calculated the amount of > BRAM and Distributed Ram that I had available and designed the code > accordingly. However after compilation I get the following results: > Number of Slices: 43734 out of 1200 3644% (*) > Number of Slice Flip Flops: 19047 out of 2400 793% (*) > Number of 4 input LUTs: 27654 out of 2400 1152% (*) > Number of IOs: 58 > Number of bonded IOBs: 53 out of 96 55% > Number of BRAMs: 528 out of 10 5280% (*) > Number of GCLKs: 2 out of 4 50% > > I don't really see how any of this is possible. I instantiated 5 > BRAM's. Where does it come up with 528? Additionally where do the > flipflops, slices, and LUT's come from? My code is only ~500 lines, I > don't even know how I coded for this much logic?!!! > > PLEASE HELP!! I think that you must have a basic misunderstanding with your code. I can only give you the obvious advice : - Think hardware. Every signal or process (or whatever) you write must correspond to a basic 'physical' structure you have in mind (or on paper). - Try to synthetize and check the smallest possible part and try to isolate the ofending code. - If everything else fails, put your code on a webpage, and some of the experts here may spot the problem for you. Best regards Josep DuranArticle: 111892
KJ wrote: >(......) > > As a general guideline setup times of an external device will translate into > clock to output delay requirement for the FPGA. Clock to output delays of > an external device will translate into input setup time requirements for the > FPGA. Both of these will translate in roughly the following manner: > > Tsu (requirement) = Clock Period - Tco (specification) - Clock Skew - PCB > prop delays differences > > > For example > > If I have a 50 mhz clock with a 20 ns period is there a general rule as > > to what my pad to setup and clock to pad should be in order to keep > > things in sync with the system clock? > The actual clock cycle is not relevant to how you go about performing the > task. > > KJ On a (hopefully) related issue, how do you handle the Tco jitter between different IO pads. Lets say, the FPGA outputs clock and data to an external chip with some Tsu requirement. Lets say, the Tco calculated for all outputs is in the range 10-12 ns, to my understanding, this is a maximum time. Is it safe to assume that any deviation from this timing will affect all outputs the same ? Is it possible that the clock signal goes out in a 20% (or 80%) of the calculated maximum Tco while some other output needs the full 100% of the maximum calculated Tco ? I would tend to think it is not possible, but I must account for some margin here (?) Am I missing some other timing constraint ? Thank you Josep DuranArticle: 111893
Hi, I have the book written by Uwe Meyer "Digital Signal Processing with FPGAs", 1st edition. Now, I want to learn the example in this book. After I install the Maxplus 2 9.23 on my Windows XP PC and obtained the license.dat (I even modified the environment variable from control panel) from altera.com, I cannot compile the examples. What's wrong with it? How about the new web edition software? Can it run the examples in the book? Thanks in advanceArticle: 111894
Hi, It might be a naive question, however, I just want to make sure. Is Xilinx new USB JTAG backward-compatible with old parallel port JTAG development boards? I'm a bit suspicious as some of the newer Xilinx boards say explicitly that the board is compatible with the USB JTAG. I know a JTAG is a JTAG regardless of whether it's USB or parallel port based. Just want to make sure. Please I would be grateful if anybody can clear this out for me as I need to order some stuff. Thanks in advance, Cheers,Article: 111895
linnix <me@linnix.info-for.us> wrote:
> Uwe Bonnes wrote:
> > linnix <me@linnix.info-for.us> wrote:
> > > Does anyone know where to find the XC9500 Jtag programming
> > > instructions? I have one for the XCR3000 (cool runner) and looking for
> > > the equivalence for XC9500 The XCR3000 jtag spec has detail info down
> > > to the TMS/TDI/TDO level. I am sure there is one for XC9500 somewhere.
> > > I can't even find the XCR3000 on xilinx's web anymore.
> >
> > Did you look in the BDSL files in the webpack xc9500xl/data/ directory?
> That would give me the boundary scan registers. What I am looking for
> is the spec of Flash programming. For example, for XCR3032, I have to
> shift in 304 data bits and 9 address bits to access the Flash. Would
> it be the same for XC9536/9572, perhaps a different number of bits?
for exampl in xc9500xl/data/xc9572xl_pc44.bsd you find
attribute INSTRUCTION_OPCODE of xc9572xl_pc44 : entity is
"BYPASS ( 11111111)," &
"CLAMP ( 11111010)," &
"ISPEX ( 11110000)," &
"EXTEST ( 00000000),"&
"FBULK ( 11101101),"&
"FBLANK ( 11100101),"&
"FERASE ( 11101100),"&
"FPGM ( 11101010)," &
"FPGMI ( 11101011)," &
"FVFY ( 11101110)," &
"FVFYI ( 11101111)," &
"HIGHZ ( 11111100),"&
"IDCODE ( 11111110),"&
"INTEST ( 00000010),"&
"ISPEN ( 11101000)," &
"ISPENC ( 11101001)," &
"SAMPLE ( 00000001)," &
"USERCODE ( 11111101)";
In the last version of naxjp with source available, you can find how these
commands are used to programm the device. E.g. in naxjp-079/alg95xl.cpp
for erasing the device you find:
bool DeviceXC95XL::Erase(){
csd->SetLength(Num,18);
csd->SetSMASK(Num,0x3ffff);
if(!stricmp(DeviceCmd,"oerase")){
PrintMessage("erase");
csi->SetTDI(Num,0xec,8,0);
csi->OutputSIR(false);
csd->SetTDI(Num,0xaa55 << 2 | 3,18,0);
csd->OutputSDR(false,400000,IgnoreLevel);
}
PrintMessage("bulk erase");
csi->SetTDI(Num,0xed,8,0);
csi->OutputSIR(false);
csd->SetTDI(Num,0x03ffff,18,0);
csd->OutputSDR(false,400000,IgnoreLevel);
csd->SetTDI(Num,0x00001,18,0);
csd->SetTDO(Num,0x00001,18,0);
csd->SetMASK(Num,0x00003,18,0);
return csd->OutputSDR(true,0,IgnoreLevel);
The comments are however in japanese, Nahitafu has no big knowledge of
english and further versions of naxjp where no longer available in source.
Probably Nahitafu signed some NDAs.
I wish the programming instruction would be available somewhere and would be
folded in some program like xc3sprog.
Cheers
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 111896FL, > Now, I want to learn the example in this book. After I install the > Maxplus 2 9.23 on my Windows XP PC and obtained the license.dat Please do yourself a favour and use Quartus II Web Edition. MaxPlus was made obsolete about two years ago. There's only one reason to use MaxPlus, and that's if you use the old Flex10K or Flex10KA families - all the other ones (inclding the Flex10KE series) are supported in Quartus II Web edition. The schematic editor is still there, the simulator is (sort of) still there, and VHDL and Verilog are way better supported than in MaxPlus. Best regards, BenArticle: 111897
> If your AD is slow, you'd probably save resources by bit-banging the SPI > from your processor. The memory for the code is probably less expensive > in your design than area in the FPGA for a real SPI master. Can you elaborate on "bit-banging" - that is a completely unfamiliar term. Thanks!Article: 111898
John_H wrote: > Ray Andraka wrote: > >> Xilinx comes up in a programmable known state. You can instantiate >> the ROC primitive to make your design take advantage of it (unless >> explicitly told otherwise, all the flip-flops come up cleared). > > > Actually, any FDP, FDPE, FDS, or FDSE primitives come up set unless > explicitly told otherwise, at least in the Spartan-N(E) families I've > used. The FD, FDR, FDRS, FDC, FDCP, FDE, FDRE, FDRSE, FDCE, and FDCPE > primitives all come up cleared as expected unless explicitly told > otherwise. > > All BlockRAM and CLB SelectRAM (including SRLs) come up cleared by > default but can be overridden as well. Yes, that is true if you instantiate the primitives. The synthesis, however, does not force the use of those primitives necessarily. If you want it to come up in a known state then you need to use the ROC. Borge, yes and no on the ROC. It is there mainly for the benefit of simulation, however if you instantiate the ROC component as a black box, synthesis leaves it in, and the Xilinx translate takes the black boxes out, leaving you with flip-flops that are explicitly forced to a specific starting state.Article: 111899
firebird wrote: > Can you elaborate on "bit-banging" - that is a completely unfamiliar > term. "Bit-banging" or "bit-bashing" is generally used to describe the technique of 'emulating' a communications protocol in software rather than employing a purpose-built peripheral normally used for the task. Typically the I/O would occur on MCU GPIO ports. Aside from SPI, another common candidate is serial (UART) comms. Obviously the wire speed must be sufficiently slow to enable software to keep up with the protocol requirements. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
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