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Dolphin wrote: > Hello, > > I have a system with limited memory resources which contains a Nios2 > processor. > An EPCS device is linked to this processor. I don't want to use the HAL > drivers to access this device because when I use the HAL drivers I will > need lots of memory and I can no longer use the small C library. It may be easier if you use Marco Groeneveld's EPCS Virtual Memory controller. It attaches the EPCS serial Flash to the Avalon bus as a parallel device you can just read and write. You can find it on: http://www.fpga.nl Look in the section IP Cores. BTW: The Firefly is a neat board as well. Best regards, Ben Twijnstra Altera Tech Support SascoHolz NederlandArticle: 111776
I searched for IO_x_x_x_x in all files in my project folder and found
this:
INFO:NgdBuild:889 - Pad net 'embedded_proc0/iobuf_4/IO' is not
connected to an
external port in this design. A new port 'IO_x_x_x_x' has been
added and is
connected to this signal.
Now this is annoying; the tools seem to be binding some unknown IO
buffer to a port I happen to need. I searched all files for iobuf_12
and found the following in embedded_proc.vhd (automatically generated
by the EDK):
iobuf_12 : IOBUF
port map (
I => fpga_0_PushButtons_5Bit_GPIO_IO_O(4),
IO => fpga_0_PushButtons_5Bit_GPIO_IO_pin(4),
O => fpga_0_PushButtons_5Bit_GPIO_IO_I(4),
T => fpga_0_PushButtons_5Bit_GPIO_IO_T(4)
);
Ah-ha! This is one of the ports I disconnected so I could use them to
debug another part of the design:
embedded_proc embedded_proc0(
.sys_clk_pin(system_clock_i),
.sys_rst_pin(sys_rst_inv_i),
....
.fpga_0_PushButtons_5Bit_GPIO_IO_pin(),
.fpga_0_DIPSWs_4Bit_GPIO_IO_pin(),
.fpga_0_LEDs_4Bit_GPIO_IO_pin(),
...
This means that Xilinx tools do several things behind my back:
1) They move unused pins burried deep into the design to the top
level
2) They may assign those pins to IOBs that are already in use
3) They give those pins and their buffers meaningless names
(IO_x_x_x_x and iobuf_12)
I deleted those pins from XPS to get around this, but am still getting
the banking error.
Todd Fleming wrote:
> Here's another clue. I checked the .pad file after I built (without a
> loc constraint on LLC_CLOCK) and noticed that B16 is occupied by signal
> "IO_x_x_x_x"; there are similarly-named signals throughout the .pad
> file, each with a different number of "_x"'s. None of my signals have
> names that are anything like this; where are these coming from?
>
> Todd
Article: 111777Thanks for responding, John_H. I found the cause of the IO_x_x_... pins and eliminated them. Now the pad file shows that the only pins in bank 0 are the three IO pins I mentioned. Oddly, it says that the problem pin is LVTTL even though my UCF file sets it to LVCMOS25. It seems to be ignoring the IOSTANDARD constraint. Todd John_H wrote: > Since SSTL2 is a 2.5V standard as is LVCMOS25, you possibly have a different > I/O in that bank. Take a look at the pad report that shows which I/O > standards are getting assigned to which banks. You'll probably find a third > I/O standard in that bunch. Either that or there's a problem with the VREF > inputs (which should also be noted in the pad report).Article: 111778
The only time I've seen the IOSTANDARD from the .ucf not applied is when it's misapplied. Have you double-checked the spelling of the net where you applied the standard in the .ucf with the pad report's pad name? "Todd Fleming" <tbfleming@gmail.com> wrote in message news:1163113660.204145.231640@h48g2000cwc.googlegroups.com... > Thanks for responding, John_H. > > I found the cause of the IO_x_x_... pins and eliminated them. Now the > pad file shows that the only pins in bank 0 are the three IO pins I > mentioned. Oddly, it says that the problem pin is LVTTL even though my > UCF file sets it to LVCMOS25. It seems to be ignoring the IOSTANDARD > constraint. > > Todd > > John_H wrote: >> Since SSTL2 is a 2.5V standard as is LVCMOS25, you possibly have a >> different >> I/O in that bank. Take a look at the pad report that shows which I/O >> standards are getting assigned to which banks. You'll probably find a >> third >> I/O standard in that bunch. Either that or there's a problem with the >> VREF >> inputs (which should also be noted in the pad report). >Article: 111779
oopere wrote: > Sure, there may be problems in my design. However, the main point of my > post is that the circuit behaviour is different in the following cases: > - State a). Original design > - State b). Originial design + output pin added + compiled + output pin > removed + compiled But you're missing the point entirely. If your design doesn't meeting timing, and/or your timing constraints are invalid/incorrect, then "all bets are off" as they say. And yes, as far as I understand, some PAR algorithms *are* non-deterministic, so two builds may result in a different bit-stream. Indeed, incremental building will almost *definitely* produce different results from a clean compile from scratch. My point is, under normal conditions and a 'flawless' design, Quartus may well produce different output on different builds - but it will always behave correctly. If the design is 'marginal' or just plain incorrect, then this process may yield working output *some* of the time, and non-working output others. In your case, adding a pin causes the design to 'work'. Removing it and you've lucky enough that Quartus still places in a manner that allows it to work. Having said that, I wonder what your sample space is? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111780
Mark McDougall wrote: > And yes, as far as I understand, some PAR algorithms *are* > non-deterministic, so two builds may result in a different bit-stream. OK, that'll teach me to post before reading the rest of the thread! Apparently Quartus *is* completely deterministic. > Indeed, incremental building will almost *definitely* produce different > results from a clean compile from scratch. I still maintain however that this *is* true. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111781
The names matched. I renamed the signal in both the Verilog file and the UCF file and it built. I then renamed it back to the original name and it failed as before. I've now tried several names: camera_llc_i: failed hungus_i: OK camera_clk_i: failed capture_clk_i: OK I see a pattern: it doesn't like the signal name to begin with camera_. I then realized I have this line: NET "camera_*" IOSTANDARD = LVTTL; Oops; I didn't notice the LVCMOS25 pin when I crafted that. If anyone from Xilinx is reading this: Please, please, please make ISE generate an error message when wildcard constraints conflict with other constraints; this would have saved me a lot of time. Also, please make ISE/XPS mixed flows stop automatically promoting unconnected non-top-level pins to the top level (see my earlier posts in this thread). If that isn't possible, at least replace worthless names such as "IO_x_x_x_x" and "iobuf_12" with meaningful ones. I'm using ISE & XPS 8.2i. Todd John_H wrote: > The only time I've seen the IOSTANDARD from the .ucf not applied is when > it's misapplied. Have you double-checked the spelling of the net where you > applied the standard in the .ucf with the pad report's pad name?Article: 111782
langwadt@ieee.org wrote: >Jon Elson wrote: > > >>Hello, all, >> >>Does anyone know where I can get just a few (5 - 10) Xilinx >>XCS30-3TQ144C chips? Anybody who has them wants to sell me >>a minimum of a hundred or more. I just need a few to make >>repairs on equipment in the field. I just got a board back >>from a customer who had a lightning strike, and I had to salvage >>a chip off a test module to get his unit repaired. >> >>If anyone has a few of these chips laying around, I'd be glad to >>pay the going rate for them, too! I can probably use other speed >>ranges or temp ranges as well. I'm in the US, but that shouldn't >>make much difference, I seem to be buying my Xilinx chips from >>Australia these days! >> >>Thanks much in advance. >> >>Jon >> >> > > >item 150055912098 on ebay?, XCS30-3TQ144C, buy now price US $6.85 > > Thanks very much for spotting this! I've been checking eBay every once in a while for a year, and NEVER saw any Spartan parts. Now, there are several. I'm checking with the seller to see if I can get less quantity than the whole lot of 220 pieces. JonArticle: 111783
Hey Mordehay, Thanks a lot!!! Warm regards, Sandip me_2003@walla.co.il wrote: > I've attached a tutorial that I found in the web > I hope it will help you to proceed. > goodluck, Mordehay. > > http://vlsi1.engr.utk.edu/~msharafa/HowToBurnSerialProm.htm > > > > > Sandip wrote: > > Hi Mordehay, > > I have done this a few times, but was unsucessful with the IMPACT tool > > to download into the board. If there is some elaboration on what > > options to choose and few steps would be great. > > > > Thanks and regards, > > Sandip > > > > me_2003@walla.co.il wrote: > > > Use the IMPACT tool in the ISE. > > > after implementing your design just open the IMPACT tool and follow the > > > instructions > > > it should be pretty simple. > > > Mordehay. > > > > > > Sandip wrote: > > > > Hi, > > > > > > > > I am using ML403 board with Virtex-4. I need to generate and download a > > > > PROM file into the PROM and then use it after I switch it OFF and then > > > > again ON. > > > > Can anyone please help me out in doing so?? > > > > > > > > Thanks and regards, > > > > SandipArticle: 111784
Hi, Is there a way to use partition for top-level edif flow? (Synthesis: Synplify_premier) Since there is only one edif design file, how do we set partition for lower level module? Thanks!Article: 111785
Ray Andraka wrote: > shaz.pecobian@gmail.com wrote: > > hi > > im doing a project to implement single and double precision floating > > point arithemetic units on Altera FPGA.Can someone please arrange me or > > tell me any link from whr i can find the VHDL coding for the same.im a > > beginner in the VHDL field. > > > > What do you mean by arithmetic units? Normally in FPGAs, we implement > only the function that is needed for that part of the circuit, not a > complete arithmetic unit like you'd find in a microprocessor. Most > likely, you won't find something that exactly meets your needs and > you'll have to roll your own. You also said nothing about performance > or size requirements. Floating point isn't all that difficult to > implement, just costly in terms of amount of logic, especially for the > adds and subtracts. I suggest you pick up a book such as Israel Koren's > Computer Arithmetic that discusses floating point number systems as a > starting point so that you understand the hardware that is necessary for > floating point operations. hi im going to develop adders,multipliers,dividers as they r somewht tough but added advantage of high precision etc.and thenplanning to make an fir filter based on them......i have got the idea from a no. of research papers who have implemented thm...i am new to this field and i have generated some code for this also(for swapping and alignment before actual addition) but getting constraints of i/p o/p pins etc.so due to being new ,i cant generate some code that is efficient enough requiring less pins or memory..Article: 111786
Find the utility jed2eqn. Google will turn up some sources. This will give you equations that reasonably easy to modify over to VHDL. John Adair Enterpoint Ltd. - Home of Tarfessock1. The Cardbus FPGA Development Board. lingamaneni.naveen@gmail.com wrote: > I have a JED file for an old PAL device and I have to put this design > in a FPGA. > Is there a tool that can read the JED file and translate it to any > usable language (VHDL prefered)...Article: 111787
Hi!
I'm trying to implement an add-compare-select (ACS) unit in a Spartan3
but I am not satisfied with the speed. The code looks like this:
...
type sum_array is array(0 to 7) of signed(13 downto 0);
signal state_reg : sum_array;
...
process(clk, rst) is
variable sum1, sum2, sum3, sum4 : sum_array;
begin
if rst = '1' then
....
elsif clk'event and clk = '1' then
...
sum1(0) := state_reg(a1) + gamma(a2);
sum2(0) := state_reg(b1) + gamma(b2);
sum3(0) := state_reg(c1) + gamma(c2);
sum4(0) := state_reg(d1) + gamma(d2);
state_reg(0) <= MIN4(sum1(0), sum2(0), sum3(0), sum4(0));
...
end if; -- rst,clk
end process;
where a1, a2, ..., d2 are some constants. The problem with this code is
that we access the newly calculated state_reg in the very next clock
cycle (the constants can be for instance zero!). Hence pipelining is not
possible. The Minimum search (MIN4) is done by doing 6 subtractions in
parallel to avoid a two stage minimum search tree.
I would like to boost the clock frequency of this architecture. Is there
a way to further improve the description in VHDL? Or is it possible to
do some hand optimisations?
Thanks in advance,
Matthias
Article: 111788Jon Elson <jmelson@artsci.wustl.edu> wrote: ... > I'm checking with the seller to see if I can get less quantity than the > whole > lot of 220 pieces. Buy all and sell the rest on EBAY ;-) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 111789
Mike Treseler wrote: > > Sorry, I didn't read the whole question. > Synthesis will convert tri-buff inferences to muxes. > How these muxes look like? Is there any scheme they are arranged? I can imagine it, but I need to understand how many resources that will require. Do you suggest to try to implement it and then look at the rtl view? Can I foresee some structure? Thanks a lot Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 111790
Mark McDougall wrote: > oopere wrote: > > > Sure, there may be problems in my design. However, the main point of my > > post is that the circuit behaviour is different in the following cases: > > - State a). Original design > > - State b). Originial design + output pin added + compiled + output pin > > removed + compiled > > But you're missing the point entirely. > > If your design doesn't meeting timing, and/or your timing constraints > are invalid/incorrect, then "all bets are off" as they say. This is exactly what was happening in this case. I was in the first phases of the design and did not care of the design not meeting timing. I "visually" inspected the relevant waveforms in a certain part of the circuit and -incorrectly- thought they were ok. > And yes, as far as I understand, some PAR algorithms *are* > non-deterministic, so two builds may result in a different bit-stream. > Indeed, incremental building will almost *definitely* produce different > results from a clean compile from scratch. > > My point is, under normal conditions and a 'flawless' design, Quartus > may well produce different output on different builds - but it will > always behave correctly. If the design is 'marginal' or just plain > incorrect, then this process may yield working output *some* of the > time, and non-working output others. Agreed. See my other post and Paul Leventis' response. > In your case, adding a pin causes the design to 'work'. Removing it and > you've lucky enough that Quartus still places in a manner that allows it > to work. > > Having said that, I wonder what your sample space is? I occasionally have to go into FPGA design, but am primarily working at RF. As a result, I am not an "expert". However, all my designs finally worked as expected :) > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266Article: 111791
Davy wrote: > Hi NigelE, > > Is AVM IEEE 1800 compatible? Thanks! > Yes it is. Adam. Adam Rose Verification Technologist Mentor GraphicsArticle: 111792
I have to build a block acting like a monostable with programmable duration:
____________
| | ________
In: _|___ -->| |----> Out: _| |____
| | <------->
Clk: --|> | duration
-------------
/ \
| |
duration
Which solutions is better:
a) Connect In to asyncronous preset and to D input ports of a flip-flop
that starts a counter, when counter reachs end it resets this flip flop;
_____________
In ----|Pre Clr|__________________________
| | | ________________ |
--|D | | Counter |---- End count
| Q|------ |
| | |---^-----------
Clk ----> | |
| | | |
| -------------- |
---------------------------
b) Connect In to the CLOCK input of a flip flop with its D input wired
to Vcc;
______________
___ | Clr|__________________________
| | | ________________ |
-----|D | | Counter |---- End count
| Q|------ |
| | |---^-----------
In ----> | |
| | |
-------------- |
Clk ---------------------------
Thank you in advance
Article: 111793I am looking for an 8bit * 8 bit pipelined multiplier. The algorithm I am trying to implement involves: 1 of the 8bits is used as the multiplier and the other, the multiplicand. A clock signal is used to activate this process. After the clock cycle: the first bit of the multiplier is looked at: if it is a "1", the multiplicand, ie 8 bits are copied into a buffer for storage, if the first bit is a "0" all zeroes ie. 00000000 are copied into the awaiting buffer. Secondly, the second bit of the multiplier is looked at, if this is a "1" the contents of the multiplicand are copied into the same buffer, but shifted one place to the left. An extra "0" is thus inserted in the space left after the shift. If the multiplier bit is a "0", then all zeroes are copied into the same buffer and shifted one place to the left, with an extra zero occupying the space left after the shift ie "000000000" This procedure is continued for all bits of the multiplier, shifting the product by 3 or 3 or 4 etc. The product results stored in the same buffer. Therefore this buffer would be kind of large. After this "logic coding" exercise we should have 8 products in the buffer, ie. P0, P1, P2, P3, P4, P5, P6, P7, P8. As seen above the clock signal is used for synchronization. After the buffer, other clock signals, attached to the first clock signal are used to push these products into several awaiting carry save adders (CSA). These CSA take 3 inputs, one of course the clock cycle, the others the products P0, P1 etc. After much research I think this CSA format is in the shape of what is called a Wallace tree. After these several summations, two sums are found, these are then inserted into a CPA, for the final summation. This result is the product of the 8bit * 8bit pipelined multiplier. I hope what i've stated above makes sense. I would really appreciate your assistance as soon as possible, since I have never used Verilog before. Any help will be welcomed and appreciated. Thank You! StephenArticle: 111794
Hello, Is there anyone who interface the C3188A - 1/3" Digital Output Colour Camera Module with an fpga. I am waiting for your answers. ThanksArticle: 111795
which series of fpga do you use? stephen.horsford@gmail.com yazdi: > I am looking for an 8bit * 8 bit pipelined multiplier. > > The algorithm I am trying to implement involves: > > 1 of the 8bits is used as the multiplier and the other, the > multiplicand. > > A clock signal is used to activate this process. After the clock cycle: > the first bit of the multiplier is looked at: if it > > is a "1", the multiplicand, ie 8 bits are copied into a buffer for > storage, if the first bit is a "0" all zeroes ie. 00000000 > > are copied into the awaiting buffer. > Secondly, the second bit of the multiplier is looked at, if this is a > "1" the contents of the multiplicand are copied into > > the same buffer, but shifted one place to the left. An extra "0" is > thus inserted in the space left after the shift. If the > > multiplier bit is a "0", then all zeroes are copied into the same > buffer and shifted one place to the left, with an extra > > zero occupying the space left after the shift ie "000000000" > This procedure is continued for all bits of the multiplier, shifting > the product by 3 or 3 or 4 etc. The product results > > stored in the same buffer. Therefore this buffer would be kind of > large. > After this "logic coding" exercise we should have 8 products in the > buffer, ie. P0, P1, P2, P3, P4, P5, P6, P7, P8. > > As seen above the clock signal is used for synchronization. > > After the buffer, other clock signals, attached to the first clock > signal are used to push these products into several > > awaiting carry save adders (CSA). These CSA take 3 inputs, one of > course the clock cycle, the others the products P0, P1 etc. > > After much research I think this CSA format is in the shape of what is > called a Wallace tree. > > After these several summations, two sums are found, these are then > inserted into a CPA, for the final summation. This result > > is the product of the 8bit * 8bit pipelined multiplier. > > I hope what i've stated above makes sense. > I would really appreciate your assistance as soon as possible, since I > have never used Verilog before. > > Any help will be welcomed and appreciated. > > Thank You! > > StephenArticle: 111796
Hi G=F6ran, Thanks for the quick reply - but the trick was to not be stupid. When synthesizing the route and place tool reports timing met, but the timing analysis tells me that the system cannot be run at 100MHz (which xapp730 claims). Reducing the clock to 66.67MHz made everything work as intended. MVH Johan On Nov 9, 4:07 pm, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > Hej Johan, > > Forgot to tell you to delete or rename that file if you have it. > > MVH > G=F6ran > > "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote in messagenews:eivg4m$qr= 02@cnn.xsj.xilinx.com... > > > Hej Johan, > > > Do you have a file called xmd_<microblaze_instance_name>.opt in the > > directory download? > > replace <microblaze_instance_name> with the name of the microblaze > > instance from the .mhs file. > > It can contain automatically settings which mess up the XMD communicati= on. > > This file get automatically used if you click on the XMD icon in XPS. > > > MVH > > G=F6ran > > > <e8jo...@gmail.com> wrote in message > >news:1163077412.628583.110960@m73g2000cwd.googlegroups.com... > >> Hi all, > > >> I've been struggling for two days now to get xapp730 from Xilinx to > >> work. I've built the hw (wo FSL as it seems to be confusing the > >> debugger) and can communicated with the CPU via xmd. However, the dow > >> command seems to be failing. See transcript of xmd session below. > > >> Any help or input is very much apprechiated. > > >> Best regards, > > >> Johan Thelin > > >> --- 8< --- > >> Address Map for Processor microblaze_0 > >> (0x00000000-0x00001fff) dlmb_cntlr dlmb > >> (0x00000000-0x00001fff) ilmb_cntlr ilmb > >> (0x24000000-0x27ffffff) DDR_SDRAM_64Mx32 mb_opb > >> (0x24000000-0x27ffffff) DDR_SDRAM_64Mx32 ixcl > >> (0x24000000-0x27ffffff) DDR_SDRAM_64Mx32 dxcl > >> (0x40000000-0x4000ffff) LEDs_4Bit mb_opb > >> (0x40020000-0x4002ffff) Push_Buttons_Position mb_opb > >> (0x40600000-0x4060ffff) RS232_Uart mb_opb > >> (0x40800000-0x4080ffff) IIC_EEPROM mb_opb > >> (0x40c00000-0x40c0ffff) Ethernet_MAC mb_opb > >> (0x41200000-0x4120ffff) opb_intc_0 mb_opb > >> (0x41400000-0x4140ffff) debug_module mb_opb > >> (0x41800000-0x4180ffff) SysACE_CompactFlash mb_opb > >> (0x41c00000-0x41c0ffff) opb_timer_1 mb_opb > > >> Connecting to cable (Parallel Port - LPT1). > >> Checking cable driver. > >> Driver windrvr6.sys version =3D 7.0.0.0.No resources. > >> LPT base address =3D 0378h. > >> ECP base address =3D 0778h. > >> Cable connection failed. > >> Connecting to cable (Parallel Port - LPT1). > >> Checking cable driver. > >> Driver windrvr6.sys version =3D 7.0.0.0. LPT base address =3D 0378h. > >> ECP base address =3D 0778h. > >> Cable connection failed. > >> Connecting to cable (Parallel Port - LPT2). > >> Checking cable driver. > >> Driver windrvr6.sys version =3D 7.0.0.0.Cable connection failed. > >> Connecting to cable (Parallel Port - LPT2). > >> Checking cable driver. > >> Driver windrvr6.sys version =3D 7.0.0.0.Cable connection failed. > >> Connecting to cable (Usb Port - USB22). > >> Checking cable driver. > >> Driver xusbdfwu.sys version: 1021 (1021). > >> Driver windrvr6.sys version =3D 7.0.0.0.Calling setinterface num=3D0, > >> alternate=3D0. > >> DeviceAttach: received and accepted attach for: > >> vendor id 0x3fd, product id 0x8, device handle 0x16726b4 > >> Cable PID =3D 0008. > >> Max current requested during enumeration is 280 mA. > >> Cable Type =3D 3, Revision =3D 0. > >> Setting cable speed to 6 MHz. > >> Cable connection established. > >> Firmware version =3D 1021. > >> CPLD file version =3D 0012h. > >> CPLD version =3D 0012h. > > >> JTAG chain configuration > >> -------------------------------------------------- > >> Device ID Code IR Length Part Name > >> 1 0a001093 8 System_ACE > >> 2 05059093 16 XCF32P > >> 3 01e58093 10 XC4VFX12 > >> 4 09608093 8 xc95144xl > >> Assuming, Device No: 3 contains the MicroBlaze system > >> Connected to the JTAG MicroProcessor Debug Module (MDM) > >> No of processors =3D 1 > > >> MicroBlaze Processor 1 Configuration : > >> ------------------------------------- > >> Version............................5.00.a > >> No of PC Breakpoints...............2 > >> No of Read Addr/Data Watchpoints...0 > >> No of Write Addr/Data Watchpoints..0 > >> Instruction Cache Support..........on > >> Instruction Cache Base Address.....0x24000000 > >> Instruction Cache High Address.....0x27ffffff > >> Data Cache Support.................on > >> Data Cache Base Address............0x24000000 > >> Data Cache High Address............0x27ffffff > >> Exceptions Support................off > >> FPU Support.......................off > >> FSL DCache Support.................on > >> FSL ICache Support.................on > >> Hard Divider Support...............on > >> Hard Multiplier Support............on > >> Barrel Shifter Support.............on > >> MSR clr/set Instruction Support....on > >> Compare Instruction Support........on > >> PVR Supported......................off > >> JTAG MDM Connected to MicroBlaze 1 > >> Connected to "mb" target. id =3D 0 > >> Starting GDB server for "mb" target (id =3D 0) at TCP port no 1234 > >> XMD% state > >> Connected targets state > > >> Target ID State Target Type > >> ---------------------------------------------------------- > >> 0 Stopped MicroBlaze MDM-based (hw) Target > >> XMD% mrd 0x24000000 100 > >> 24000000: FFFFFDFF > >> 24000004: FFFFFFFF > >> 24000008: FFFFFFFF > >> 2400000C: FFFFFEFF > >> 24000010: FFDFFFFF > >> 24000014: FFFFFFFF > >> 24000018: FFFFFFFF > >> 2400001C: FFFFFFFF > >> 24000020: FFFFFFFF > >> 24000024: FFFF7FFF > >> 24000028: BFFFFBFF > >> 2400002C: FFFFFFFF > >> 24000030: FFFFF7FF > >> 24000034: FFFFFFFF > >> 24000038: FFFFFFFE > >> 2400003C: FFFFFFFF > >> 24000040: FFFFFDFF > >> 24000044: FFFFFFF7 > >> 24000048: FFFFFFFF > >> 2400004C: FFFFFFFF > >> 24000050: FFFF7FFF > >> 24000054: FFFFFFFF > >> 24000058: FFFFBFFF > >> 2400005C: FFFFFFFF > >> 24000060: FFFFFFFF > >> 24000064: FFFFFFFF > >> 24000068: FFFFFBFF > >> 2400006C: FFFFFFFF > >> 24000070: FFFFDDFF > >> 24000074: FFFFF7FF > >> 24000078: FFFFFFFF > >> 2400007C: FFFFFFFF > >> 24000080: FFFFFFFF > >> 24000084: 7FFFFFFF > >> 24000088: FFFFFFFF > >> 2400008C: FFFFFFFF > >> 24000090: FDFFFFFF > >> 24000094: FFFFFFFF > >> 24000098: FFFFFFFF > >> 2400009C: FFFFFFFF > >> 240000A0: FFFFFFFF > >> 240000A4: FFFFFFFF > >> 240000A8: FFFFFFFF > >> 240000AC: FFFFFFFF > >> 240000B0: FFFF7FFD > >> 240000B4: FFFFFFFF > >> 240000B8: BFFFFFFF > >> 240000BC: BFFFFFFF > >> 240000C0: FFFFFFFF > >> 240000C4: FFFFF77F > >> 240000C8: FFFFFBFF > >> 240000CC: FFFFFFFF > >> 240000D0: FFDFFFFF > >> 240000D4: FFFFFFFF > >> 240000D8: FFFEFFFF > >> 240000DC: FFFFFFBF > >> 240000E0: FFFFFFFF > >> 240000E4: FFFFFFDF > >> 240000E8: FFFFFBFF > >> 240000EC: FBFFFFFF > >> 240000F0: FFFFFFFF > >> 240000F4: FFFFFFFF > >> 240000F8: FFFFFFFF > >> 240000FC: FFFFFFFF > >> 24000100: FFFFFFFF > >> 24000104: FFDFFFFF > >> 24000108: FFEFFBFF > >> 2400010C: FFFFFFFF > >> 24000110: FFFFFFFF > >> 24000114: F7FFFFFF > >> 24000118: FFFFFFFF > >> 2400011C: FFFFFFFF > >> 24000120: FFFFFFFF > >> 24000124: FFF7FFDF > >> 24000128: FFFFFFFF > >> 2400012C: FFFFFFFF > >> 24000130: FFFFFFFF > >> 24000134: FFFFFFFF > >> 24000138: FFFFFBFF > >> 2400013C: FFFFFFFF > >> 24000140: FFFFDFFF > >> 24000144: FFFFFFFF > >> 24000148: BFFFFFFF > >> 2400014C: FEFFFFFF > >> 24000150: FFFFFFFF > >> 24000154: FFFFFFFF > >> 24000158: FFFFFFFF > >> 2400015C: EFFFFFFF > >> 24000160: FFFFFFFF > >> 24000164: FFFFFFFF > >> 24000168: FFFFBEFF > >> 2400016C: FFFFFFFF > >> 24000170: FFFFFDFF > >> 24000174: FFFFFFFF > >> 24000178: FFFFFFFF > >> 2400017C: FFFFFFFF > >> 24000180: FFFFFFFF > >> 24000184: FFFFFDFF > >> 24000188: FFFFFEFF > >> 2400018C: FFFFFFFF > > >> XMD% mwr 0x24000000 1 > >> XMD% mrd 0x24000000 1 > >> 24000000: 00000001 > > >> XMD% dow -data image.bin 0x24000000 > >> XMD% mrd 0x24000000 100 > >> 24000000: 00000001 > >> 24000004: FFFFFFFF > >> 24000008: FFFFFFFF > >> 2400000C: FFFFFEFF > >> 24000010: FFDFFFFF > >> 24000014: FFFFFFFF > >> 24000018: FFFFFFFF > >> 2400001C: FFFFFFFF > >> 24000020: FFFFFFFF > >> 24000024: FFFF7FFF > >> 24000028: BFFFFBFF > >> 2400002C: FFFFFFFF > >> 24000030: FFFFF7FF > >> 24000034: FFFFFFFF > >> 24000038: FFFFFFFE > >> 2400003C: FFFFFFFF > >> 24000040: FFFFFDFF > >> 24000044: FFFFFFF7 > >> 24000048: FFFFFFFF > >> 2400004C: FFFFFFFF > >> 24000050: FFFF7FFF > >> 24000054: FFFFFFFF > >> 24000058: FFFFBFFF > >> 2400005C: FFFFFFFF > >> 24000060: FFFFFFFF > >> 24000064: FFFFFFFF > >> 24000068: FFFFFBFF > >> 2400006C: FFFFFFFF > >> 24000070: FFFFDDFF > >> 24000074: FFFFF7FF > >> 24000078: FFFFFFFF > >> 2400007C: FFFFFFFF > >> 24000080: FFFFFFFF > >> 24000084: 7FFFFFFF > >> 24000088: FFFFFFFF > >> 2400008C: FFFFFFFF > >> 24000090: FDFFFFFF > >> 24000094: FFFFFFFF > >> 24000098: FFFFFFFF > >> 2400009C: FFFFFFFF > >> 240000A0: FFFFFFFF > >> 240000A4: FFFFFFFF > >> 240000A8: FFFFFFFF > >> 240000AC: FFFFFFFF > >> 240000B0: FFFF7FFD > >> 240000B4: FFFFFFFF > >> 240000B8: BFFFFFFF > >> 240000BC: BFFFFFFF > >> 240000C0: FFFFFFFF > >> 240000C4: FFFFF77F > >> 240000C8: FFFFFBFF > >> 240000CC: FFFFFFFF > >> 240000D0: FFDFFFFF > >> 240000D4: FFFFFFFF > >> 240000D8: FFFEFFFF > >> 240000DC: FFFFFFBF > >> 240000E0: FFFFFFFF > >> 240000E4: FFFFFFDF > >> 240000E8: FFFFFBFF > >> 240000EC: FBFFFFFF > >> 240000F0: FFFFFFFF > >> 240000F4: FFFFFFFF > >> 240000F8: FFFFFFFF > >> 240000FC: FFFFFFFF > >> 24000100: FFFFFFFF > >> 24000104: FFDFFFFF > >> 24000108: FFEFFBFF > >> 2400010C: FFFFFFFF > >> 24000110: FFFFFFFF > >> 24000114: F7FFFFFF > >> 24000118: FFFFFFFF > >> 2400011C: FFFFFFFF > >> 24000120: FFFFFFFF > >> 24000124: FFF7FFDF > >> 24000128: FFFFFFFF > >> 2400012C: FFFFFFFF > >> 24000130: FFFFFFFF > >> 24000134: FFFFFFFF > >> 24000138: FFFFFBFF > >> 2400013C: FFFFFFFF > >> 24000140: FFFFDFFF > >> 24000144: FFFFFFFF > >> 24000148: BFFFFFFF > >> 2400014C: FEFFFFFF > >> 24000150: FFFFFFFF > >> 24000154: FFFFFFFF > >> 24000158: FFFFFFFF > >> 2400015C: EFFFFFFF > >> 24000160: FFFFFFFF > >> 24000164: FFFFFFFF > >> 24000168: FFFFBEFF > >> 2400016C: FFFFFFFF > >> 24000170: FFFFFDFF > >> 24000174: FFFFFFFF > >> 24000178: FFFFFFFF > >> 2400017C: FFFFFFFF > >> 24000180: FFFFFFFF > >> 24000184: FFFFFDFF > >> 24000188: FFFFFEFF > >> 2400018C: FFFFFFFF >=20 > >> XMD% >=20 > >> --- >8 ---Article: 111797
Bhanu Chandra wrote: > Hi, > > > Hi, > > I am getting the following error when I create a peripheral of my own > and > then add it to the project. As you can see i created and imported a > peripheral which has the name register_controller, the verilog file is > named user_logic.v. Please help me with this error. Is this a bug in > XPS which needs a patch? > > TIA [snip] > > ERROR:NgdBuild:604 - logical block > 'register_controller_0/register_controller_0/USER_LOGIC_I' with type > 'user_logic' could not be resolved. A pin name misspelling can cause > this, a > missing edif or ngc file, or the misspelling of a type name. Symbol > 'user_logic' is not supported in target 'virtex4'. This looks like a bug in XST that causes modules instantiated by verilog to be renamed if there is a VHDL instantiation of the same module. Unfortunately the netlist does not generate the underlying netlist for the renamed module, in your case it has "_0" appended, so you get the error during the translate process (NGDBUILD). I have worked around this by making sure that verilog instantiated module names do not match any VHDL instantiation names. This includes system library primitives like RAMB16_Sx_Sy. Again the workaround is to avoid using the same module name when instantiating from both VHDL and Verilog. This becomes a big headache for the case of primitives. I first noticed this in 8.1i and was hoping Xilinx would fix it by release 8.2i Another workaround for you may be to find your register_controller.ngc file and make a copy of it called register_controller_0.ngc In the case of library primitives you generally don't have the .ngc file available to rename. HTH, GaborArticle: 111798
tsemer wrote: > Hello everyone, > is there anyone who knows about the FPOA (Field Programmable Object > Array) by Mathstar? > Did anyone ever used this kind of programmable logic? > As they say in their site FPOA can proccess in very high frequencies > such as 1 GHz. > is there any suggestions about this silicon? > thank you very much. > > tsemer We'll be using the FPOA in an upcoming product. The array consists of a large number of ALU modules, which are really small microsequencers with a code size of 8 instructions. In addition to these there are a smaller number of register files and multiplier/accumulator modules in the array. Around the array are a number of peripheral controllers and larger block memories. Data flows though the array at the common clock rate of up to 1 GHz, using pipeline registers when it needs to traverse a large distance. This keeps the clock rate predictable under all routing conditions, but creates design pipeline changes in the process. The development tools help with this, but are still somewhat primitive compared to FPGA synthesis and P&R tools. You should not consider the FPOA as an FPGA replacement, because there are some things that FPGA's do better. If you could imagine a Xilinx FPGA with mostly DSP blocks and block rams and only a small number of slices, you would get a feel for the kind of tasks that would be hard to implement on the FPOA. On the other hand if you have a streaming data application that is very hard to implement at speed in a standard DSP chip, but too complex to fit well in an FPGA, the FPOA would be a good choice. HTH, GaborArticle: 111799
Can anyone tell me why the default width for the PLB in EDK is 64-bits when the PPC is a 32-bit processor? I have nothing in my design that is 64 bits wide. Am I wasting power and resources by using 64-bits? Thanks, Clark
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