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Dear Friends, Please forgive me if you confused while trying to understand my problems. In my mail there are many box marks or maybe question marks when I explain my flow states. They aren't box or question marks but they were right-direction arrow marks, because I was writing my mail with Microsoft Office before I posted to forum. So please forgive me for the inconvenience. And please I need the answer soon because I'd like to continue my project urgently. I have done everything to access J3 Intel Strata Flash including read Status Signal (SF_STS) prior to data replacements. But still doesn't make it updates the data. Please Masters, I need help urgently and I am waiting your answers A.S.A.P. Thank you for your attentions. Best regards, EkaArticle: 103176
John_H wrote: > > I'd suggest that there's no help provided by including the filename in > the information sent back to Xilinx. The part of the tool that spits > out the URL can simply strip the filename information. If there's a > need to know filetype, my competitors won't care if I'm working in > Verilog or VHDL so include filetype if desired. > > My opinion: it's bad form to include the filenames. > > Thanks for helping with the issue, Austin, > - John_H Howdy John, Agreed... unless the issue IS the path. Some programs have trouble with real long paths, or paths with long directory names, or paths with symbolic links, or UNC (Universal Naming Convention) paths. The only reason this came to mind is that I've had the tools blow up due to the hierarchy names being too long (actually it was several levels, each with long names). Not the same thing, but it doesn't seem impossible either. Have fun, MarcArticle: 103177
Thanks for your interest, I still didn't decide strictly what type of display, but it is going to be something like this module... http://www.sharpsma.com/part.php?PartID=4831 or this http://www.sharpsma.com/part.php?PartID=4817 I think this is standard connection for module like this, isn't it? So question is... how to connect this type of display to SPARTAN-3 and control it from uClinux? I realize that it have to be some core connected to PLB (?) or some other BUS on one side, and to I/O pins on other side in microblaze configuration? Am I right? Thank you for your efforts to help me Branko Karaklajic www.orpid.co.yuArticle: 103178
Marc Randolph wrote: > John_H wrote: > >>I'd suggest that there's no help provided by including the filename in >>the information sent back to Xilinx. The part of the tool that spits >>out the URL can simply strip the filename information. If there's a >>need to know filetype, my competitors won't care if I'm working in >>Verilog or VHDL so include filetype if desired. >> >>My opinion: it's bad form to include the filenames. >> >>Thanks for helping with the issue, Austin, >>- John_H > > > Howdy John, > > Agreed... unless the issue IS the path. Some programs have trouble > with real long paths, or paths with long directory names, or paths with > symbolic links, or UNC (Universal Naming Convention) paths. > > The only reason this came to mind is that I've had the tools blow up > due to the hierarchy names being too long (actually it was several > levels, each with long names). Not the same thing, but it doesn't seem > impossible either. I wondered if they thought that sending library names could help them ( ie the error just might cough up from a library file! ) but for general name issues & errors, these surely are not some unknown/lottery ! They could very easily test for valid file names, before passing them to the fussier tools, and say : "Sorry, tools do not like [spaces,paths>180char,you get the idea..]" - then there is no need to violate the customers security protocols, and one _really_ would think that Xilinx was VERY sensistive to this ?! :( - but it does nicely show, where true security problems come from, not the front door, but some casual side door, quite often technical-use in nature .... -jgArticle: 103179
Hallo, I have read about the chipsync technology based on iserdes implemented on Virtex-4. May I use it to connect a DVI connector directly to fpga without a receiver like tpf403? In this way I could deserialize the signal and obtain 24 bit rgb signal, right? Also, which kind of signal should I use? LVDS can support a 1,2Gb/s signal? Man Thanks, MarcoArticle: 103180
branek wrote: > > I realize that it have to be some core connected to PLB (?) or some > other BUS on one side, and to I/O pins on other side in microblaze > configuration? Am I right? Look at the CPUs that have LCD video interface. For example PXA255 from Intel. Plenty of docs at their web site. That will give you some idea. In general the (soft in your case) CPU should just write to a frame buffer. And some logic in the rest of the FPGA should scan that frame buffer and send bits to the LCD lines. For most panels there are 8 or 16 data lines and 3 clocks - pixel, horizontal and vertical. -Alex.Article: 103181
noArticle: 103182
what I did was to modify xilinx ip core to work with the display http://xilant.com/content/view/38/2/ the issue was that PLB is not supported in S-3 by default so you need to change several IP cores in EDK to enable s-3 family support as og linux support the microwindows application was compiled to directly work with the tft ip core, I did not have linux framebuffer driver at all. I tried by the framebuffer required several other drivers and some of them did not want to compile but xilinx framebuffer linux driver should be easy starting point anyway beware of the memory bandwidth, with single bank 32 bit wide sdram the tft refresh may consume over 70% of the total memory bandwidth AnttiArticle: 103183
Jim Granville <no.spam@designtools.co.nz> wrote: > This was just posted in c.a.e, but could have potential for fast >simulation times in FPGA developments ? :) > I presume the delay-simulations are OK with single precision 32 bit >floats ? >PDF article: http://www.cs.berkeley.edu/%7Esamw/projects/cell/CF06.pdf >web article: http://www.hpcwire.com/hpc/671376.html >With these speeds, it also looks like a nice device to put alongside a >FPGA.... Now we only need a parts supplier to start constructing with the cell cpu.. ;)Article: 103184
branek <orpid.yu@gmail.com> wrote: >Thanks for your interest, >I still didn't decide strictly what type of display, but it is going to >be something like this module... >http://www.sharpsma.com/part.php?PartID=4831 >or this >http://www.sharpsma.com/part.php?PartID=4817 >I think this is standard connection for module like this, isn't it? >So question is... how to connect this type of display to SPARTAN-3 and >control it from uClinux? A quick read of the datasheet. I think it goes something like this. Set VSHD to the same voltage as the spartan (3.3) select LVTTL output. As this seems to be the way to determine the V-IL and V-IH. Define a buffer of N1 bits that will satisfy this equation: N1 = ceil(display_bits/memory_bits) In the case of 18 bit display and 8 bit memory, N1 becomes =3. Then read a "word" of memory externally and put it in a buffer of the size N1. Do this until buffer is full. Then await clocking of data to display before letting the "memory counter" on loose again. It will need at most ceil(display_bits/memory_bits) cycles of transfer for every pixel. Drive VCOM and CS. Then setup a master clock at N1 x pixelclock. In this case pixelclock=DCLK. Use master clock + counter output to drive N2 bits. In this case N2 ought to be in the ballpark ceil(ln(320*240)/ln(2)) = 17 bits. So a 16-bit counter should do it. Then you drive AND gates, with inputs inverted as to make it active at a predetermined value of the counter output. And latch the output of the AND-gate for use on the opposite flank of the one that triggers the counter. Make certain counter values trigger LP, SPL, CLS, PS, SPS, memory fetch to appriate level. This should get you started.. Don't forgett those analogue signals aswell .. ;) (for contrast/brightness) There's also some lcd driver at opencores.org iirc. >I realize that it have to be some core connected to PLB (?) or some >other BUS on one side, and to I/O pins on other side in microblaze >configuration? Am I right?Article: 103185
>I, and probably others, regularly work on projects which "don't exist", >so any data collection for those projects is an unacceptable leak. Path >names frequently disclose projects names, and file names frequently >disclose intent. Even the data you do want to collect, regarding part >usage, discloses what type and size part, all of which can >inadvertently disclose the existance of an FPGA project (which doesn't >exist) using certain parts, which for very strict non-disclosure >projects would be an unacceptable breach. What about only allow http traffic from those machines through a proxy. And then have the proxy remove anything not authorized. Ie modify the http stream. That way vendor server is happy and customer don't have to provide restricted data.Article: 103186
Worked like a charm! :) Thank you all for your help!! RoiArticle: 103187
> What about only allow http traffic from those machines through a proxy. And > then have the proxy remove anything not authorized. Ie modify the http > stream. Based on what do you detect - at the proxy or wherever in your house - what you want not to let out. Plain search will be enough only for obvious transactions. Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > >I, and probably others, regularly work on projects which "don't exist", > >so any data collection for those projects is an unacceptable leak. Path > >names frequently disclose projects names, and file names frequently > >disclose intent. Even the data you do want to collect, regarding part > >usage, discloses what type and size part, all of which can > >inadvertently disclose the existance of an FPGA project (which doesn't > >exist) using certain parts, which for very strict non-disclosure > >projects would be an unacceptable breach. > > What about only allow http traffic from those machines through a proxy. And > then have the proxy remove anything not authorized. Ie modify the http > stream. That way vendor server is happy and customer don't have to provide > restricted data.Article: 103188
On Fri, 26 May 2006 07:55:10 -0700, Mike Treseler wrote: > Terry Brown wrote: >> Seems like the timing tool should also be smart enough to say "Aha! >> Coregen version of asynchronous fifo, let's be careful about some paths." > > Does your fifo have to be asynchronous? > > -- Mike Treseler Yes, data has to cross clock domains--an asynchronous fifo seemed the simplest methodArticle: 103189
If you are working on classified projects, then you should probably be working on a classified network. I regularly work on such projects, and the network has no external connections to the public Internet. Even if the tools wanted to report back, they have no path to Xilinx/Altera servers. The downside is that the only way to get data in is on CD-R, and on only one machine control by an internal IS person. If you aren't working on classified projects, but they are still considered sensitive, put the machine behind a firewall, and control outbound access. Or, get a node-locked license, and don't connect the machine at all. I do this on my personal (home) network, although I'm not terribly concerned about Xilinx or Altera learning about my educational activities. I even turned on the talk-back feature in Quartus II so I could use the logic analyzer cores. I do think companies could be a little more careful about data collection, though. I don't care if they report resource utilization and IP types, but why do they need my name or my company name?Article: 103190
All, Thank you to those who posted. All of this will be fed back to the tools folks. It is definitely a brave new world, and we are trying to take advantage of what we can, without causing any harm - real, or imagined. The folks who write our software are concerned about privacy and security. It is quite easy for them to put themselves in your shoes. For any of you familar with the Xilinx Values, the 'C' in the catch phrase (first letter) refers to 'customer.' The customer is the first thing we (should) think about when deciding anything. For any of you who ever visited, the "org chart" was my favorite: The top was the customer, with the Board of Directors at the bottom (upside down of a traditional org chart). All ideas are welcome. I am very familiar with firewalls, and with secure development (where the computers have no connection to anything outside, and no machine EVER leaves the facility, and no machine has any USB/CDR/etc. ability (other than read only). The security offered by our 3DES and 256AES relies on a third party: Xilinx. We are trusted to properly encypt the bitstream, and properly generate the keys. Since we are a 'trusted third party' it makes no sense at all to do anything that would shed any doubt on that trust. AustinArticle: 103191
Rob, you mntion that you do not use the FULL and EMPTY flags. In that case, the asynchronous FIFO design becomes trivial. Just have an address counter in each clock domain, and connect one to the write port, the other one to the read port. No Gray counters, no comparators, no anti-metastable re-synchronizers. All that complexity is only needed to generate reliable flags. Timing constraints that cross the clock domain are inherently meaningless, since there is no fixed timing relationship. Peter Alfke,Xilinx (from home)Article: 103192
Hi, I was wondering if it is possible to design a peripheral (for Microblaze) in EDK 7.1 which is connected to more than one OPB bus. If yes, how can this be done ? Thanx in advance .... SAVS.Article: 103193
you should be able to design a edk ip core with 2 opb slave ports, this should be connecatable to 2 different opb busses but then all the arbitration is to be done in your ip core. anttiArticle: 103194
> I'm curious if anyone owns one, and has looked to see if the necessary > configuration pins are brought out anywhere. I had the same idea, but at least in the Cyclone version of the board there's no way to reach them (and I think they're directly connected to a GND plane). The boards are a good buy anyway. I use one as a multi-purpose peripheral (playground) attached to a Coldfire CPU board (which does initial configuration via JTAG/LPT port). Other boards with fewer connectors (and less displays) are available from other vendors, those are better suited for standalone operation. K. -- mr. kolja waschk - haubach-39 - 22765 hh - germany fon +49 40 889130-34 - fax -35 - http://www.ixo.deArticle: 103195
>Based on what do you detect - at the proxy or wherever in your house - >what >you want not to let out. Plain search will be enough only for obvious >transactions. If data is not recognised proxy will drop it on the floor..Article: 103196
Well, I just succeeded to do similar thing. Can you, please, tell me how much of FPGA is used after your design was completed.Article: 103197
Hi, I am new to EDK, so kindly bear with me. How do I design such a edk ip core ? I mean if I use the 'Add/Import Peripheral Wizard' then there is no option to make the peripheral a slave on two OPB buses....what I plan to design is a shared memory system with two microblaze cores....for that i need a controller which is connected to the OPB buses of the processors and also to the external memory via an OPB bus. Thanx again.... SAVSArticle: 103198
Are you trying to initialize for 720 x 576 at 25 Hz frame rate with a 29.5 Mhz clock? And, how are you initializing the SD registers? Are you designing your own core and licensing a commercial core? DerekArticle: 103199
a system with: microblaze opb_ethernet opb_uart opb_gpio opb_spi opb_sdram plb_sdram plb_display (the xilinx modified) 30% of XC3S1500
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z