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-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Jim Granville wrote: > Stephen Williams wrote: >> GaLaKtIkUs™ wrote: >>> I wanted to use Icarus but I was confronted to a big problem (as a user >>> of Xilinx): in the simlation libraries there are specify blocs and >>> Icarus verilog doesn't support them and there are no shoft term plans >>> to support them. Great was my deception (as open source enthusiast) but >>> now I'm obliged to use a commercial simulator. >> >> >> It doesn't matter. The specify blocks are ignored and simulation >> works just fine. You will not be able to do back-annotated post- >> par timing simulations, but functional simulations work just fine. >> >> I (and my day job co-workers) use Icarus Verilog for Xilinx work >> all the time. > > Interesting - can you give some comments on the relative speed / > reliability /size of the present Icarus release ? I can say with certainty that a licensed Modelsim simulator is faster. Others will be able to say how much faster. I do image processing in a 1/3 full XC2V3000 w/ SDRAMS, and I can simulate plausible jobs. Sometimes I even do simulations on my 1.3GHz Powerbook G4:-) Now when you say "present Icarus release", there are the current snapshots and there is the v0.8 stable branch. The stable branch is a little faster in some cases, but is not as complete in others. The stable release is "stable", but the snapshots are getting the bug fixes and new features. - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.5 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFEkzc7rPt1Sc2b3ikRAhx5AJ9I6krjEnRhmfE8CNQ0IxLSSWkeuACfXEIA fHyPzIDCgAgjffEl1dwE+rM= =xg0D -----END PGP SIGNATURE-----Article: 104026
Austin Lesea wrote: > I still have no idea why this matters whatsoever, > > Sorry, You are right - if you are happy with Xilinx being third, then it makes no difference. (to you). -jg > > Austin > > Tommy Thorn wrote: > >> mk wrote: >> >>> Austin, >>> I think you misunderstand. The post was about "largest part WITH free >>> tool support". According to the op, now A seems to be winning this >>> contest and he wanted to see if X would up the ante. You're right, I >>> don't think anyone is asking for LX200 to be supported by free tools >>> but something larger than S3E 1600. How about it? >> >> >> >> Thanks, that's exactly what I was asking. I see now that I was unclear >> and I unfortunately didn't realize that Austin had misunderstood. All I >> was suggesting was for some of the Virtex 5 parts (larger than 70k LUT4 >> equiv.) to have free tool support (3S5000 would only be a narrow win >> over). >> >> It's not just a urination contest, it has real implications. >> >> Updating the score board (LUT4 / total memory): >> >> Altera: 68k / 1.2Mb (EP2C70) >> Lattice: 48k / 0.5Mb (ECP2-50) >> Xilinx: 33k / 0.9Mb (3S1600E) Highest memory to LUT ratio >> Actel: 25k / 0.1Mb (A3P1000) Adjust the 25k; this is LUT3 based >> Atmel: ? >> >> Tommy >>Article: 104027
Adam Megacz wrote: > All of the asynchronous-circuits-on-Xilinx work I've found to date has > involved either the XC6200 or jbits (Virtex-2-nonpro and earlier only). > > Is anybody aware of any self-timed/async work using Spartan-3 or > Virtex-IIPro/4/5? I suspect that Reece and Traver have done current Phased Logic work on newer Xilinx and Altera FPGAs. I'd suggest contacting them. http://www.erc.msstate.edu/mpl/projects/phased_logic/publications/mssu_coe_erc_01_03.pdfArticle: 104028
"Ray Andraka" <ray@andraka.com> wrote in message news:b_Dkg.47810$ZW3.16335@dukeread04... > 17/sqrt(21) is a constant= 3.7097..., which represented as a binary nubmer > is 011.1011010111 when rounded off to 10 bits right of the radix point. > You said your input is 9 bits, so you already have an error of > +/- 1/2 of the LSB weight. In most cases it doesn't make sense to > multiply by any more precision than you have in the input. Rounding your > constant to 9 bits (and treating as unsigned) gives: > 11.1011011. = 2^1 + 2^0 + 2^-1 +2^-3 + 2^-4 + 2^-6 + 2^-8 =3.7109375 > > This can be done with 4 adders arranged in 3 layers to sum shifted terms > of input N: > > a= N + N*2; > b= a + 8*a; > c= 8*N - N; > d= b + 64*c; > result = d/128; > > This will give you pretty much the fastest logic solution assuming no fast > memories. > > Your input is only 9 bits. If you are doing it in an FPGA, just program a > block ram as a look-up table ot (0:512)*17/sqrt(21) and be done with it. > If block RAMs are at a premium, and your FPGA has embedded multipliers, > use the embedded multiply to multiply the 9 bit input by > 0x1DB (or more bits if you so desire) and be done with it. I apologize for what remains of an obviously messed up piece of software on my machine. The post above was repeated scores of times byond the original post on May 30th. These two copies just made their way out of the clogged internat pipes. I replaced by netscape software with a fresh thunderbird install so I shouldn't see repeats of this message again. Ray, your suggestions are much what the other folks in the thread included. There are many, many ways to skin one cat, some people are just better at picking the best candidates.Article: 104029
fslearner wrote: > I'm currently working with an old imaging device whose only output is a > floppy drive which only allows transferring 6 images at a time (due to > floppy disk size constraint). I had the idea of implementing an FDC > (floppy drive controller) on an fpga then connecting the drive cable to > the fpga and using the fpga to stream the images through a serial port > thus bypassing the disk size constraint. Can anybody comment on the > feasibility of this project and perhaps point me to some existing VHDL > code? Otherwise, does anyone have any other feasible ideas? > My understanding is that you want to create a replacement device for the floppy drive so that you can stop having to shuffle data back and forth. This would mean that the FPGA device would have to fully emulate drive and the disk itself and to be completely transparent to the test equipment that you are using. That's not a trivial project. Why not just use something like the Delkin Flashpath SmartMedia Floppy Adapter http://www.amazon.com/gp/product/B00000JI3H/002-8914784-7568866?v=glance&n=172282 it looks like you might need to add a driver to the system, but your test equipment is likely running Windows under the hood anyway so this might be possible. If your test equipment has a spare IDE location then you could also just use a straight IDE to CompactFlash like this one. http://www.acscontrol.com/Index_ACS.asp?Page=/Pages/Products/CompactFlash/IDE_To_CF_Adapter.htm Ed McGettigan -- Xilinx Inc.Article: 104030
"Bluespace Technologies" <bluespace@rogers.com> writes: > I'm trying to use the sample pictiva VHDL code from Avnet to drive a mini > OLED (OSRAM Pictiva 128x64 pixel) on their test board, to get anything > presented (numerical data) on the screen. Has anyone got this device to > work, using sample code or other? I haven't tried yet. I am somewhat pissed off that the datasheet on the controller chip in the module is apparently nearly impossible to obtain, and the data sheet on the module doesn't give the details of the interface other than electrical parameters. This is not conducive to Pictiva getting design wins; they should arrange with the supplier of the controller chip for the data sheet on that chip to be publicly available. Or perhaps I'm wrong, and someone can point me to a URL where I can download it. Preferrably without having to "register" first. I'm really unhappy about this whole "register to download data sheets" phenomenon. Yesterday I needed to download data on a Samsung ARM-based SOC. I know I've downloaded data on the same chip in the past without registering, but now they require registration. I was willing to do that, but the registration system they are using will ONLY work if you run their ActiveX control. This is a problem for three reasons: * I use Firefox, not Internet Explorer, because IE's security has more holes than swiss cheese. * I'm not running Windows, so I couldn't run IE and ActiveX even if I wanted to. * Even if I *were* running Windows and IE, I wouldn't run ActiveX controls from web sites. The whole idea is abhorrent. At least Java has a carefully designed security sandbox for applets; ActiveX security is just about nonexistent. Conclusion: I won't be designing Samsung SOCs into any products. I'll likely use Cirrus Logic's part instead, or possibly TI.Article: 104031
"Leon" <leon.heller@bulldoghome.com> writes: > Steve Wozniak designed the Apple II floppy disk interface, many years > ago, using a few TTL chips, IIRC. Five TTL chips, one 555 timer, and a 256x8 PROM for a state machine. There is a second 256*8 PROM to store boot code, but that is logically independent of the disk controller functionality. However, the reason this worked is that it didn't have to be compatible with anything else in the world. The trick to making a good FDC is having a robust data separator. Simple techniques don't work well with marginal cases. Even a single DPLL doesn't solve the problem, because you need to deal with pulse shifting from the magnetic media independently of tracking frequency variations due to motor speed. A second-order DPLL works pretty well though. There was a lot of work done in this area in the 1980s. WD and SMC had US patents (which should have expired by now) on some clever second-order DPLL designs.Article: 104032
vans wrote: > I need to just rearrange pixels. I don't care at all of their values. > > The 10 bit TMDS link contains 10 bits, 8 for pixel data, 2 for control. Not really control but more like parity/encoding format bits. You probably know this but other people might be confused since the four links in an interface are R, G, B and "control". > I just need to rearrange pixels from different links, for a proprietary > lcd display. This sounds vaguely like you just want to multiplex video streams. That would be simple, but anything else is probably more complicated than you are imagining. > The pixel clock on DVI is max 150MHz, any decent high speed op amp can > easily handle that. But each pixel has to shoot ten bits through the wires, as you said above. That is 1.5Gbps or 750MHz worst case frequency. Both your op amps and your FPGAs will have trouble coping with that. -- JecelArticle: 104033
Rich Grise wrote: > [crossposted because it's about Xilinx S/W, I'm running Slackware, and > s.e.d is where all the really smart people hang out...] > > OK, I decided to take a chance and download that 839MB shell script that's > written for RedHat Enterprise, and was doing OK, (I had to shell out as > root a couple of times to give the install script permission to write to a > new directory, but that felt kind of kewl. :-) ), and now I'm at kind of a > stopper. The graphic install has the progress bar at 99%, and there's a > white-X-in-the-red-circle error message: Error: Cannot run process - > /usr/local/richgrise/Xilinx/.xinstall/install_driverscript > while simultaneously, the Konsole where I invoked it says: > ------<quote>------ > richgrise@thunderbird:~/L/Downloads/Xilinx_Webpack_8.1i_Webpack $ > WebPACK_81i_SFD.sh > Verifying archive integrity... All good. Uncompressing Xilinx ISE WebPACK > Installer..................................................................................................................................................................................................... > /lib/modules/misc/windrvr6.o: kernel-module version mismatch > /lib/modules/misc/windrvr6.o was compiled for kernel version > 2.4.18-14 while this kernel is version 2.4.31. > ------</quote>------ > and the console is patiently waiting (no prompt), and the error dialog box > is patiently waiting for me to click "OK". > > So, I wonder, is there some way to spoof Xilinx ISE for Red Hat Enterprise > into thinking that I have the older kernel? Or, maybe (yah, right) that > Xilinx guy who shows up from time to time on comp.arch.fpga might have > some suggestion. :-) > > Frankly, I'm kinda surprised that it's gotten as far as it has, running a > Red Hat Enterprise script on a plain vanilla Slackware box. :-) That's > Slackware 10.2, basically right out of the box; and the "Single File > Install" at Xilinx: > http://www.xilinx.com/ise/logic_design_prod/webpack.htm > > So, back to the question, can I spoof it? Or get enough source code to > recompile and relink it? I certainly don't want to try to install a > different kernel - that's WAY beyond my scope of "expertise". ;-) > > Thanks! > Rich My Linux knowledge and experience says "go for it", tell the install it is OK. Significant API changes the second version number. If you had a 2.4.X versus a 2.6.x version issue it could not be expected to not cause some problems. -- JosephKK Gegen dummheit kampfen die Gotter Selbst, vergebens.  --SchillerArticle: 104034
Commments like Eric's are important. I am engaged in round 2 of the battle for the "Xilinx Store", and there may even be light at the end of the tunnel. I have used quotes from this newsgroup to get some points across. I have told the powers that be that information, availability, and delivery time are crucial. And mentioning "in stock" availability while quoting 6 weks delivery is an insult. There are drawbacks: The prices do not look attractive, and probably it will be impossible to guarantee 10 ppm reliability, when tubes and trays are opened many times. (Xilinx is paranoid about quality, and that is good.) But both of these are secondary considerations when one builds a prototype. And I suggested "No Registration", just name, address and credit card # at the end of the transaction. But sales people collect user identities like scalps were collected in earlier times. Let's see what comes out of it. Peter Alfke ================= Eric Smith wrote: > "Bluespace Technologies" <bluespace@rogers.com> writes: > > I'm trying to use the sample pictiva VHDL code from Avnet to drive a mini > > OLED (OSRAM Pictiva 128x64 pixel) on their test board, to get anything > > presented (numerical data) on the screen. Has anyone got this device to > > work, using sample code or other? > > I haven't tried yet. I am somewhat pissed off that the datasheet on the > controller chip in the module is apparently nearly impossible to obtain, and > the data sheet on the module doesn't give the details of the interface other > than electrical parameters. > > This is not conducive to Pictiva getting design wins; they should arrange > with the supplier of the controller chip for the data sheet on that chip > to be publicly available. > > Or perhaps I'm wrong, and someone can point me to a URL where I can > download it. Preferrably without having to "register" first. > > > I'm really unhappy about this whole "register to download data sheets" > phenomenon. Yesterday I needed to download data on a Samsung ARM-based > SOC. I know I've downloaded data on the same chip in the past without > registering, but now they require registration. I was willing to do that, > but the registration system they are using will ONLY work if you run > their ActiveX control. This is a problem for three reasons: > > * I use Firefox, not Internet Explorer, because IE's security has more holes > than swiss cheese. > > * I'm not running Windows, so I couldn't run IE and ActiveX even if I wanted to. > > * Even if I *were* running Windows and IE, I wouldn't run ActiveX controls from > web sites. The whole idea is abhorrent. At least Java has a carefully > designed security sandbox for applets; ActiveX security is just about > nonexistent. > > Conclusion: I won't be designing Samsung SOCs into any products. I'll > likely use Cirrus Logic's part instead, or possibly TI.Article: 104035
Peter Alfke wrote: > Commments like Eric's are important. > I am engaged in round 2 of the battle for the "Xilinx Store", and there > may even be light at the end of the tunnel. > I have used quotes from this newsgroup to get some points across. > I have told the powers that be that > information, availability, and delivery time are crucial. > And mentioning "in stock" availability while quoting 6 weks delivery is > an insult. > There are drawbacks: > The prices do not look attractive, and probably it will be impossible > to guarantee 10 ppm reliability, when tubes and trays are opened many > times. (Xilinx is paranoid about quality, and that is good.) But both > of these are secondary considerations when one builds a prototype. yes, not many developers bench's are anywhere near 10ppm... ( ask antti ;) > > And I suggested "No Registration", just name, address and credit card # > at the end of the transaction. But sales people collect user identities > like scalps were collected in earlier times. Well, most would tolerate an ASCII registration, (especially if that means sales get-with-the-program) Eric's complaint is mainly with the silly extra froth and risk. Xilinx sent me about 6 invites to the last CPLD seminar, ( am I that important ? ) - so you could do a simple check to avoid that much traffic... -jgArticle: 104036
Eric Smith wrote: <snip> > > I'm really unhappy about this whole "register to download data sheets" > phenomenon. Sometimes this also is there to reduce denial-of-service attacks, where some bot machines in eastern europe, log in and merrily download all the PDF's they can find. Nice way to clog the pipes..... > Yesterday I needed to download data on a Samsung ARM-based > SOC. I know I've downloaded data on the same chip in the past without > registering, but now they require registration. I was willing to do that, > but the registration system they are using will ONLY work if you run > their ActiveX control. This is a problem for three reasons: > > * I use Firefox, not Internet Explorer, because IE's security has more holes > than swiss cheese. > > * I'm not running Windows, so I couldn't run IE and ActiveX even if I wanted to. > > * Even if I *were* running Windows and IE, I wouldn't run ActiveX controls from > web sites. The whole idea is abhorrent. At least Java has a carefully > designed security sandbox for applets; ActiveX security is just about > nonexistent. Did you complain to Samsung ? I remember Philips had a nonsense on their web site, where they linked to a stock ticker in the technical web pages, and that link was often very very slow : result was you could not load technical info, because some idjit had decided the stock price was important to everyone on the planet. I (and others) pointed out that was not quite true, and I see that is now removed from the technical pages. So, the speed may be glacial, but these big companies will respond.... -jgArticle: 104037
On 16 Jun 2006 12:32:07 +0200, "Symon" <symon_brewer@hotmail.com> wrote: >Hi Marco, >http://groups.google.com/groups?q=PCBs+for+modern+FPGAs >HTH, >Cheers, Syms. Also available at http://www.fpga-faq.org/archives/75000.html#75023 and the link http://www.fpga-faq.org/caf_pics/layer_1_2.gif Cheers, PhilipArticle: 104038
Odds are, this equipment is way too old to have a 3.5" floppy -or- an IDE port. Most likely, it's a 5.25" inch drive, mayby FAT12 360K, mayby not. It's still very doable. I've done something almost the same to the MFM interface on an old hard disk drive. Snag the -entire- data stream, sector/track headers and all into memory. A 360K floppy will fit into 1/2 meg of memory. Use a micro to sift through the image to find the data fields of the sectors. Then find the file system in those. If the micro has a usb port, you can emulate a flash key. Or write out to a SD/MMC card. Or whatever. It was a fun project; remember that the device will be reading as well as writing, if there's a file system on the "disk".Article: 104039
Hi, thank you all for you replies, in my board I have some more bga components like a Blackfin DSP and some memories. I was thinking I'd need at leat 6 layers, including a Vcc plane and a GND plane. Our pcb manufacturer could go down to 4mils tracks and this should allow me to route the board within those 6 layers, but, as long as this is my first bga board, I decided to ask more experinced and skilled people like you how to approach this project (how to start, routing startegies, how many layers and so on). MarcoArticle: 104040
GaLaKtIkUs™ wrote: > I wanted to use Icarus but I was confronted to a big problem (as a user > of Xilinx): in the simlation libraries there are specify blocs and > Icarus verilog doesn't support them. Could you write your own code and not use the libraries? -- Mike TreselerArticle: 104041
I remember seeing someone already did it, but with a microcontroller rather than an FPGA. Google for "semi-virtual disk". It is using an Atmel AVR uC to simulate a floppy. Works for both FM and MFM formats. -Alex.Article: 104042
backhus wrote:
> what do you mean with winner? Lowest overall FF count?
Sorry. I thought you meant converting a graph
to a netlist and minimizing the logic, maybe like this:
http://www.ece.utexas.edu/~adnan/syn-03/SIS_paper.pdf
> The question was if a state minimzation can be performed with ISE
> regardless of the encoding style.
Minimizing an arbitrary digraph is a hard problem,
so I'm not surprised the tools punt it.
> The Quartus results are quite interesting.
> In pseudo_states.pdf we can see the states before(!) minimization.
Yes, it drew them for me without even
being asked.
> The only difference between the double circled states and the single
> circled states is, that Y remains constantly '0'.
That makes some sense, as zero outputs
require no state decodes for d-flop synthesis.
> The ptd-fsm checks a serial bitstream X for non-BCD tetrades with LSB
> first (at S0) and MSB last (at S(>6)), setting the output Y at that moment.
> Now what happens in the QUARTUS created FSM when it should branch to S7
> or S11. Does it remain in S3 or S5 for 2 clock cycles?
Run a sim on the netlist.
I expect that it is functionally equivalent.
> Thank you for presenting these results.
You are welcome.
-- Mike Treseler
Article: 104043Alex Freed <alexf@mirrow.com> wrote: >I remember seeing someone already did it, but with a microcontroller >rather than an FPGA. Google for "semi-virtual disk". It is using an >Atmel AVR uC to simulate a floppy. Works for both FM and MFM formats. http://www.thesvd.com/ Seems to be a PIC 16C65b @ 20MHz + 256kByte sram in essence. Schematic+PCB: http://www.thesvd.com/SVD/Downloads/SVD-Instructions.pdfArticle: 104044
Jim Granville <no.spam@designtools.co.nz> wrote: >Austin Lesea wrote: >> I still have no idea why this matters whatsoever, >> >> Sorry, > You are right - if you are happy with Xilinx being third, >then it makes no difference. (to you). Maybe it's as to why LUT4/total memory quote matters. Not wheater being on position X in the list matters.Article: 104045
Rewrite the whole libraries, which model Xilinx primitives for all Xilinx FPGA/CPLD families and all speed grades? :-S Mike Treseler wrote: > GaLaKtIkUs=99 wrote: > > > I wanted to use Icarus but I was confronted to a big problem (as a user > > of Xilinx): in the simlation libraries there are specify blocs and > > Icarus verilog doesn't support them. > > Could you write your own code > and not use the libraries? >=20 > -- Mike TreselerArticle: 104046
GaLaKtIkUs™ wrote:
> Rewrite the whole libraries, which model Xilinx primitives for all
> Xilinx FPGA/CPLD families and all speed grades?
No.
Leave the primitives to synthesis.
Leave the timing to STA.
-- Mike Treseler
Article: 104047"pinku" <praveenkumar.bm@gmail.com> wrote in message news:1150463558.443993.57510@r2g2000cwb.googlegroups.com... > Hello, > > I am doing some Excel timing analysis of asynchronous interface. > I am finding difficult in formulating the formula for HOLD time margin. > > Write Transaction: > Read Transaction: > > > Any help will be great. > Thanks and regards > Praveen > I don't know fuck but I would read the data sheet. Hey, it's not like helping is a problem. I help lots of people every day. Makes me feel good to help you. Makes you feel good to have got some help. Makes me feel better knowing I have helped someone who needed some help. Makes me feel cuddly by giving the right sort of help. It's a win win situation. We should all try and help each other. Thank you in advance for your appreciation of my efforts. DNAArticle: 104048
Peter Alfke wrote: > I am engaged in round 2 of the battle for the "Xilinx Store", and there > may even be light at the end of the tunnel. [...] > There are drawbacks: > The prices do not look attractive, Unless the prices are substantially worse than the last time parts were offered through the store, I don't see that as a problem, other than possibly for hobbyists or students. Engineers are accustomed to one-off prices being relatively high. The purpose of having parts in the store is to guarantee quick availability in small quantities, not to have great prices. > and probably it will be impossible > to guarantee 10 ppm reliability, when tubes and trays are opened many > times. (Xilinx is paranoid about quality, and that is good.) But both > of these are secondary considerations when one builds a prototype. Agreed. I'd be willing to click-through an agreement regarding the fact that the devices are from open packages, may not meet Xilinx' usual quality standards, and must be baked if they are to be reflow soldered. In other words, I'm willing to treat them as engineering samples, even when the silicon is considered fully production qualified. > And I suggested "No Registration", just name, address and credit card # > at the end of the transaction. But sales people collect user identities > like scalps were collected in earlier times. In my opinion, the Xilinx web site registration process is one of the least obnoxious and better implemented ones around. I don't mind having to register nearly as much when it is easy to do and works with any browser. > Let's see what comes out of it. Thanks again for your efforts on this! EricArticle: 104049
Mike Treseler wrote: > GaLaKtIkUs=99 wrote: > > Rewrite the whole libraries, which model Xilinx primitives for all > > Xilinx FPGA/CPLD families and all speed grades? > > No. > Leave the primitives to synthesis. > Leave the timing to STA. STA? >=20 > -- Mike Treseler
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