Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com> writes: > If I may ask, what's your application for this ? Actually, if you're really curious, here's the poster describing current results (as of April) on Atmel's supurb devices: http://www.megacz.com/research/papers/bwrc.poster.pdf Note that I haven't yet built anything that requires an interlock. That's the next step. - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380Article: 104001
> With all the competition going on between A and X, I'd like to see more > movement in the category "Largest FPGA with free tool support". A, > with the Cyclone II EP2C70 has been the leader for a very long time > now. X only offers the Spartan 3E XC3S1600E is less than half the size > of the EP2C70. While not as large as the Altera's Cyclone II 70, Lattice's ispLEVER-Starter does support the Lattice ECP2-50, a 48K LUT4 90nm FPGA. You can download ispLEVER-Starter here: http://www.latticesemi.com/products/designsoftware/isplever/ispleverstarter.cfm Bart Borosky, LatticeArticle: 104002
I fixed the Xilinx script to solve its error. The script will not work after ISE 6.3. I had set my environment varibale to point to the my 6.2 install, but my PATH directory still pointed to the 8.1 binaries. Because of this, the Perl script was executing the program 'partgen' from the 8.1 binaries instead of the 6.2 binaries. I changed the perl script in 2 spots to pre-pend a path based on the XILINX environment variable to the invocation of the partgen program. Now I need to look at the output of the perl script... John P johnp wrote: > Brian - > > Thanks for the pointer to the Answer Record, unfortunately, the script > dies on my machine with the following error: > > FATAL_ERROR:StaticFileParsers:StaticAcdRead.c:614:1.48 - ACD file .acd > does not > exists Process will terminate. To resolve this error, please > consult the > Answers Database and other online resources at > http://support.xilinx.com. If > you need further assistance, please open a Webcase by clicking on > the > "WebCase" link at http://support.xilinx.com > > Any ideas? > > Thanks! > > John Providenza > > > Brian Davis wrote: > > johnp wrote: > > > Does anyone know if similar clocking is available on the V2Pro parts? > > Yes. > > > > > Any pointers to documentation? > > > > Other than XAPP609, I know of: > > - the phantom XAPP769 for S3 local clocks > > - manual inspection in FPGA Editor > > - the perl script in Answer Record 17697 : > > How do you determine I/O locations for Local Clock Routing > > according to XAPP609? > > > > Also, that DIFF_OUT buffer example code I posted a couple > > months ago had some local clocking notes in the comments. > > > > The various flavor DRAM app notes may have a few more tidbits > > of information, since the local clocks are used for DQS-like signals. > > > > BrianArticle: 104003
Check whether there really is any difference between LVTTL and LVCMOS. LVTTL inherited a Vohmin specification of 2.4 V from a 40-year old T.I. specification. Today this has no connection to reality, since in CMOS the output pulls to the rail, irrespective of any specification. Since it exceeds the spec, everybody is happy to comply with LVTTL... The difference between LVTTL and LVCMOS is really just a numbers game and has nothing to do with physical reality. Peter Alfke =============== KJ wrote: > "kia rui" <krbyxtrm@gmail.com> wrote in message > news:1150312807.015662.272400@f6g2000cwb.googlegroups.com... > > Is LVTTL or LVCMOS can be used for PCI Signaling? > > BTW, I'm using Atera MAX-II EPM1270T144C5... > > > > - kai - > > > > Depends on the > - Physical size of the PCI bus > - Number of loads > - PCI bus speed (33 or 66 MHz) > > But in some situations LVTTL can be used with no problem. > > KJArticle: 104004
"Antti" <Antti.Lukats@xilant.com> wrote: >fslearner schrieb: > >> I'm currently working with an old imaging device whose only output is a >> floppy drive which only allows transferring 6 images at a time (due to >> floppy disk size constraint). I had the idea of implementing an FDC >> (floppy drive controller) on an fpga then connecting the drive cable to >> the fpga and using the fpga to stream the images through a serial port >> thus bypassing the disk size constraint. Can anybody comment on the >> feasibility of this project and perhaps point me to some existing VHDL >> code? Otherwise, does anyone have any other feasible ideas? >> >> Thanks. > >should be doable. there is one guy who has floppy disk host interface >done by 100% software with some small microcontroller. So with FPGA >you defenetly can do it. but I bet you need todo it all from scratch. > >Antti Doable, no doubt, but you need more information than just the specs of the interface between floppy and controller. With an FPGA you can recover the raw data sent to the floppy as well as the head positioning and motor on/off commands. You will need details about the file system structure in the floppy to allow you to interpret these data and commands to recover the files you want to send out. As an aside, I worked for a company that made a system that simulated a magnetic tape drive, for similar purposes. Instead of filling a tape reel and then remove it and physically transport it to a different location to process the data, "fake" the drive, collect the data from the tape interface and stream it over the Internet for processing.Article: 104005
xilinx_user wrote: > > I have another question. I am now trying to simulate the core using the > ISE simulator in Webpack 8.1 I am running into the problem that the > output is always 0 no what frequency I set as the 'quiescent' frequency > for this core. > > I know I am doing something wrong. Do you have any general observations > along the lines of your reply to me? Any help with be appreciated. In the core generator project options (Project -> Project Options..., then Generation tab), you can choose either Behavioral or Structural simulation files. Try them both; sometimes one doesn't work. If you do this, make sure that you connect the signals correctly when instantiating the module. Some cores have the signals in a different order depending on whether Behavioral or Structural are chosen. --- Joe Samson Pixel VelocityArticle: 104006
Article: 104007
Article: 104008
vssumesh wrote: > Hi all, > I am doing a DDR SDRAM design which is obtained using the MIG tool. > The target device is V4LX60. But in that i observed a problem that the > controller is using differntial clocking. And IBUFGDP is used to buffer > the clcok. The problem is controller needs two differential clcok > signals. But the demo board support only one. Tried to assign the same > clock to different IBUFGDP units but in the par state it showed an > error. Is it possible to assign a differntial clcok signals to two > different buffers. One clock runs the IDELAY and the other clock runs the MIG logic. Thanks to a timely answer in comp.arch.fpga <http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/63fc624d0e1e38fd/5fd43818b8ab7a89#5fd43818b8ab7a89> we know that the IDELAY can run from 180MHz to 220MHz and can be driven from a DCM (thanks, Peter!). You can go through the MIG code and find where the reference clock has its IBUFGDP, delete the IBUFGDP, take the clock signal and connect it to any clock you have lying around that meets the 180MHz to 220MHz spec (or use a DCM output to generate one). > Second question is what is the risk involved in changing the RAM > controlller code to work with single ended clock. I am planning to use > 160 MHz for RAM operation. Shouldn't be a problem using single-ended, but if you can increase the rate to 180MHz, you can use the same clock for the IDELAY. --- Joe Samson Pixel VelocityArticle: 104009
mk wrote: > Austin, > I think you misunderstand. The post was about "largest part WITH free > tool support". According to the op, now A seems to be winning this > contest and he wanted to see if X would up the ante. You're right, I > don't think anyone is asking for LX200 to be supported by free tools > but something larger than S3E 1600. How about it? Thanks, that's exactly what I was asking. I see now that I was unclear and I unfortunately didn't realize that Austin had misunderstood. All I was suggesting was for some of the Virtex 5 parts (larger than 70k LUT4 equiv.) to have free tool support (3S5000 would only be a narrow win over). It's not just a urination contest, it has real implications. Updating the score board (LUT4 / total memory): Altera: 68k / 1.2Mb (EP2C70) Lattice: 48k / 0.5Mb (ECP2-50) Xilinx: 33k / 0.9Mb (3S1600E) Highest memory to LUT ratio Actel: 25k / 0.1Mb (A3P1000) Adjust the 25k; this is LUT3 based Atmel: ? TommyArticle: 104010
fslearner wrote: > I'm currently working with an old imaging device whose only output is a > floppy drive which only allows transferring 6 images at a time (due to > floppy disk size constraint). I had the idea of implementing an FDC > (floppy drive controller) on an fpga then connecting the drive cable to > the fpga and using the fpga to stream the images through a serial port > thus bypassing the disk size constraint. Can anybody comment on the > feasibility of this project and perhaps point me to some existing VHDL > code? Otherwise, does anyone have any other feasible ideas? > > Thanks. Steve Wozniak designed the Apple II floppy disk interface, many years ago, using a few TTL chips, IIRC. LeonArticle: 104011
John_H wrote: > References: <447ceb61@news.starhub.net.sg> > In-Reply-To: <447ceb61@news.starhub.net.sg> > Content-Type: text/plain; charset=us-ascii; format=flowed > Content-Transfer-Encoding: 7bit > Lines: 22 > Message-ID: <Ae8fg.9896$ho6.9329@trnddc07> > Date: Wed, 31 May 2006 03:40:16 GMT > NNTP-Posting-Host: 71.117.188.223 > X-Complaints-To: abuse@verizon.net > X-Trace: trnddc07 1149046816 71.117.188.223 (Tue, 30 May 2006 23:40:16 EDT) > NNTP-Posting-Date: Tue, 30 May 2006 23:40:16 EDT > > Mr. Ken wrote: > >>My task is to scale up a 9-bit data by 17/sqrt(21) (= 3.7097), with the >>best precision possible. Without considering clipping and range issues, I >>am using multiplication by 59/16, which gives 0.599% error. What better >>approach can I use? >> >>I am going to implement the calculation in ASIC, thus less complexity is >>what I am expecting. > > > Use more bits. If you were looking at simple shift for the division > you're on the right track but you need more digits such as 3799/10241. > > If ASICs have dedicated multipliers as a simple element, you probably > have what you need with a multiplier. > > If you have loads of time, a bit-serial approach can give you tiny. > > If you want abstruse, you can do a 115/31 where the divide by 31 is a > bunch of 5-bit adds and a few conditionals around the digit 31 (and a > bit of latency). > > Where do you want to go? 17/sqrt(21) is a constant= 3.7097..., which represented as a binary nubmer is 011.1011010111 when rounded off to 10 bits right of the radix point. You said your input is 9 bits, so you already have an error of +/- 1/2 of the LSB weight. In most cases it doesn't make sense to multiply by any more precision than you have in the input. Rounding your constant to 9 bits (and treating as unsigned) gives: 11.1011011. = 2^1 + 2^0 + 2^-1 +2^-3 + 2^-4 + 2^-6 + 2^-8 =3.7109375 This can be done with 4 adders arranged in 3 layers to sum shifted terms of input N: a= N + N*2; b= a + 8*a; c= 8*N - N; d= b + 64*c; result = d/128; This will give you pretty much the fastest logic solution assuming no fast memories. Your input is only 9 bits. If you are doing it in an FPGA, just program a block ram as a look-up table ot (0:512)*17/sqrt(21) and be done with it. If block RAMs are at a premium, and your FPGA has embedded multipliers, use the embedded multiply to multiply the 9 bit input by 0x1DB (or more bits if you so desire) and be done with it.Article: 104012
Hi, (This was posted in sci.electronics.design, but I'm reposting it here, as this might be a more fitting place). What is the best way to convert a differential DVI signal to single ended for use in an FPGA? (My FPGA does not support differential I/O) I was thinking high speed op amp in unity gain, but unsure of this as I'm not an analog circuit buff. I also need to take the output ports of the FPGA and convert them to differential signals. What is the best way to do this? Thanks, apologies for double post.Article: 104013
vans schrieb: > Hi, > > (This was posted in sci.electronics.design, but I'm reposting it here, > as this might be a more fitting place). > > What is the best way to convert a differential DVI signal to single > ended for use in an FPGA? (My FPGA does not support differential I/O) > > I was thinking high speed op amp in unity gain, but unsure of this as > I'm not an analog circuit buff. > > I also need to take the output ports of the FPGA and convert them to > differential signals. What is the best way to do this? > > Thanks, apologies for double post. you just cant do DVI with an FPGA without using proper DVI receiver and transmitter. . AnttiArticle: 104014
vans schrieb: > Hi, > > (This was posted in sci.electronics.design, but I'm reposting it here, > as this might be a more fitting place). > > What is the best way to convert a differential DVI signal to single > ended for use in an FPGA? (My FPGA does not support differential I/O) > > I was thinking high speed op amp in unity gain, but unsure of this as > I'm not an analog circuit buff. First, there are dedicaded differential to single ended converter ICs. Second, they wont work at thoses DVI speeds (370 Mbit/s??). > I also need to take the output ports of the FPGA and convert them to > differential signals. What is the best way to do this? Same procedure as above. Use dedicatd tranceiver ICs. But they must support the speed (which most ICs dont). Regards FalkArticle: 104015
Why Not? I don't need to decode the TMDS data. And, even if I did, the algorithm is pretty straightforward. Antti wrote: > vans schrieb: > > > Hi, > > > > (This was posted in sci.electronics.design, but I'm reposting it here, > > as this might be a more fitting place). > > > > What is the best way to convert a differential DVI signal to single > > ended for use in an FPGA? (My FPGA does not support differential I/O) > > > > I was thinking high speed op amp in unity gain, but unsure of this as > > I'm not an analog circuit buff. > > > > I also need to take the output ports of the FPGA and convert them to > > differential signals. What is the best way to do this? > > > > Thanks, apologies for double post. > > you just cant do DVI with an FPGA without using proper DVI receiver and > transmitter. > . > > AnttiArticle: 104016
vans schrieb: > Why Not? > > I don't need to decode the TMDS data. So why would you feed the DVI into a FPGA? Regards FalkArticle: 104017
Marco How many layers you end up using depends a lot on the manufacturer that you use for pcbs and their technology abilities, (principally track and gap and via size etc), that you use. I would say using the FT256 that a 4 layer board is easily viable on the right technology level probably 4/5 thou (0.1-0.127mm) track and gap and maybe down to the easier 6 thou or 0.15mm track and gap. A 6 layer board will probably allow you to use 8 thou or 0.2mm track and gap and allow a wider choice of potential pcb manufacturers. How you do it wil vary a lot depending on your pcb layout and what things connect to and where i.e. where things are placed but to give you a practical example of what can be achieved is our low cost Raggedstone1 product that achieves a full use of XC3S400(264 I/O), in a FG456 package, on a 4 layer board. I will say that wasn't easy even by our standards. The comparitive product of Xilinx(Digilent) Spartan-3E Starter Kit board I believe has 8 layers to do less than we do with I/O. On a more general point Xilinx used to have breakout patterns for things like Virtex2. Do have a search for those on their site. The is also some useful info here http://www.xilinx.com/bvdocs/userguides/ug072.pdf. John Adair Enterpoint Ltd. Marco wrote: > Hi all, > as many of you may know after all my posts, I'm working with a Spartan3 > in the FT256 BGA package. Could anyone give me a link or something on > documentation that may help me routing all those pins out in that kind > of package with a 4-6 layer board. I'd like to get some examples or > guidelines related to the most common approach adopted by experienced > people. > Thanks, > MarcoArticle: 104018
I need to just rearrange pixels. I don't care at all of their values. The 10 bit TMDS link contains 10 bits, 8 for pixel data, 2 for control. I just need to rearrange pixels from different links, for a proprietary lcd display. The pixel clock on DVI is max 150MHz, any decent high speed op amp can easily handle that. Falk Brunner wrote: > vans schrieb: > > Why Not? > > > > I don't need to decode the TMDS data. > > So why would you feed the DVI into a FPGA? > > Regards > FalkArticle: 104019
vans schrieb: > I need to just rearrange pixels. I don't care at all of their values. > > The 10 bit TMDS link contains 10 bits, 8 for pixel data, 2 for control. > > I just need to rearrange pixels from different links, for a proprietary > lcd display. > > The pixel clock on DVI is max 150MHz, any decent high speed op amp can > easily handle that. So go for the dedicaded converters (DVI is LVDS I guess). There are LVDS-CMOS converters. Regards FalkArticle: 104020
Joseph Samson wrote: > xilinx_user wrote: > > > > I have another question. I am now trying to simulate the core using the > > ISE simulator in Webpack 8.1 I am running into the problem that the > > output is always 0 no what frequency I set as the 'quiescent' frequency > > for this core. > > > > I know I am doing something wrong. Do you have any general observations > > along the lines of your reply to me? Any help with be appreciated. > > In the core generator project options (Project -> Project Options..., > then Generation tab), you can choose either Behavioral or Structural > simulation files. Try them both; sometimes one doesn't work. If you do > this, make sure that you connect the signals correctly when > instantiating the module. Some cores have the signals in a different > order depending on whether Behavioral or Structural are chosen. > > --- > Joe Samson > Pixel Velocity Thanks. I had already tried both behavioral and structural, and neither one worked. I then did a post route simulation and that seems to work. This simulator seems flaky, if not goofy. I am not sure I trust anything out of it. In any event, thanks for the help.Article: 104021
I still have no idea why this matters whatsoever, Sorry, Austin Tommy Thorn wrote: > mk wrote: > >>Austin, >>I think you misunderstand. The post was about "largest part WITH free >>tool support". According to the op, now A seems to be winning this >>contest and he wanted to see if X would up the ante. You're right, I >>don't think anyone is asking for LX200 to be supported by free tools >>but something larger than S3E 1600. How about it? > > > Thanks, that's exactly what I was asking. I see now that I was unclear > and I unfortunately didn't realize that Austin had misunderstood. All I > was suggesting was for some of the Virtex 5 parts (larger than 70k LUT4 > equiv.) to have free tool support (3S5000 would only be a narrow win > over). > > It's not just a urination contest, it has real implications. > > Updating the score board (LUT4 / total memory): > > Altera: 68k / 1.2Mb (EP2C70) > Lattice: 48k / 0.5Mb (ECP2-50) > Xilinx: 33k / 0.9Mb (3S1600E) Highest memory to LUT ratio > Actel: 25k / 0.1Mb (A3P1000) Adjust the 25k; this is LUT3 based > Atmel: ? > > Tommy >Article: 104022
> Vivek Menon wrote: > > Hi, Iam looking to use Virtex-4 Rocket IO capability so as to use the > > Aurora core and probably intercae the FPGA board to similar such boards > > using coaxial cables or any available interface. > > We have several boards that do what you describe. The lowest cost board would be the DNDVI card. http://www.dinigroup.com/index.php?product=DN8000k10pci&PHPSESSID=f1cfc7c6d28ae81d6f69cab3274f8b62 http://www.dinigroup.com/dvidc.phpArticle: 104023
The S3E starter kit was initilaly scheduled for release in july 2004. It became available spring 2006 (this year) . Say no more. "John_H" <johnhandwork@mail.com> wrote in message news:V9Ejg.3356$oa1.1432@news02.roc.ny... > The Xilinx webcast just ended. It was a nice intro to the board; I've got > one on my desk so I learned nothing new about my "toy" but for those > wondering whether to take the plunge, I'd recommend the board. > > What was "teased" in the webcast and not followed up was a new board on the > horizon using the largest Spartan 3E: the XC3S1600E. > > Any info on the board as it develops would be appreciated. Some folks on > the newsgroup were disappointed in the lack of stubless LVDS paths to get > on/off the board and this lack did put a crimp on my prototyping a few 600 > MB/s links (I implemented one very nicely as a proof of concept, though). > > There are lots of wants among the people who visit the newsgroup regularly. > If there's anything to whet our appetite or any input before the schematic > is final, we're here and some of us are even eager. > > But for $150, don't wait for the big board. > > - John_H > >Article: 104024
mike_la_jolla wrote: >> Vivek Menon wrote: >>> Hi, Iam looking to use Virtex-4 Rocket IO capability so as to use the >>> Aurora core and probably intercae the FPGA board to similar such boards >>> using coaxial cables or any available interface. >>> > We have several boards that do what you describe. The lowest cost > board would be the DNDVI card. > > http://www.dinigroup.com/index.php?product=DN8000k10pci&PHPSESSID=f1cfc7c6d28ae81d6f69cab3274f8b62 > > http://www.dinigroup.com/dvidc.php > I would personnaly recommend that board (DNDVI), it's really great ! We got it a few weeks ago and we didn't have any major issues with it. And when you look at the schematics, you feel that they anticipated your needs and took care of little details. Of course we needed mainly DVI connectivity and RAM ;) We also use a rocket io connection to connect a SGMII phy board and get gigabit ethernet and it works fine. Here is some info about the rocket io on that board : - The clock connected to the rocket io banks is either (depending of the rocket io bank) a fixed 250MHz clock or the output of the PLL with a 21.48MHz reference. - The rocket io are directly connected to the SMA, nothing in-between. I know some standard requires a AC coupling cap to be placed as close as the transmitter as possible ... - There is no SMA to bring in a clock to the rocket io (I think that's my most annoying point ...) There is a two pin standard 2.54mm pitch connector to bring one differential clock IIRC but it's not SMA and I don't know how degraded a clock would be using this connector. Sylvain
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z