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"Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:e6d4pl$9e31@cliff.xsj.xilinx.com... > John Smith wrote: > > "gallen" <arlencox@gmail.com> wrote in message > > news:1149896992.818022.324140@y43g2000cwc.googlegroups.com... > >> What about the ML401. It's about the same price. You get a Virtex 4 > >> instead of the Spartan 3. The peripherals look about the same. The > >> LX25 is a little smaller than the S3-1500, but not tons smaller and > >> it's still supported by webpack. > > > > Ok, but my point is that > > 1: Xilinx does not offer any customer support. > > 2: Xilinx does not offer any customer support. > > 3: Xilinx does not offer any customer support. > > > > I'ts impossiblle to get hold of the guys ! Even simple guestion ! > > NO saupport e-mail. NO support phone ? What am I supposed to do ? > > I would suggest that you try http://support.xilinx.com Right at the > top you will see a tab labeled "Contact Support" where you can follow > the links to file a WebCase on your issue or to get the phone number > for technical support as well. > > In additional to our official support channels we also monitored this > newsgroup for issues. To claim that Xilinx does not offer any customer > support is a bit of hyperbole. No, it's not. I have tried to register with Xilinx support, but I got a reply that stated that since I was not an employe , but only a student, I could not get direct support. May be there is some part of "You can not join" that I did not understand ?Article: 103751
Well, Mr. Mcgettigan, I hope you will come up with an e-mail to someone who can give me som answers about HARDWARE issues on the SP305-board itself . Thats all I ask for. It's 4:00 saturday morning here now, so I'm turning in. I have a nice day ahead of me, no clouds and 80 F +. I have no boat, I'm sorry to say, but I migt take a trip out to one one the local islands here i Oslofjorden, and just relax. Have a nice weekend ! PS. Give me best regards to Austin as well. DS. "Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:e6d4pl$9e31@cliff.xsj.xilinx.com... > John Smith wrote: > > "gallen" <arlencox@gmail.com> wrote in message > > news:1149896992.818022.324140@y43g2000cwc.googlegroups.com... > >> What about the ML401. It's about the same price. You get a Virtex 4 > >> instead of the Spartan 3. The peripherals look about the same. The > >> LX25 is a little smaller than the S3-1500, but not tons smaller and > >> it's still supported by webpack. > > > > Ok, but my point is that > > 1: Xilinx does not offer any customer support. > > 2: Xilinx does not offer any customer support. > > 3: Xilinx does not offer any customer support. > > > > I'ts impossiblle to get hold of the guys ! Even simple guestion ! > > NO saupport e-mail. NO support phone ? What am I supposed to do ? > > I would suggest that you try http://support.xilinx.com Right at the > top you will see a tab labeled "Contact Support" where you can follow > the links to file a WebCase on your issue or to get the phone number > for technical support as well. > > In additional to our official support channels we also monitored this > newsgroup for issues. To claim that Xilinx does not offer any customer > support is a bit of hyperbole. > > Ed McGettigan > -- > Xilinx Inc.Article: 103752
I would highly recommend the *free*, multi-OS Perforce Visual Merge Tool (P4Merge -- http://www.perforce.com/perforce/products/merge.html) This is a true three-way merge tool, which is what you want when you are doing multi-user code development. You give the tool two or three versions of the code. Two-way merge is exactly as with any other tool. However, it's three way merge where P4Merge really shines. You supply the "Base", "Left", and "Right" files to it. The Base is the file you started with before making your changes. Left is your file. And Right is the other file someone else has created -- they've made changes (starting from base) at the same time as you were making your changes. It will then do a correct merge, and it does an excellent job flagging conflicts. This is the tool many of ourdevelopers use for merging, and in my experience, it is signficantly better (fewer mistakes, better conflict identification) than many other tools. Regards, Paul Leventis Altera Corp.Article: 103753
"blisca" <blisca@tiscali.it> wrote in message news:448a698e$0$18282$4fafbaef@reader1.news.tin.it... > > blisca <blisca@tiscali.it> wrote in message > 448a0bad$0$14780$4fafbaef@reader4.news.tin.it... > > > > John Smith <someone@microsoft.com> wrote in message > > e6cskr$ofc$2@readme.uio.no... > > > > > > "blisca" <blisca@tiscali.it> wrote in message > > > news:4489bd31$0$18288$4fafbaef@reader1.news.tin.it... > > > > hello > > > > i built on myself a cable 3 interface,following the xilinx drawing,i > > > checked > > > > in all the possible ways,ohmically,injecting square waves,and then > once > > > > connected tho the parallel port i used the option in the Jtag > programmer > > > > utility that allows to force level on tdi,sending n clock pulses and > so > > > > on,these signals are present on the pins of the fpga and the cable is > > > > connected to the supply(5V),but the pc doesn't see the cable at all > > > > please,anyone can help me?thanks! > > > > > > > > > > Try the different BIOS setup options on your computer for the port in > > > question. It worked wonders for me, but that was a Parallel IV cable. > When > > > it was set to ECP-mode, everything worked so much better. > > > > > > > > despite here in italy are 1:45 a.m. i want to follow your hint,stay tuned > > and thank you > > > no way :-( but thank you Well, try to change the port. My Cable IV would not work at all on my "expansion bord" LPT, but it worked on my mainboard LPT. Maybe the opposite is the case for you ? Regards, JohnArticle: 103754
John Smith <someone@microsoft.com> wrote in message e6dtau$6jo$2@readme.uio.no... > > "blisca" <blisca@tiscali.it> wrote in message > news:448a698e$0$18282$4fafbaef@reader1.news.tin.it... > > > > blisca <blisca@tiscali.it> wrote in message > > 448a0bad$0$14780$4fafbaef@reader4.news.tin.it... > > > > > > John Smith <someone@microsoft.com> wrote in message > > > e6cskr$ofc$2@readme.uio.no... > > > > > > > > "blisca" <blisca@tiscali.it> wrote in message > > > > news:4489bd31$0$18288$4fafbaef@reader1.news.tin.it... > > > > > hello > > > > > i built on myself a cable 3 interface,following the xilinx drawing,i > > > > checked > > > > > in all the possible ways,ohmically,injecting square waves,and then > > once > > > > > connected tho the parallel port i used the option in the Jtag > > programmer > > > > > utility that allows to force level on tdi,sending n clock pulses and > > so > > > > > on,these signals are present on the pins of the fpga and the cable > is > > > > > connected to the supply(5V),but the pc doesn't see the cable at all > > > > > please,anyone can help me?thanks! > > > > > > > > > > > > > Try the different BIOS setup options on your computer for the port in > > > > question. It worked wonders for me, but that was a Parallel IV cable. > > When > > > > it was set to ECP-mode, everything worked so much better. > > > > > > > > > > > despite here in italy are 1:45 a.m. i want to follow your hint,stay > tuned > > > and thank you > > > > > no way :-( but thank you > Well, try to change the port. My Cable IV would not work at all on my > "expansion bord" LPT, but it worked on my mainboard LPT. Maybe the opposite > is the case for you ? > > Regards, > > John > >mmmmmm.....thank you but i tried it yet on 2 different pc's ,reverse proof now should be to find another cable III and use it on the same pc.......... if i could find it here in italy i should buy an official xilinx programmer.......Article: 103755
Hi Paul, I will try P4Merge. Thank you for your suggestion. WengArticle: 103756
Hi all, I have some basic doubts. The initialization sequence for sdram's from different chip manufacturers vary slightly although the ones that I have referred to(micron, samsung, hynix) use "precharge followed by 2 auto-refresh cycles". how does this wake up the device? Also does the 2 cycles here mean two complete refreshes of 4096 rows? My understanding is this. Once I power-up and initialize using burst type auto-refresh, my device is in idle state and because I write/read every row and column more than twice within 64ms, i dont need any refresh. Although from post-place and route simulation results I can verify that the logic and timing for memory controller is ok, the pattern still looks very strange(on the monitor after configuration with the bit fle). It looked to me like once every few rows, a wrong row is opened. The only thing that changed this strange pattern was the auto-refresh counter in the initialization sequence Auto-refresh specified can be implemented either as a burst of 4096 cycles every 64ms or can be distributed every 15.625 us right? so while initializing the device if I use burst type command then after 2 complete cycles the device should be in idle state. Does the internal refresh counter stop working now? and if I dont issue any refresh then it cannot carry on any kind of refresh operation now can it? Any help is greatly appreciated. Thanks Subhasri.KArticle: 103757
Hello, both VHDL and Verilog are well established standards that have been widely adopted by the engineering community. Excellent behavioral simulators are available for both of the languages. Therefore it would be prgamatic to use Verilog and VHDL for new projects. AHDL is simple to use but a lot of what can be done in AHDL can be accomplished with Verilog and VHDL. As language parsing and synthesis are two separate processing steps all three languages benefit from the improvements that are made to the Quartus core logic synthesis and technology mapping algorithms. Therefore you will be able to achieve equivalent Quality of Results with all three languages. - Subroto Datta Altera Corp. "czerstwy" <czebaka@o2.pl> wrote in message news:e6cc9t$2tg$1@news.onet.pl... > Subroto Datta napisał/a: >> AHDL support will be there in Quartus for a long long time.The AHDL >> language, is fully maintained and supported for reasons of backwards >> compatibility. There are lots of legacy Max+Plus II designs which >> customers are migrating to Quartus for use in both existing and new >> projects. We are sensitive to our customers needs and will not do >> anything to jeopardize their productivity. > > Is backward compatibility the only reason why Altera keeps AHDL in > Quartus? Which languages Altera suggests to use in new projects? > > czerstwyArticle: 103758
Subhasri krishnan wrote: > I have some basic doubts. The initialization sequence for sdram's from > different chip manufacturers vary slightly although the ones that I > have referred to(micron, samsung, hynix) use "precharge followed by 2 > auto-refresh cycles". how does this wake up the device? Also does the 2 > cycles here mean two complete refreshes of 4096 rows? Does anyone here know the purpose of the SDRAM initialization sequence? I have never implemented it and never noticed any sort of failure in my designs. This may be because I mostly use it for frame buffers and fifos (sequential access), not cpu (random access) designs. Alan NishiokaArticle: 103759
Alan Nishioka wrote: > Subhasri krishnan wrote: > > I have some basic doubts. The initialization sequence for sdram's from > > different chip manufacturers vary slightly although the ones that I > > have referred to(micron, samsung, hynix) use "precharge followed by 2 > > auto-refresh cycles". how does this wake up the device? Also does the 2 > > cycles here mean two complete refreshes of 4096 rows? > > Does anyone here know the purpose of the SDRAM initialization sequence? > > I have never implemented it and never noticed any sort of failure in my > designs. > > This may be because I mostly use it for frame buffers and fifos > (sequential access), not cpu (random access) designs. > > Alan Nishioka I am not sure I understand what you're saying. You never implemented the initialization sequence? Isnt it essential to do it irrespecitve of the way the sdram is used? or maybe you meant auto-refresh? Please do clarify. I am also working on frame buffers and noticed that some of the scan lines looked wrong. Auto-refresh seemed to be the only command that affected the image. - Subhasri.KArticle: 103760
Subhasri krishnan wrote: > Alan Nishioka wrote: > > Subhasri krishnan wrote: > > > I have some basic doubts. The initialization sequence for sdram's from > > > different chip manufacturers vary slightly although the ones that I > > > have referred to(micron, samsung, hynix) use "precharge followed by 2 > > > auto-refresh cycles". how does this wake up the device? Also does the 2 > > > cycles here mean two complete refreshes of 4096 rows? > > > > Does anyone here know the purpose of the SDRAM initialization sequence? > > > > I have never implemented it and never noticed any sort of failure in my > > designs. > > > > This may be because I mostly use it for frame buffers and fifos > > (sequential access), not cpu (random access) designs. > > > > Alan Nishioka > > I am not sure I understand what you're saying. You never implemented > the initialization sequence? Isnt it essential to do it irrespecitve of > the way the sdram is used? or maybe you meant auto-refresh? Please do > clarify. I have never implemented the SDRAM init sequence. The manual says it is essential, but not why. Also, I don't refresh (auto or otherwise) since I am continually writing and reading every row that I am interested in. This has worked fine for me with several different designs and several different SDRAMs (Hitachi, Micron and Samsung that I am certain of). > I am also working on frame buffers and noticed that some of the scan > lines looked wrong. Auto-refresh seemed to be the only command that > affected the image. It seems that you are trying to do a similar thing, so I don't know what is causing you problems. I didn't use refresh (auto or otherwise) because I didn't need it and it would have interrupted my stream at an inconvenient time. Alan NishiokaArticle: 103761
List of Xilinx distributors on this page http://www.xilinx.com/company/sales/ww_disti.htm. looks like you have a choice in Italy. More than we have in the UK. John Adair Enterpoint Ltd. blisca wrote: > John Smith <someone@microsoft.com> wrote in message > e6dtau$6jo$2@readme.uio.no... > > > > "blisca" <blisca@tiscali.it> wrote in message > > news:448a698e$0$18282$4fafbaef@reader1.news.tin.it... > > > > > > blisca <blisca@tiscali.it> wrote in message > > > 448a0bad$0$14780$4fafbaef@reader4.news.tin.it... > > > > > > > > John Smith <someone@microsoft.com> wrote in message > > > > e6cskr$ofc$2@readme.uio.no... > > > > > > > > > > "blisca" <blisca@tiscali.it> wrote in message > > > > > news:4489bd31$0$18288$4fafbaef@reader1.news.tin.it... > > > > > > hello > > > > > > i built on myself a cable 3 interface,following the xilinx > drawing,i > > > > > checked > > > > > > in all the possible ways,ohmically,injecting square waves,and then > > > once > > > > > > connected tho the parallel port i used the option in the Jtag > > > programmer > > > > > > utility that allows to force level on tdi,sending n clock pulses > and > > > so > > > > > > on,these signals are present on the pins of the fpga and the cable > > is > > > > > > connected to the supply(5V),but the pc doesn't see the cable at > all > > > > > > please,anyone can help me?thanks! > > > > > > > > > > > > > > > > Try the different BIOS setup options on your computer for the port > in > > > > > question. It worked wonders for me, but that was a Parallel IV > cable. > > > When > > > > > it was set to ECP-mode, everything worked so much better. > > > > > > > > > > > > > > despite here in italy are 1:45 a.m. i want to follow your hint,stay > > tuned > > > > and thank you > > > > > > > no way :-( but thank you > > Well, try to change the port. My Cable IV would not work at all on my > > "expansion bord" LPT, but it worked on my mainboard LPT. Maybe the > opposite > > is the case for you ? > > > > Regards, > > > > John > > > >mmmmmm.....thank you but i tried it yet on 2 different pc's ,reverse proof > now should be to find another cable III > and use it on the same pc.......... > if i could find it here in italy i should buy an official xilinx > programmer.......Article: 103762
John, Students are being supported through the webcase email system, as our agreement with a university for support of students expired, and no one wanted to continue to provide student support. Seems that universities are equally challenged to do things for free. Since we do recognize and appreciate students using Xilinx parts, we chose to provide support through email webcase. No phones for students (what I was told, but maybe that changed. I'll get corrected if I'm wrong). Sorry. Phone calls cost money. Emails are much more efficient. Austin John Smith wrote: > "Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message > news:e6d4pl$9e31@cliff.xsj.xilinx.com... > >>John Smith wrote: >> >>>"gallen" <arlencox@gmail.com> wrote in message >>>news:1149896992.818022.324140@y43g2000cwc.googlegroups.com... >>> >>>>What about the ML401. It's about the same price. You get a Virtex 4 >>>>instead of the Spartan 3. The peripherals look about the same. The >>>>LX25 is a little smaller than the S3-1500, but not tons smaller and >>>>it's still supported by webpack. >>> >>>Ok, but my point is that >>>1: Xilinx does not offer any customer support. >>>2: Xilinx does not offer any customer support. >>>3: Xilinx does not offer any customer support. >>> >>>I'ts impossiblle to get hold of the guys ! Even simple guestion ! >>>NO saupport e-mail. NO support phone ? What am I supposed to do ? >> >>I would suggest that you try http://support.xilinx.com Right at the >>top you will see a tab labeled "Contact Support" where you can follow >>the links to file a WebCase on your issue or to get the phone number >>for technical support as well. >> >>In additional to our official support channels we also monitored this >>newsgroup for issues. To claim that Xilinx does not offer any customer >>support is a bit of hyperbole. > > > No, it's not. I have tried to register with Xilinx support, but I got a > reply that stated that since I was not an employe , but only a student, I > could not get direct support. > > May be there is some part of "You can not join" that I did not understand ? > >Article: 103763
Spending Real money for a product makes you a customer (not a student). As such, open a webcase. It really isn't that hard, is it? We only get tens of thousands of cases opened each month. Austin John Smith wrote: > "Austin Lesea" <austin@xilinx.com> wrote in message > news:e6cs9c$7bn18@xco-news.xilinx.com... > >>John, >> >>It is listed as out of stock. >> >>How does that equate to discontinued? > >>I think I missed something. >> >>Austin > > > Well, Austin deare, I did not meen to be rude, but when I buy hardware for > about $400, it would be very nice to have an e-mail address to post simple > questions, an get some answers to. Thats not to much to ask for. > > It's kind'a like the ultimatium the US ambassador in Norway has given us: > Either you are with us, or you are against us ! (He IS a fool !) > > I would not put it quite like that, I would say; I you dont offer propper > support, you will loose me as a customer. Maybe you'll regret that some > time. Remenber the first days of The Beatles ? > > I'll always manage. I'll just switch to one of Xilinxs competitors. > >Article: 103764
[crossposted because it's about Xilinx S/W, I'm running Slackware, and
s.e.d is where all the really smart people hang out...]
OK, I decided to take a chance and download that 839MB shell script that's
written for RedHat Enterprise, and was doing OK, (I had to shell out as
root a couple of times to give the install script permission to write to a
new directory, but that felt kind of kewl. :-) ), and now I'm at kind of a
stopper. The graphic install has the progress bar at 99%, and there's a
white-X-in-the-red-circle error message: Error: Cannot run process -
/usr/local/richgrise/Xilinx/.xinstall/install_driverscript
while simultaneously, the Konsole where I invoked it says:
------<quote>------
richgrise@thunderbird:~/L/Downloads/Xilinx_Webpack_8.1i_Webpack $
WebPACK_81i_SFD.sh
Verifying archive integrity... All good. Uncompressing Xilinx ISE WebPACK
Installer.....................................................................................................................................................................................................
/lib/modules/misc/windrvr6.o: kernel-module version mismatch
/lib/modules/misc/windrvr6.o was compiled for kernel version
2.4.18-14 while this kernel is version 2.4.31.
------</quote>------
and the console is patiently waiting (no prompt), and the error dialog box
is patiently waiting for me to click "OK".
So, I wonder, is there some way to spoof Xilinx ISE for Red Hat Enterprise
into thinking that I have the older kernel? Or, maybe (yah, right) that
Xilinx guy who shows up from time to time on comp.arch.fpga might have
some suggestion. :-)
Frankly, I'm kinda surprised that it's gotten as far as it has, running a
Red Hat Enterprise script on a plain vanilla Slackware box. :-) That's
Slackware 10.2, basically right out of the box; and the "Single File
Install" at Xilinx:
http://www.xilinx.com/ise/logic_design_prod/webpack.htm
So, back to the question, can I spoof it? Or get enough source code to
recompile and relink it? I certainly don't want to try to install a
different kernel - that's WAY beyond my scope of "expertise". ;-)
Thanks!
Rich
Article: 103765On Sat, 10 Jun 2006 19:15:57 +0000, Rich Grise wrote: > [crossposted because it's about Xilinx S/W, I'm running Slackware, and > s.e.d is where all the really smart people hang out...] [continuing to crosspost, because I'm a kind of annoying fellow...] > > OK, I decided to take a chance and download that 839MB shell script that's [written for Red Hat Blah blah...] So, now, I'm wondering, how in the heck do they include a whole installable package in a shell script? Binary here documents? Thanks, RichArticle: 103766
John Smith wrote: > > > > Have you tried searching on the Xilinx website. I was able to find: > > > > http://www.xilinx.com/products/boards/sp305/reference_designs.htm > > > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SP305-US&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=BOARDS > > > > Between the two, there are reference designs (with working UCF files), > > schematics, and a user guide. > > > > Well, I've checked it out now, and I have downloaded all this stuff before, > so nothing new. In fact, I had to make my own "master" UCF-file for this > board. Maybe there are some hidden treasures in the EDK files, but I'm only > using ISE. > > And Xilinx does not offer any customer support either. > > Not a good way to treat future customers. What exactly are you trying to learn beyond what can be gleaned from the datasheets and schematics? If you have the schematics, then you can create the UCF. You also have the part numbers for all the board devices, so you can download the datasheets if they aren't included. >From there, you really don't need anything else for ISE. (EDK may be a different story, but I haven't messed with that yet) I wrote my own UCF for the Spartan 3E "sample pack" board, which admittedly isn't as complex as the board you have, but it's not difficult. This was my first experience with Xilinx devices, so I had a few problems with the UCF format (specifically, forgetting to put 'p' in front of the pin numbers) but I was able to get a working top-level VHDL and UCF files pretty quick. Besides, I find going through the schematics to be helpful anyway. It gets you familiar with the parts on the board, how they are connected, and any limitations or gotcha's. For example, I discovered that 2 of the 8 signal lines for MA1-DATA bus on the Spartan 3E sample pack boards are INPUT ONLY! (Who knows what the designers were thinking when there are exactly two unused GPIO lines left unused on the board...) I also discovered that the upper 8 bits of the 16-bit FLASH data bus are input-only as well. Now that I know that, I can make better decisions about I/O mapping.Article: 103767
Rich Grise <richgrise@example.net> wrote: >[crossposted because it's about Xilinx S/W, I'm running Slackware, and >s.e.d is where all the really smart people hang out...] > >OK, I decided to take a chance and download that 839MB shell script that's >written for RedHat Enterprise, and was doing OK, (I had to shell out as >root a couple of times to give the install script permission to write to a >new directory, but that felt kind of kewl. :-) ), and now I'm at kind of a >stopper. The graphic install has the progress bar at 99%, and there's a >white-X-in-the-red-circle error message: Error: Cannot run process - >/usr/local/richgrise/Xilinx/.xinstall/install_driverscript >while simultaneously, the Konsole where I invoked it says: >------<quote>------ >richgrise@thunderbird:~/L/Downloads/Xilinx_Webpack_8.1i_Webpack $ >WebPACK_81i_SFD.sh >Verifying archive integrity... All good. Uncompressing Xilinx ISE WebPACK >Installer..................................................................................................................................................................................................... >/lib/modules/misc/windrvr6.o: kernel-module version mismatch > /lib/modules/misc/windrvr6.o was compiled for kernel version > 2.4.18-14 while this kernel is version 2.4.31. >------</quote>------ >and the console is patiently waiting (no prompt), and the error dialog box >is patiently waiting for me to click "OK". > >So, I wonder, is there some way to spoof Xilinx ISE for Red Hat Enterprise >into thinking that I have the older kernel? Or, maybe (yah, right) that >Xilinx guy who shows up from time to time on comp.arch.fpga might have >some suggestion. :-) > >So, back to the question, can I spoof it? Or get enough source code to >recompile and relink it? I certainly don't want to try to install a >different kernel - that's WAY beyond my scope of "expertise". ;-) I think there is an option in the kernel which allows you to turn this check off. But this will need a recompilation of the kernel. By changing some defines, you can have the 2.4.18-14 kernel compile as a 2.4.31 version. Still, there may be differences in the kernel which make the software written for the 2.4.31 version incompatible with version 2.4.18. Somehow Linux developers don't seem to care a bit about backwards compatibility which makes maintaining Linux software a real pain in the ass. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 103768
"Austin Lesea" <austin@xilinx.com> wrote in message news:e6f0m5$7bn19@xco-news.xilinx.com... > John, > > Students are being supported through the webcase email system, as our > No phones for students (what I was told, but maybe that changed. Xilinx can't be that stupid, so I am still looking for a support e.mail adress for students.Article: 103769
"radarman" <jshamlet@gmail.com> wrote in message news:1149973082.570326.86310@i40g2000cwc.googlegroups.com... > John Smith wrote: > > > > > > Have you tried searching on the Xilinx website. I was able to find: > > > > > > http://www.xilinx.com/products/boards/sp305/reference_designs.htm > > > > > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SP305-US&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=BOARDS > > > > > > Between the two, there are reference designs (with working UCF files), > > > schematics, and a user guide. > > > > > > > Well, I've checked it out now, and I have downloaded all this stuff before, > > so nothing new. In fact, I had to make my own "master" UCF-file for this > > board. Maybe there are some hidden treasures in the EDK files, but I'm only > > using ISE. > > > > And Xilinx does not offer any customer support either. > > > > Not a good way to treat future customers. > > What exactly are you trying to learn beyond what can be gleaned from > the datasheets and schematics? If you have the schematics, then you can > create the UCF. You also have the part numbers for all the board > devices, so you can download the datasheets if they aren't included. > >From there, you really don't need anything else for ISE. (EDK may be a > different story, but I haven't messed with that yet) > > I wrote my own UCF for the Spartan 3E "sample pack" board, which > admittedly isn't as complex as the board you have, but it's not > difficult. This was my first experience with Xilinx devices, so I had a > few problems with the UCF format (specifically, forgetting to put 'p' > in front of the pin numbers) but I was able to get a working top-level > VHDL and UCF files pretty quick. > > Besides, I find going through the schematics to be helpful anyway. It > gets you familiar with the parts on the board, how they are connected, > and any limitations or gotcha's. For example, I discovered that 2 of > the 8 signal lines for MA1-DATA bus on the Spartan 3E sample pack > boards are INPUT ONLY! (Who knows what the designers were thinking when > there are exactly two unused GPIO lines left unused on the board...) I > also discovered that the upper 8 bits of the 16-bit FLASH data bus are > input-only as well. > I totally agree with you ! I have gone throug all of that, but there is an error in the schematics. And there is now way I can get support on this issue, no email support, noe phone support.. I am totally pissed off by Xilinx, if they dont straighten up i'll cut them lose and left them drift away..forever.Article: 103770
"Austin Lesea" <austin@xilinx.com> wrote in message news:e6f0pr$7bn20@xco-news.xilinx.com... > Spending Real money for a product makes you a customer (not a student). Well, $400 is real money for me, I guess like $400 000 is real money for you ? Im Sorry, I dont have that kind of money.... If you dont wish to support individual customers,you should not engage in the retail end of the market. Its as simple as that-you make great chips but you dont understand the retail business. I expect to see some improvement in your coustumers service soon. here is an example of what your homepage should looke like : http://www.msi.com.tw/ Youve got a long way to go, miss Lesea.Article: 103771
John Smith wrote: <snip> > > I totally agree with you ! I have gone throug all of that, but there is an > error in the schematics. Here is a tip : provide information and you will get information back. Spit the dummy, and you will get ignored... > And there is now way I can get support on this > issue, no email support, noe phone support.. Well, others seem able to get answers to questions ? perhaps, you should work on your skills, and not throw the toys out of your cot ? In engineering, you _are_ going to need the skill of getting information you require, and a rant is counter-productive - or do you not plan employment in engineering ? > I am totally pissed off by > Xilinx, if they dont straighten up i'll cut them lose and left them drift > away..forever. and the point of that rant is what, exactly ? If you have a specific issue, like an error in a schematic, point that out, and it will likely be corrected. <paste> > If you dont wish to support individual customers,you should not engage in > the retail end of the market. Its as simple as that-you make great chips but > you dont understand the retail business. Xilinx are not engaged in the retail end of the market. Their customers are designers and engineers. Walmart is a retailer. > > I expect to see some improvement in your coustumers service soon. > here is an example of what your homepage should looke like : > > http://www.msi.com.tw/ Hmm, well, _that_ is a shocker of a web site - all froth, and no substance. I hope Xilinx do NOT copy that. -jgArticle: 103772
John, I have taken a new direction: when insulted, ignored, and railed against unjustly when all I offered was help, I press "ignore" so that I never have to experience your unhappy existence, again. I can not solve all the world's problems, and I must accept there are those who are so intent on being miserable, and causing others pain, that I can have no positive influence whatsoever. Good luck. (Mr) Austin Lesea John Smith wrote: > "Austin Lesea" <austin@xilinx.com> wrote in message > news:e6f0pr$7bn20@xco-news.xilinx.com... > >>Spending Real money for a product makes you a customer (not a student). > > Well, $400 is real money for me, I guess like $400 000 is real money for > you ? > Im Sorry, I dont have that kind of money.... > > If you dont wish to support individual customers,you should not engage in > the retail end of the market. Its as simple as that-you make great chips but > you dont understand the retail business. > > I expect to see some improvement in your coustumers service soon. > here is an example of what your homepage should looke like : > > http://www.msi.com.tw/ > > > Youve got a long way to go, miss Lesea. > >Article: 103773
Rich Grise wrote: > On Sat, 10 Jun 2006 19:15:57 +0000, Rich Grise wrote: >> [crossposted because it's about Xilinx S/W, I'm running Slackware, and >> s.e.d is where all the really smart people hang out...] > [continuing to crosspost, because I'm a kind of annoying fellow...] >> >> OK, I decided to take a chance and download that 839MB shell script that's > [written for Red Hat Blah blah...] > > So, now, I'm wondering, how in the heck do they include a whole installable > package in a shell script? Binary here documents? > Nvidia does the same thing with their binary-only drivers, the binary is included as part of one giant shell script. Perhaps you could even modify it if you used an 8-bit clean editor...Article: 103774
jaxato@gmail.com wrote: > Hi, > > Both the T65 from Opencores and Free6502 from the Free-Ip Project (its > been a while that the guy took it offline, but you can still get it > from fpgaarcade) are stable and rather small in terms of logic > resources (30% of xc3s200). We have used them in a good five projects. > Each one has their own pros and cons. The T65 has a well defined > synchronous interface but tries to mimic the real 6502, signals are > inverted and so on. The free6502 on the other hand, has a good > interface too but lacks a ready input signal. For people that wants to > run it at maximum speed (around 40 MHZ, 10 mips), its tricky to make it > go into wait states (to handle slower peripherals like an RTL8019AS > chip), while the T65 has that mechanism and will allow itself to be > idle... > > In all, both are very usable and well-defined soft processors suitable > for FPGA implementation. > > Jacques > > www.design4fpga.com > FYI - the T65 from opencores has known bugs. For example ADC (),Y is broken. You would be better off getting the T65 from fpgaarcade (http://home.freeuk.com/fpgaarcade/library.htm) where this and some other issues have been addressed. I don't know why the opencores version hasn't been fixed yet. Maybe the author lost interest in it. I'm pretty sure that the free6502 (now only available at http://www.sprow.co.uk/fpgas/free6502.htm - maybe you were thinking of the patched T65 at fpgaarcade?) has problems. I didn't track down the exact issue, but if you whip together an Apple 1 like system (we're talking a few hours work here if you substitute a UART for the video/keyboard interface) and run integer basic then try running a basic program like Hammurabi from the Replica1 site, and you'll see that it has problems. Just too much trouble to track down the problem. It's an interesting core, so would be nice to see it fixed. Another possibility is the core at http://www.syntiac.com/fpga64.html which seemed to work well in my limited testing. (The BusCycles feature is a little different - I guess that this came from the VIC/C64 world.) The main problem is that none of these cores include documentation or verification suites. I would plan on being able to switch different cores in and out if you run into problems. Kind of a pain since they are all a little different, but might save pain during development. Regards, Keith
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