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Messages from 104250

Article: 104250
Subject: Re: Xilinx ISE S/W Install kernel version "mismatch"
From: Rich Grise <richgrise@example.net>
Date: Wed, 21 Jun 2006 21:56:19 GMT
Links: << >>  << T >>  << A >>
On Tue, 20 Jun 2006 06:14:25 +0000, Adam Goldman wrote:

> In article <pan.2006.06.11.03.15.36.415791@example.net>, Rich Grise wrote:
>>OK, I decided to take a chance and download that 839MB shell script that's
>>written for RedHat Enterprise, and was doing OK, (I had to shell out as
>>root a couple of times to give the install script permission to write to a
>>new directory, but that felt kind of kewl. :-) ), and now I'm at kind of a
>>stopper. The graphic install has the progress bar at 99%, and there's a
> 
>>/lib/modules/misc/windrvr6.o: kernel-module version mismatch
>>        /lib/modules/misc/windrvr6.o was compiled for kernel version
>>        2.4.18-14 while this kernel is version 2.4.31.
> 
> Not specifically for your distribution but here's something on recompiling
> xpc4drvr and windrvr6 for a different kernel:
> 
> http://gentoo-wiki.com/HOWTO_Xilinx
> 
> It looks to me as if unless you're using their programmer hardware you
> don't need to bother. Synthesis and schematic capture ought to work without
> this driver.
> 
> Coincidentally, Xilinx mailed out my copy of ISE today, so I'll know
> soon enough ;-)
> 

Thanks, but that link only talks about kernel 2.6, but Slackware ships
with 2.4, and 2.6 is an option, that I've been afraid to try. ("Compile
a new kernel????? Are you nuts?"

Thanks!
Rich



Article: 104251
Subject: Re: Xilinx ISE S/W Install kernel version "mismatch"
From: Duane Clark <junkmail@junkmail.com>
Date: Wed, 21 Jun 2006 23:17:30 GMT
Links: << >>  << T >>  << A >>
Rich Grise wrote:
> On Tue, 20 Jun 2006 06:14:25 +0000, Adam Goldman wrote:
> 
>> In article <pan.2006.06.11.03.15.36.415791@example.net>, Rich Grise wrote:
>>> OK, I decided to take a chance and download that 839MB shell script that's
>>> written for RedHat Enterprise, and was doing OK, (I had to shell out as
>>> root a couple of times to give the install script permission to write to a
>>> new directory, but that felt kind of kewl. :-) ), and now I'm at kind of a
>>> stopper. The graphic install has the progress bar at 99%, and there's a
>>> /lib/modules/misc/windrvr6.o: kernel-module version mismatch
>>>        /lib/modules/misc/windrvr6.o was compiled for kernel version
>>>        2.4.18-14 while this kernel is version 2.4.31.
>> Not specifically for your distribution but here's something on recompiling
>> xpc4drvr and windrvr6 for a different kernel:
>>
>> http://gentoo-wiki.com/HOWTO_Xilinx
>>
>> It looks to me as if unless you're using their programmer hardware you
>> don't need to bother. Synthesis and schematic capture ought to work without
>> this driver.
>>
>> Coincidentally, Xilinx mailed out my copy of ISE today, so I'll know
>> soon enough ;-)
>>
> 
> Thanks, but that link only talks about kernel 2.6, but Slackware ships
> with 2.4, and 2.6 is an option, that I've been afraid to try. ("Compile
> a new kernel????? Are you nuts?"
> 

Do you want to use the Xilinx programming tools (impact)? If not, you 
don't need those two drivers, as Adam said.

If you do want to use those tools, then Xilinx requires that you 
recompile the drivers against your kernel, if you are using a kernel 
different from the one the compiled against. Kind of annoying, and 
hopefully one of these days Xilinx will do it right.

If you have not recompiled your own kernel, then you probably just need 
to install the kernel sources corresponding to the kernel you have, and 
compile the drivers. I don't use Slackware, so I don't know how it is 
done there. I see that this is crossposted to alt.os.linux.slackware, so 
someone there could probably help with that.

Article: 104252
Subject: Re: Linking/mapping code sections with Xilinx EDK
From: "Joseph" <joeylrios@gmail.com>
Date: 21 Jun 2006 21:47:56 -0700
Links: << >>  << T >>  << A >>
Steve,

That .s/.S proprocessor thing is a feature (.S signals gcc to use the
preprocessor, .s tells it not to use the CPP).  Assuming all the
linkers and such are right (I am not an expert on this by any means),
I'd wonder how you are actually compiling and linking.  How are you
calling the tools?  Do you have a makefile?  Maybe the .S isn't getting
into the action with your makefile?

Joey

sgfallows@gmail.com wrote:
> I'm using a V2Pro based eval board with a simple set of frimware and
> software files. The software set includes the Xvectors.S file from the
> EDK library and I want/expect the code in the xvectors.S file to be
> loaded into memory with the image.
>
> The vector code is in section .vectors, which is mapped by the linker
> script to 0xFFFF0000. However the map file shows zero length for the
> section and the debugger confirms that what is loaded there is the next
> section after the .vectors section.
>
> map file snippet:
>
> .vectors        0xffff0000        0x0
>                 0xffff0000                __vectors_start = .
>  *(.vectors)
>                 0xffff0000                __vectors_end = .
>
> linker script snippet:
>
> .vectors : {
>    __vectors_start = .;
>    *(.vectors)
>    __vectors_end = .;
> } > plb_bram_if_cntlr_1
>
>
> xvectors.S file snippet:
>
> 	.section .vectors,"ax"
>
> 	.globl	_vectorbase
>
> _vectorbase:
> 	// Vector 0x0000, Jump to zero.
> 	critical_interrupt 0000, 0
>
> 	// Vector 0x0100, Critical interrupt.
> 	critical_interrupt 0100, 1
>
> It all looks right to me. I must be missing something. I've tried lots
> of name/case/quoting changes. I can't get the code for the vectors
> (expanded macro 'critical_interrupt" etc.) to be loaded in memory no
> matter what I do. Even messed with the case of the .s file extension
> which very bizarrely (to me anyway) changes whether the C preprocessor
> is invoked.
> 
> Any clues or ideas??
> Thanks
> Steve


Article: 104253
Subject: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 21 Jun 2006 21:59:37 -0700
Links: << >>  << T >>  << A >>
Yes, we support "channel bonding", which means we can use four
transceivers, each at 2.5/3.125 Gbps to operate with a throughput of 10
Gbps. But it involve four transceivers and four physical connections.
I think Vivek's question was whether the four channels can be combined
to one.
Physical the answer is "NO". Virtual the answer is "YES", through
channel bonding.
Peter Alfke

==========
Falk Brunner wrote:
> Vivek Menon schrieb:
> > Hi Sean,
> > Can you please elaborate on Virtex-II Pro X and the technique to
> > combine 4x2.5 Gbit/sec into 10 Gbit/sec?
>
> Very simple. The key word is channel bonding. This is done every day in
> the 10G XAUI interfaces. So the idea is not new and it is doable without
> too much trouble.
>
> Regards
> Falk
> 
> P.S. The 4x2.5G is 4x3.125G due to 8B10B coding.


Article: 104254
Subject: Re: FSM State Minimization on FPGAs
From: backhus <nix@nirgends.xyz>
Date: Thu, 22 Jun 2006 08:15:20 +0200
Links: << >>  << T >>  << A >>
Hi Andy,
as already said by John, it's not done in a single pass.

A simple explanation can be found here
(regardless of the typo on p.4: read "SZ and SY"):
http://web.cecs.pdx.edu/~mperkows/temp/021.Introduction-state-minimization-complete.pdf

A more scientific approach can be found here:
http://av.rds.yahoo.com/_ylt=A9ibyK.OMZpEXW4AhZSTLaMX;_ylu=X3oDMTBvdmM3bGlxBHBndANhdl93ZWJfcmVzdWx0BHNlYwNzcg--/SIG=12a31utog/EXP=1151042318/**http%3a//web.cecs.pdx.edu/%7ealanmi/510FM2/510OCE-11.ppt

While the first paper can be understood and applied even by 
undergraduates, the second one is very theoretical.

Funny coincidence: both explain the rule for equivalent states on p.4 :-)


Best regards

    Eilert


Andy schrieb:
> I'm not sure I understand how your simplified state table optimization
> is going to find identical sequences of states, since the individual
> states do not have identical from's and to's compared to any other
> individual states, but the sequence as a whole may be identical to
> another sequence as a whole.  It seems to me that this is where the
> most redundant states are going to be found. In software, they usually
> write these identical sequences as subroutines, perhaps we should focus
> on the same, and use sub-state-machines.



Article: 104255
Subject: Re: xst can, but vcomp can't
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Thu, 22 Jun 2006 08:45:06 +0200
Links: << >>  << T >>  << A >>

"Ralf Hildebrandt" <Ralf-Hildebrandt@gmx.de> wrote in message 
news:4ft3joF1joptjU1@individual.net...
> Morten Leikvoll wrote:
>
>> Error from vcom: Attribute "event" requires a static signal prefix.
>> Xst handles this very nice..
>
> Synthesis with Synopsys DC is even worse. It does not even allow
>
> my_gen: if N in 0 to 7 generate
> ...
> if rising_edge(clock_vector(N)) then
> ...
> end generate;
>
.....
> You could select the clock-signal out of the vector before calling the 
> procedure. Then you feed only the selected signal to the procedure.
...
> Hmm ... dual-edge behavior? Do you want to model synthesizable code? Have 
> a look at http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf 
> if you really need it and want to be independent from the tools.
>
>
> Ralf

Looks like an idea.. Can I call a procedure from another procedure? In that 
case I can try write a new procedure to extract the bit and pass it (as 
inout?) to a clock detecting procedure using a clean bit. Hmm.. not sure if 
that will work tho.. Gotta try it.
I am not really trying to use dual edge here. I only want to program my 
cpu_register to be able to detect a rising of falling edge from my system 
depending on a constant input parameter (here, the input variable 'neg').
Thanks for suggestion and the interesting article :)



Article: 104256
Subject: Re: Locks for the peasants :-)
From: backhus <nix@nirgends.xyz>
Date: Thu, 22 Jun 2006 08:58:10 +0200
Links: << >>  << T >>  << A >>
Hi Austin,
that sounds reasonable. Security proofs are expensive.

For the V2 boards you gave away ... what reward did you offer in case of 
success? I suspect there are people out there who would pay good for 
that knowledge as long as you don't have it, so why should they tell 
you? ;-)

Best regards
   Eilert

Austin Lesea schrieb:
> backhus,
> 
> That is something that we thought about.  But, really what we talking
> about is providing access to the crypto-engine through the general
> interconnect, and control of that engine.
> 
> It was considered that anything we do in this regard would have to be
> completely and thoroughly tested so as not to be a back door, and
> compromise security.
> 
> It wasn't worth the work to have to prove we did not break something.

Article: 104257
Subject: Re: FSM State Minimization on FPGAs
From: fpga_toys@yahoo.com
Date: 22 Jun 2006 00:10:26 -0700
Links: << >>  << T >>  << A >>

Phil Hays wrote:
> As an example, suppose I was designing for 4-input LUTs, and I had two
> input states, and two condition bits for a state.  One-hot is assumed.
> The input logic to state3 would be:
>
> state3 :: (state1, state2, (state3, c1, c2))
>
> This is five inputs, which would require two levels of logic with
> 4-LUTs.  I could improve speed by splitting state 3 into two states,
> state3a and state3b:
>
> state3a :: (state1, (state3a, c1, c2))
> state3b :: (state2, (state3b, c1, c2))
>
> Any output equations and next state equations would have state3
> replaced with (state3a or state3b).  A "state minimization feature"
> would collapse these states back into state3, making the FPGA run
> slower.

Since One-Hot is assumed, there probably isn't a significant time
penalty for carefully packing a slice using an F5 mux to build a
5-input LUT, or using the carry mux and Cin for some cases, both of
which avoid the routing/switch box delays, with a small mux delay
instead. If only the tools did that automatically for performance, or
allowed it easily by hand.


Article: 104258
Subject: Re: keys to the Kingdom
From: "Thomas Stanka" <usenet_10@stanka-web.de>
Date: 22 Jun 2006 00:13:50 -0700
Links: << >>  << T >>  << A >>
Hi,

Austin Lesea schrieb:

> Just don't go advertising them to be more than they really are:  a
> convenient way to make it cost at least $5,000 to find the key.

Is it that cheap today to open the die and observe the fuses?
I have no idea, if (and how) Altera protected the key fuses against
optical inspection of die  cuts. But If your right, it would be very
cheap to reengineer most Asics.

BTW Am I right, that if I use a Xilinx with security inside a
equipment, the chip could be highjacked (Chipmodded) by just removing
the power supply of the keys and applieing a new bitstream?
Which means the bitstream itself may be protected, but not the chip?
Why did nobody combine software and fuse based technologies? It would
be sufficient to have 128 bit (with secure algorithms) in SW and 128 in
fuses. 

bye Thomas


Article: 104259
Subject: Re: comp.arch.fpga : Selection of Device
From: Kolja Sulimma <news@sulimma.de>
Date: Thu, 22 Jun 2006 10:11:48 +0200
Links: << >>  << T >>  << A >>
Pravin G schrieb:
> Hi all,
> 
> We want to implement a design in a spartan - 3. and select a device (in terms of system gates) at the initial stage of the project. 
> Is there any method for this.

Ask the designer who will implement the design for an estimate. (If s/he
has a boss, ask the boss)
There really is no other way because it is not uncommon to have a
factor of 10 in LUT count between FPGA designers.

For example I just saw a design that used 90% of the area for a huge mux
that allowed to read back all parameter registers. Using a shift
register instead or getting rid of the readback requirement would
improve area 10x.

Sometimes there are obvious limits as Peter suggested: The number of
I/Os, number of BRAMs, number of multipliers. But LUT count is
impossible to predict without knowing the engineer.

Kolja Sulimma


Article: 104260
Subject: Re: Detachable Virtex-II Pro/Virtex-4 FX module with Rocket I/O
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Thu, 22 Jun 2006 10:28:56 +0100
Links: << >>  << T >>  << A >>
Vivek

We have some V2Pro designs that we have done that might be adapted and some 
plans on the V4 side that might be close to what you want. Not for public 
consumption at present but we can talk about what you need offline. Use any 
of the public email addresses on our website and make it for my attention 
and it will be passed to me.

John Adair
Enterpoint Ltd. - Home of Hollybush1. The PC104+ Solution.
http://www.enterpoint.co.uk


"Vivek Menon" <vivek.menon79@gmail.com> wrote in message 
news:1150913001.916921.156290@m73g2000cwd.googlegroups.com...
> Hi,
> I am searching for a detachable Virtex-II Pro or a Virtex-4 FX series
> FPGA with rocket I?O capability. I do not want a huge evaluation board.
> After I program the FPGA and the Rocket I/O, I need to detach the
> board/mini-module.
> Please let me know if you are aware of such mini-modules.
> Thanks,
> Vivek
> 



Article: 104261
Subject: Xilinx Library Conversion
From: "dougeh" <DanielJDouglas@gmail.com>
Date: 22 Jun 2006 02:49:08 -0700
Links: << >>  << T >>  << A >>
Hi All,

My Goal is to use some librarys I have for Xilinx ISE 8.1 with Cadence.

The way I thought of going about this is to *somehow* export the
library to EDIF and then import that EDIF to Cadence, having them in
EDIF will also hopefully solve this headache if I need to use them
somewhere else at a different time.

Has anyone done something similar to this before, or could anyone give
me some pointers. I have little to no experiance at this, I was looking
at possibly writing a perl script to read from the library and create
the EDIFs.

Thanks

Doug


Article: 104262
Subject: Newbie in Chipscope-changes need to route bidirectional data port
From: "subint" <subin.82@gmail.com>
Date: 22 Jun 2006 03:20:43 -0700
Links: << >>  << T >>  << A >>
Hi,
I am using the chipshop first time. I am using this one to debug my ddr
controller in the v4 board. When i tried to route the data bus of ddr
through the chipscope it generated ILA and inserted into my design but
when i try to implement(map and par) xilinx ise showing error that the
bidirectional port is being driven by some buffer by the chipscope
module.the ddr bus are  bidirectional so what changes needed in the
chipscope setting to route my bidirectional port.
regard
subin


Article: 104263
Subject: Remote access to Altera FPGA via jtagd in Linux
From: Wojciech Zabolotny <wzab@mail.cern.ch>
Date: Thu, 22 Jun 2006 13:16:58 +0200
Links: << >>  << T >>  << A >>
Hi All,

I just needed to program and debug my Altera FPGAs remotely.
So I've prepared a small script on the remote machine:

#!/bin/bash
killall jtagd
killall jtagd
sleep 1
echo I have killed the old server
export PATH=/home/me/quartus/bin:$PATH
sudo rmmod ppdev
echo I have removed the ppdev driver
sleep 2
sudo modprobe ppdev
echo I've lodaed the ppdev driver
sleep 2
jtagd
echo I have run jtagd server
sleep 4
echo Started server configuration
jtagconfig --remove 1
jtagconfig --add byteblastermv lpt1
jtagconfig --enableremote my_password
jtagconfig

Unfortunately the last command outputs the following:

1) ByteBlasterMV [/dev/parport0]
  0100A0DD !
  020030DD !
  0100A0DD !
  020030DD !

  Captured DR after reset = (0100A0DD020030DD0100A0DD020030DD) [128]
  Captured IR after reset = (5455554555) [40]

So the jtagd does not recognize the chips (probably it doesn't read the 
pgm_parts.txt file, when run in this mode)
However the server is running and ready:

$netstat -l -t -p
Proto Recv-Q Send-Q Local Address           Foreign Address         State 
PID/Program name
[...]
tcp        0      0 *:1309                  *:*                     LISTEN     
5444/jtagd
[...]

When I run the jtagd with --user-start option (adding it in the proper 
line of the script),
it correctly recognizes chips, but fails to enable remote access:

Started server configuration
Error (Unknown error) when setting password
1) ByteBlasterMV [/dev/parport0]
  0100A0DD   EPC16/4/8
  020030DD   EP1S25/_HARDCOPY_FPGA_PROTOTYPE
  0100A0DD   EPC16/4/8
  020030DD   EP1S25/_HARDCOPY_FPGA_PROTOTYPE

now netstat returns:
$ netstat -l -t -p
Proto Recv-Q Send-Q Local Address           Foreign Address         State 
PID/Program name
[...]
tcp        0      0 localhost:1309          *:*                     LISTEN     
5767/jtagd
[...]

So jtagd listens only on the local machine.
I tried to use ssh tunneling:

ssh user@remote.machine -L1309:localhost:1309

But then the local jtagd may not start, as 1309 port is occupied.
Finally I've the solution, using the extended version of SSH tunneling:

ssh user@remote.machine -Laaa.bbb.ccc.ddd:1309:localhost:1309
(aaa.bbb.ccc.ddd - is the IP of my local machine, you can also 
create a fake additional IP with "ifconfig eth0:1 aaa.bbb.ccc.ddd up" 
using an unrouteable IP)

Now the local jtagd connects to the localhost 1309 port, while tunneled
remote jtagd listens on the aaa.bbb.ccc.ddd 1309 port.
If you now locally run
$ qrt_path/jtagd --user-start
$ qrt_path/jtagconfig --addserver aaa.bbb.ccc.ddd e
("e" is a dummy password, not used, but needed)
$ qrt_path/bin/jtagconfig
1) ByteBlasterMV on aaa.bbb.ccc.ddd [/dev/parport0]
  0100A0DD   EPC16/4/8
  020030DD   EP1S25/_HARDCOPY_FPGA_PROTOTYPE
  0100A0DD   EPC16/4/8
  020030DD   EP1S25/_HARDCOPY_FPGA_PROTOTYPE

BTW This method should provide better security. I know nothing about
the security of Altera remote jtagd protocol.
It seems (from ethereal dumps) that it doesn't send passwords
as plaintext, but I don't know how easy it is to break.
In the above method you connect via the proven SSH protocol.

So my final script "~/jtagstart" looks like this:

#!/bin/bash
killall jtagd
killall jtagd
sleep 1
echo I have killed the old server
export PATH=/home/me/quartus/bin:$PATH
sudo rmmod ppdev
echo I have removed the ppdev driver
sleep 2
sudo modprobe ppdev
echo I have lodaed the ppdev driver
sleep 2
jtagd --user-start
echo I have run jtagd server
sleep 4
echo Started server configuration
jtagconfig --remove 1
jtagconfig --add byteblastermv lpt1
jtagconfig

You should run on the local machine:
$ssh me@remote.machine -Laaa.bbb.ccc.ddd:1309:localhost:1309  
/home/me/jtagstart
and then locally:
$ qrt_path/jtagd --user-start
$ qrt_path/jtagconfig --addserver aaa.bbb.ccc.ddd e

Works like a dream :-).

HTH & Regards
Wojtek Zabolotny


Article: 104264
Subject: Re: Spartan-3 starter kit strange problem
From: "jmariano" <jmariano@ualg.pt>
Date: 22 Jun 2006 04:43:00 -0700
Links: << >>  << T >>  << A >>
Hello Siva,

Tank you very much for your help. I managed to solve the problem with
the help Rob
Barris, who reply to the same message posted elsewhere. It turns out
that the origin of
the problem was the unconnected nets. After I connected all the nets to
pins on the FPGA,
the problem disappeared.

Regards

Mariano


Article: 104265
Subject: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
From: Kolja Sulimma <news@sulimma.de>
Date: Thu, 22 Jun 2006 14:12:15 +0200
Links: << >>  << T >>  << A >>
Fred schrieb:
> Does anyone know of any software, ideally freeware, which can use the above 
> JTAG interfaces to exercise other JTAG interfaces on non FPGA devices?
> 
> In my case I'd like to read the state of pins on an unrelated device.

There is JTAG code in the not very active open source project "open wince".

Kolja

Article: 104266
Subject: One significant correction: Remote access to Altera FPGA via jtagd
From: Wojciech Zabolotny <wzab@mail.cern.ch>
Date: Thu, 22 Jun 2006 14:23:50 +0200
Links: << >>  << T >>  << A >>
In the script from the previous post, when script finishes, the tunnel 
disappears and connection is broken :-(.
So you either must ssh to the command prompt:

$ssh my@remote.machine -Laaa.bbb.ccc.ddd:1309:localhost:1309

and then run the jtagstart manually:

$./jtagstart

The session will be active until you logout with exit.
Or you should add a never ending loop at the end of the script,
e.g. like this:
while true; do
  echo tunnel active
  sleep 1m
done

-- 
Sorry for confusion,
wojtek


Article: 104267
Subject: Re: xc3sprog -- any updates?
From: "Sandro" <sdroamt@netscape.net>
Date: 22 Jun 2006 05:27:22 -0700
Links: << >>  << T >>  << A >>
Eric wrote:
>
> They created it this afternoon; it should be up! I'm going to import
> the original code into svn right now...
>      ...Eric

Eric,
Great... I saw the version you uploaded is slightly different than
the version I worked on!
I'll check how my changes apply to your version and after
i'll send you!

bye
Sandro


Article: 104268
Subject: newbie:my ISE doesn't include old xcs30 spartan how........
From: "blisca" <blisca@tiscali.it>
Date: Thu, 22 Jun 2006 14:01:26 +0100
Links: << >>  << T >>  << A >>
how can i do to make it work with this old devices?experimenting with an old
board i need to add xcs30 and i need a tool(older impact versions) for
programming it,i guess that treatin it as an xc2s30 is not the right way to
proceed
Thanks to everyone
Diego



Article: 104269
Subject: Re: newbie:my ISE doesn't include old xcs30 spartan how........
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Thu, 22 Jun 2006 14:11:49 +0100
Links: << >>  << T >>  << A >>
Diego,
these parts are dinosaurs, the last version of the tools to support 
4K/spartan was ISE4.1 (maybe 4.2 but I'm not sure) you can still 
download tools from www.xilinx.com for old parts.
I don't have a link handy, but is straightforward to find them on xilinx.com
Aurash
blisca wrote:

>how can i do to make it work with this old devices?experimenting with an old
>board i need to add xcs30 and i need a tool(older impact versions) for
>programming it,i guess that treatin it as an xc2s30 is not the right way to
>proceed
>Thanks to everyone
>Diego
>
>
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Article: 104270
Subject: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
From: "Vivek Menon" <vivek.menon79@gmail.com>
Date: 22 Jun 2006 06:34:07 -0700
Links: << >>  << T >>  << A >>
Hello,
After reading up the Aurora user guide and the different replies for
this topic, I have a couple of questions:
Assume I have two V2 Pro or V4 boards with 8 Rocket I/O outputs each. I
have 4 Rocket I/Os (TX side=4 X 2.5 or 3.125 Gbits/sec) on Board 1
connected to 4 Rocket I/Os (RX side=4 X 2.5 or 3.125 Gbits/sec) on
Board2. I have also implemented Aurora protocol. Now is it possible to
enable channel bonding and take the output from the 5th Rocket I/O (TX
side) on Board 2 and safely assume that it transmits 10 GB/sec.
If what I have described holds true, the same concept can be used to
combine the data on 4 X 10 Gb/s(which cannot be achieved now).
Also, if anyone has suggestions on what specific parameters are to be
modified in Aurora, please let me know. I think the three parameters
that need to be changed are:
INST aurora_module_i_1/lane_0_mgt_i CHAN_BOND_MODE           = OFF;
INST aurora_module_i_1/lane_0_mgt_i CHAN_BOND_ONE_SHOT       = FALSE;
INST aurora_module_i_1/lane_0_mgt_i CHAN_BOND_SEQ_1_1        =
00101111100;
INST aurora_module_i_1/lane_0_mgt_i SERDES_10B               = FALSE;

I think the CHAN_BOND_MODE should be TRUE for the 5th Rocket I/O on
Board 2(cos that would be the master with the other 4 configured as
slaves).
What should be the values for ENHANSYNC and the remaining attributes??

Thanks in advance,
Vivek
Peter Alfke wrote:
> Yes, we support "channel bonding", which means we can use four
> transceivers, each at 2.5/3.125 Gbps to operate with a throughput of 10
> Gbps. But it involve four transceivers and four physical connections.
> I think Vivek's question was whether the four channels can be combined
> to one.
> Physical the answer is "NO". Virtual the answer is "YES", through
> channel bonding.
> Peter Alfke
>
> ==========
> Falk Brunner wrote:
> > Vivek Menon schrieb:
> > > Hi Sean,
> > > Can you please elaborate on Virtex-II Pro X and the technique to
> > > combine 4x2.5 Gbit/sec into 10 Gbit/sec?
> >
> > Very simple. The key word is channel bonding. This is done every day in
> > the 10G XAUI interfaces. So the idea is not new and it is doable without
> > too much trouble.
> >
> > Regards
> > Falk
> > 
> > P.S. The 4x2.5G is 4x3.125G due to 8B10B coding.


Article: 104271
Subject: Amirix AP120, U-Boot and uartlite
From: Klaus Mitskowski <awu.al888@gmail.com>
Date: Thu, 22 Jun 2006 16:03:34 +0200
Links: << >>  << T >>  << A >>
Hi,

since the license of the "original" uart-port is expired, I'm trying to use the uartlite ip core with u-boot and it won't work.

First of all the board boots PPCBoot Lite fine so I can load the compiled u-boot.bin via loadb into the memory (adress 08000000).
Finally I try to boot U-boot with go 08000100 and it won't work and the board hangs.

How I compiled u-boot:
make AP1000_config
make all

it works with the "original" uart ip core uart16550 but not with uartlite.

Can anybody give me a hint how to "patch" u-boot?

Greetings
Klaus

Article: 104272
Subject: Any eval SW comes with Spartan 3E Dev board from Xilinx/Digilent ?
From: rashid.karimov@gmail.com
Date: 22 Jun 2006 07:10:51 -0700
Links: << >>  << T >>  << A >>
ISE  and/or EDK ?


Article: 104273
Subject: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Thu, 22 Jun 2006 16:15:10 +0200
Links: << >>  << T >>  << A >>
Vivek Menon schrieb:

> Hello,
> After reading up the Aurora user guide and the different replies for
> this topic, I have a couple of questions:
> Assume I have two V2 Pro or V4 boards with 8 Rocket I/O outputs each. I
> have 4 Rocket I/Os (TX side=4 X 2.5 or 3.125 Gbits/sec) on Board 1
> connected to 4 Rocket I/Os (RX side=4 X 2.5 or 3.125 Gbits/sec) on
> Board2. I have also implemented Aurora protocol. Now is it possible to
> enable channel bonding and take the output from the 5th Rocket I/O (TX
> side) on Board 2 and safely assume that it transmits 10 GB/sec.

If the MGTs would support 10G.

> If what I have described holds true, the same concept can be used to
> combine the data on 4 X 10 Gb/s(which cannot be achieved now).

Since you dont have a 40G MGT. But you can do channel bonding using 16 
MGTs @ 3.125 Gbit/s to form al logical 40G data channel.

Regards
Falk

Article: 104274
Subject: R: newbie:my ISE doesn't include old xcs30 spartan how........
From: "blisca" <blisca@tiscali.it>
Date: Thu, 22 Jun 2006 15:37:34 +0100
Links: << >>  << T >>  << A >>
Thank you very much,i guess this is the right tool,even older than i thought
,
http://www.xilinx.com/webpack/classics/spartan_4k/index.htm
the fact is that i have to practice on surplus boards....
i ordered today an educational board from Digilent
http://www.digilentinc.com/
many thanks

Aurelian Lazarut <aurash@xilinx.com> wrote in message
e7e4um$8oc3@cliff.xsj.xilinx.com...
> Diego,
> these parts are dinosaurs, the last version of the tools to support
> 4K/spartan was ISE4.1 (maybe 4.2 but I'm not sure) you can still
> download tools from www.xilinx.com for old parts.
> I don't have a link handy, but is straightforward to find them on
xilinx.com
> Aurash
> blisca wrote:
>
> >how can i do to make it work with this old devices?experimenting with an
old
> >board i need to add xcs30 and i need a tool(older impact versions) for
> >programming it,i guess that treatin it as an xc2s30 is not the right way
to
> >proceed
> >Thanks to everyone
> >Diego
> >
> >
> >
> >
>
>
> --
>  __
> / /\/\ Aurelian Lazarut
> \ \  / System Verification Engineer
> / /  \ Xilinx Ireland
> \_\/\/
>
> phone: 353 01 4032639
> fax: 353 01 4640324
>
>





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