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Kolja Sulimma wrote:
> > wget --user={username} --password={password}
> > http://www.xilinx.com/webpack/index.htm
>
> I am sure that qualifies as hacking an effective copy protection
> technology under the DMCA.
:) Can it be considered a copy protection mechanism if it is advertised
as a copy-enabling mechanism?
Article: 107926On 2 Sep 2006 07:37:50 -0700, "fl" <rxjwg98@gmail.com> wrote: >Maybe the "ability" is not correct or accurate. After synthesis, the >simulation should reflect the reality of FPGA. But, the initial value >of counter is "0000". After the first clock rising edge, its content is >"00X0". It seems the simulation does not know the correct value even it >did know the first value is "0000". The simulation (or the simulator) does exactly what you you tell it to do. You need to know why your design doesn't calculate the first count correctly and fix it.Article: 107927
I have a xilinx soc that is running 2.4 of the PPC linux fine. To run 2.6 is it just a matter of copying the arch directory over to the 2.6 tree and compiling? (Assuming I keep the configuration options the same.) Thanks, ClarkArticle: 107928
Hello, I need to create a custom peripheral that DMA's data to the DDR SDRAM on the ML403 board. My custom componet & the DDR SDRAM reside on the PLB bus. Does anybody have an example of how to do this? The template that XPS generates does not provide any details and as everyone knows, the xilinx documentation is pretty poor. Thanks in advance HarryArticle: 107929
zwsdotcom@gmail.com wrote: > PeteS wrote: > > > I recently had this problem downloading the latest version at home. If > > you have a standalone firewall in place, and you are running a Win32 > > My Internet access, like most peoples', goes through a hardware router > that NATs my local network onto a single real IP address. I can't > connect directly to the Internet because there is other hardware that > requires 24/7 connectivity - alarms will ring and pain will occur if I > unplug the cable. > > > platform, then check the 'generic host process' permissions. I normally > > ... where? I've never seen a checkbox like this I don't use Windows > Firewall. I use Norton Antivirus. But even on a machine where I have no > software firewall, I get the same symptom. I don't use Windows Firewall. because I recently had to 're-purpose' my dedicated firewall / NAT / router box and have yet to replace it, I installed ZoneAlarm Pro, which gives me a lot of control of processes that may access different zones (for both inbound and outbound connections). I got an email back from Xilinx that basically said 'that's the way it is. It's free' My view on that is that so is their competition's. > > Xilinx's webmaster should be shot. His manager should be shot too, for > not keeping the situation under control. And HIS manager should be > boiled in oil, twice. I started a thread a while back on the worst websites, and Xilinx is quite up there. My comment was 'you need to know specifically what you are looking for and where it is before you start'. I had a call from my CM the other day asking about a download cable, and I told them to check the Xilinx site - they called back after an hour of frustration. Fortunately, I already had the PDF they needed at the office so I logged in and got it for them. > > They never test anything. As a data point, I've spent 38 billable hours > just trying to get to the point of getting a simple tutorial example to > build and run. (Not counting this WebPACK shenanigan). My experience too. Then there's the 'upgrade' to 8.1 - it's a bloated, stinking hog. 1GByte full install download (I can do that, but it's still huge). Where Impact started alost immediately before, now it takes an age, and it won't let me just open it and right click - no - EVERYTHING has to be associated with a f*ing project. D*mb sh*ts. > > > In addition, for some features, you need to turn on Java (which is even > > more stupid - I never use Java on websites, and if a vendor requires > > it, they are usually dropped from any designs I may be doing). > > I have to have Java installed because I do some development in that > language, so that's not a problem. Oh, I have it installed, I just don't permit remote sites to run java applets. And don't get me going on Webpack (well, ISE) requiring the use of Internet Exploder for it's html rendering - how about using the system browser? IDTenT error, apparently. IE is so locked on this system, it can read text and that's it. Cheers PeteSArticle: 107930
mk wrote: > On 2 Sep 2006 07:37:50 -0700, "fl" <rxjwg98@gmail.com> wrote: > > >Maybe the "ability" is not correct or accurate. After synthesis, the > >simulation should reflect the reality of FPGA. But, the initial value > >of counter is "0000". After the first clock rising edge, its content is > >"00X0". It seems the simulation does not know the correct value even it > >did know the first value is "0000". > > The simulation (or the simulator) does exactly what you you tell it to > do. You need to know why your design doesn't calculate the first count > correctly and fix it. I mean, I don't care about the absolute initial value of the counter. I think it indeed there are such cases in reality (although it is only a redundant activity to reset the counter to some value). I want to understand the capability of synthesis software a little more here. I have to program adhere to its requirement. I increase the step of the counter from 1 to 2, it is correct. But, it seems reset is necessary to obtain a correct counter. For shift register, some Xilinx chips have a structure which is very efficient but without a reset function I remember. Thank you.Article: 107931
Ali wrote: > I like to start FPGA but I have access to a CPLD traning kit . > > I would like to know : > > 1-If I start with CPLD (XC9572 the training kit has it ) can I later > work with FPGA (Spartan 2,3) ? > 2-Does these two have much defferent Hardware design ? > 3-Are ISE & VHDL have much defference ? > Look at it this way: What you need to know to do good work with FPGAs, CPLDs, or ASIC, for that matter, is a firm grounding in _logic_ design. You can get that from CPLDs, or from big conglomerations of 74xx parts, for that matter (although I don't know of any Verilog-to-74xx synthesizers). You'll run into some detail differences when you move to a different technology (such as an FPGA), but you'll still be doing _logic_ design. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 107932
Michael A. Terrell wrote: > > I worked seven months of 112 hours per week, and got paid for 148 > hours (16 hours/day with time and a half for anything over 40 hours) > except for Christmas Day and New Years Day when I got paid an extra 16 > hours per day. On top of that, my boss was bitching that I should be > willing to work even more hours. > > You know it is bad when this is the case and you ARE the boss.Article: 107933
Ray Andraka wrote: > Michael A. Terrell wrote: > > >> >> I worked seven months of 112 hours per week, and got paid for 148 >> hours (16 hours/day with time and a half for anything over 40 hours) >> except for Christmas Day and New Years Day when I got paid an extra 16 >> hours per day. On top of that, my boss was bitching that I should be >> willing to work even more hours. >> >> > > You know it is bad when this is the case and you ARE the boss. Do I hear a suppressed sigh? Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 107934
On 2006-09-02, Ali <sadatakhavi.ali@gmail.com> wrote: > > 1-If I start with CPLD (XC9572 the training kit has it ) can I later > work with FPGA (Spartan 2,3) ? Tim gave you a great answer. I just want to add that a small CPLD like the XC9572 is very small compared to an FPGA. The '72' is 72 flops. The smallest Spartan 3E has over 2000. I didn't appreciate this gap when I built my first proto board with a CPLD. > 3-Are ISE & VHDL have much defference ? Not that much. By the way, have you seen the Spartan 3 starter kit? http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=BOARDS -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 107935
Hello Bill, >> >>It's hard to practice out here in the west. Except for Radio Nederland >>Wereldomroep plus one friend who was born in NL there isn't much of a >>chance. > > Even in the Netherlands it is getting difficult - I've got an obvious > English accent, and many people will reply to my Dutch in English, just > to exercise their English. > The Dutch typically speak 3-4 languages so I had the same problem. Then I told all the people I see the most to respond in Dutch and not make it easy for me. Folks in the pubs, the merchants, the vendors at the market. That did it. Problem was, my Dutch wasn't what they speak in the north or in the big cities. I lived in Zuid Limburg and had been a member of a Belgian sports club. To make matters worse, some of the folks I learned from were born in the former Dutch colonies and they had a really thick accent. In the north they'd barely understand us unless we slowed down. What really amazed me was when we listened to the Belgian comedian Urbanus. We rolled on the floor laughing and the northerners wouldn't have a clue what his jokes were all about. English was a similar matter, one teacher from Kentucky, the other from Louisiana. -- Regards, Joerg http://www.analogconsultants.comArticle: 107936
Hi, I am learning Modelsim (6.1e) along with ISE webpack. I had done a behavior simulation, then a post-translate simulation. Now, I go back to do the behavioral simulation again. When I am in Modelsim, I modify the source vhdl code after I terminate the simulation. I recompile it. Then I simulate the testbench file. I find that the simulation is on the post-translation, not the behavioral simulation model. Why? Must I go back to ISE and relaunch the Modelsim? The following is the script. Why does it automatically compile smallComp_translate.vhd? vcom -explicit -93 -O0 C:/Xilinx/x/test/smallComp.vhd C:/Xilinx/x/test/netgen/translate/smallComp_translate.vhd # Model Technology ModelSim XE III vcom 6.1e Compiler 2006.03 Mar 8 2006 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity smallcomp # -- Compiling architecture behavioral of smallcomp # -- Loading package vital_timingArticle: 107937
zwsdotcom@gmail.com wrote: > Is it actually possible to download WebPACK? > > I tried using my existing xilinx.com account to download it, and I get > into an endless loop where I'm shown a button that says "click here to > register" then another button that says "click here to download if > you're already registered". The second button just takes me to the same > page again, over and over. > > I tried creating a new account on xilinx.com and with this account I > can't even log into the abovementioned infinite-loop page; it doesn't > accept the new username/password. > > Has anyone ever worked out the magic combination of browser versions > and whatever other magic the PITAs at xilinx require? Since this seems broken in so many ways, how about filing a request for a CD copy, every time this chokes or stumbles ? A beancounter in Xilinx will then notice that increase in CD despatch, and might actually (eventually) feel motivated enought to fix it. What happened to the old 'froth free' "site map" buttons ? -jgArticle: 107938
After thinking about how a "normal" CPU could look like, I've tried to design a Forth-like CPU: http://www.frank-buss.de/vhdl/forth-cpu.html Maybe someone from comp.lang.forth could take a look at it, if something is missing for compiling normal high-level Forth programs to this instruction set, without too many complications. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 107939
In engineering terms resolving preformance from background noise is the task Noise includes spurious= internal politics, nasty collegues and inept superiors. To imporve signal to noise increase the averaging period but beware the bathtub deterioration of performance both with age and boredome. Engineers are much further foreward in evaluating reality than accountants , general managers or HR where two faces make decisions Picean jjlindula@hotmail.com wrote: > Hello, I'm posting this question here because I want responses from > engineers, so please don't be offended. I want to know what your > thoughts are concerning Performance Appraisals at your company, are > they beneficial, how are they conducted, and what is the best way go > give performance appraisals? > > Where I work, the manager brings you into their office, starts a series > of short questions concerning your family and other things not relating > to your job and then finally gives you a pat on the back and says, good > job. Not much is really discussed and therefore not really useful. > > Your comments are welcomed. > > thanks, > joeArticle: 107940
I'm using an ML403 development board. The board has a Compact Flash card on it, as well as SRAM, DDR RAM, Flash, etc. I'm trying to load my large application into a file that I can copy to the Compact Flash in a file. I want to have a bootloader program read then file, load it into SRAM, and then start executing the SRAM code. Is there an example of doing this? Is this an unreasonable thing to do with this system? I've been talking to our local FAEs but have no real feedback from them on how to do this. Any help would be greatly appreciated. Thanks. DaveArticle: 107941
I've got a ML403 Virtex 4 development board with an FX12 part on it. I've developed several VHDL components that I need to interface to an embedded MicroBlaze. The VHDL components interface to the outside world through FPGA pins. I've looked at some Xilinx examples of devices like LEDs and switches interfacing to the MicroBlaze but these devices are always defined during the Base System Builder in XPS. I've tried the process of adding a GPIO for 32-bit input as: 1. Add IP for GPIO 2. Attach the GPIO to the OPB 3. Set the port connection IP2INTC_Irpt to opb_gpio_IP2INTC_Irpt 4. Set GPIO_in to opb_gpio_0_in 5. Generate addresses Do the GPIO pins have to be mapped to FPGA I/O pins? I had to select "Make External" on each connection or I got errors when trying to build the project. How do I attach local component functionality (known only to the top-level VHDL) to these GPIO pins? Are there any __simple__ examples of GPIO usage and instantiation with connections to the top-level architecture? Any help would be very much appreciated. Thanks. DaveArticle: 107942
Frank Buss wrote: > After thinking about how a "normal" CPU could look like, I've tried to > design a Forth-like CPU: > > http://www.frank-buss.de/vhdl/forth-cpu.html > > Maybe someone from comp.lang.forth could take a look at it, if something is > missing for compiling normal high-level Forth programs to this instruction > set, without too many complications. Looks good - some brief comments : I think the opcode is 8 bits ? That's good for off-chip memories. You could optionally allow a 9-bit opcode, for where the memory is FPGA BRAM ? That could also allow an option for 32 bit registers ? I think there is also opcode room to allow one byte SKIP form on the BRA... opcodes ? This could be assembler-automatic - where this is usefull, is in operating from serial flash memory. -jgArticle: 107943
I am a newer of System Generator. I designed an FIR with system generator, only using the Delay, Cmult, Addsub, upsampler, downsampler and Gateway In/Out block. Then I made it into a subsystem and masked it. Question are : Do I need to set the filter coefficient? What does filter coefficient stands for? And what value should I give to the coefficient? Thank you very much for your kindly help!Article: 107944
Frank Buss wrote:
> After thinking about how a "normal" CPU could look like, I've tried to
> design a Forth-like CPU:
>
> http://www.frank-buss.de/vhdl/forth-cpu.html
>
> Maybe someone from comp.lang.forth could take a look at it, if something is
> missing for compiling normal high-level Forth programs to this instruction
> set, without too many complications.
If you are going to compile Forth then CALL is probably the first
instruction you want to optimize and I didn't even see it or an
equivalent in your list. Other than that this is probably a very
reasonable way to encode Forth. Given that you have spare bits in
several cases my guess would be that it isn't an optimal encoding
(Chuck Moore's 5 bit instruction set and the variations people have
made are probably closer to optimal).
Even with your current instruction set it is probably possible to write
your network address swap code to be a little smaller:
push byte 5
:loop dup ; i i
pop A ; i
@A byte ; (i) i
over ; i (i) i
push byte 6 ; 6 i (i) i
add ; 6+i (i) i
pop A ; (i) i
@A byte ; (6+i) (i) i
over ; (i) (6+i) i
!A byte ; (6+i) i
over ; i (6+i) i
pop A ; (6+i) i
!A byte ; i
dec ; i-1
bcc byte :loop
drop
When you have an address register like in the MISC processors it is a
good idea to avoid reloading it when possible. In this case having both
6+i accesses happen next to each other does that. And in general it
isn't very good to allow the stack to get very deep with temporary
values when programming stack machines.
By the way - this code fragment that you have been testing various
architectures with has a problem in that in general the first word to
be swapped would be some random one and not happen to be address zero.
Rewritting it so that MAC addresses to be swapped are at 200 and 206,
for example, would have no effect in some cases but increase the length
of the code for other processors.
-- Jecel
Article: 107945Jim Granville wrote: > Since this seems broken in so many ways, how about filing a request > for a CD copy, every time this chokes or stumbles ? A DVD copy is free, but you pay shipping. I suspect the cost of DVDs is negligible... it would take a lot for the beancounters to notice!Article: 107946
As a data point, webpack just downloaded fine for me. The registration, questionaire and process was the same as the last time I tried it (last year?) It was 970MB and took 1 hour 44 minutes over DSL. I am using Firefox 1.5.0.5. The hardest part was remembering my user name and password. But I am in Redwood City, California, so it only had to go a few miles. Alan Nishioka zwsdotcom@gmail.com wrote: > Jim Granville wrote: > > > Since this seems broken in so many ways, how about filing a request > > for a CD copy, every time this chokes or stumbles ?Article: 107947
Alan Nishioka wrote: > As a data point, webpack just downloaded fine for me. The Amazing. Maybe they have multiple servers for load sharing, and the one handling the East Coast is the one that's f#$cked up? I think I went above the call of duty - I tried three different browsers on three different machines, one of which was a completely vanilla installation of MSIE on Windows XP - I had literally only just unwrapped the machine. If a web site doesn't work on a system that generic, it's WAY broken.Article: 107948
Ray Andraka wrote: > > Michael A. Terrell wrote: > > > > > I worked seven months of 112 hours per week, and got paid for 148 > > hours (16 hours/day with time and a half for anything over 40 hours) > > except for Christmas Day and New Years Day when I got paid an extra 16 > > hours per day. On top of that, my boss was bitching that I should be > > willing to work even more hours. > > > > > > You know it is bad when this is the case and you ARE the boss. That one wasn't self employed, and I quit no long after that. They ended up spending over $100,000 to replace equipment I routinely repaired, and no one else in the country wanted to touch. I did put in a lot of long hours when starting a business. Sometimes I worked for a couple days straight and did a job that was scheduled to take weeks to complete, sleep a couple days and do the same thing on another big job. That may be why my health is shot, and I'm 100% disabled these days. Later on when the business was running smooth, if I woke up during the night I would go to the shop and work four or five hours with no one around, and no phone calls to bug me. -- Service to my country? Been there, Done that, and I've got my DD214 to prove it. Member of DAV #85. Michael A. Terrell Central FloridaArticle: 107949
Jim Granville wrote: > > Looks good - some brief comments : > I think the opcode is 8 bits ? > That's good for off-chip memories. > You could optionally allow a 9-bit opcode, for where the memory is FPGA > BRAM ? That could also allow an option for 32 bit registers ? > Since you have flag registers, you need a way to push and pop them if you have interrupts. Usually Forth chips use 0=, 0< and IF or IF and -IF instead of flag registers, so there is nothing to save. This means that signed comparisons like < take longer but that doesn't seem to be a problem. CALL is used in Forth much more often than in other languages so you should try to encode it compactly. 8-bit opcodes are kind of nice because serial flash is pretty fast. In a Spartan3, you could map the lower 2K bytes of program space to a BRAM block and the rest to external flash. You keep the fast (mostly kernel) words in the BRAM. --brad
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