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"srini" <g.shrinivasan@gmail.com> wrote in message news:1147439140.316222.317180@j33g2000cwa.googlegroups.com... > Hi, > In Synplify Pro, there is a 'Fanout Guide' option. What is the > reasonable value for this option? How to decide the Fanout value. Is > there any thumb rule sort of thing for this? > > Thanks & Regards, > Srini. I don't think there's any one answer. For my designs where I keep the timing tight and the logic cones short, the fanout limit often causes more problems than it solves. Since the Xilinx architecture I target has drivers at each node when the signal splits off in a chaotic tree to get to all the destinations, there isn't a "load" that makes the signal less reliable as the situation might be when loading many inputs off a physical wire. If your target architecture has fanout recommendations, consider those. If the timing analysis from your back end tools (and from SynplifyPro) suggest you're fine with timing, don't worry about fanout unless experience or literature suggests there's a problem. When I have one signal feeding every bit in multiple adders, for instance, the signal is cleanly distributed in my FPGA yet the number of connections would cause the fanout limit to replicate. As with register duplication, this second signal is too-often combined with the original signal to make a 4-input LUT break out into 2 levels of logic because there are now 5 signals for the function, two of which are exact copies. I'd like to see reasons anyone else might choose to apply a real fanout limit.Article: 102251
"srini" <g.shrinivasan@gmail.com> wrote in message news:1147421219.221889.122660@g10g2000cwb.googlegroups.com... > Hi, > I am using the "syn_useioff = 1" directive in my top module to pack the > Input/Output registers into the IOB and synthesizing using Synplify > Pro. For PAR, I am using Xilinx ISE 7.1 > I would like to know how to check and see whether the input and output > registers are packed in the IO blocks after PAR. > Also, I am tri-stating my outputs based on a control signal by using > the following syntax in verilog : out_data = 16'bz. So, I want to check > whether the tri-state buffers and the output registers are placed in > the same IOB. Can this be done? Some people are telling that this > verilog syntax will not actually tri-state the outputs in > implelementation and I have to specifically instantiate the tri-state > buffers from Xilinx. Can anyone clarify me about this? > > Thanks & Regards, > Srini. Me, I like to have an OFFSET OUT AFTER constraint that gives a Tco value slightly larger than the guaranteed clock-to-out time for my I/O standards. If I don't have a register packed in the IOB, there's a failure in the timing constraint.Article: 102252
srini wrote: > Hi, > In the map report file, all the input and output signals are listed > under the IOB name column in the IOB properties section. But under the > reg(s) column, only my clock outputs have the OFF1 entry and all other > input and ouput signals have no entry of IFF/OFF/ENFF. What does it > mean? > It means that those IOs aren't registered in the IOB. If you want to figure out why, I suggest you search comp.arch.fpga. http://groups.google.com/group/comp.arch.fpga/search?group=comp.arch.fpga&q=iob+register&qt_g=1&searchnow=Search+this+group --- Joe Samson Pixel VelocityArticle: 102253
"John_H" <johnhandwork@mail.com> wrote in message news:8N19g.698$oa1.536@news02.roc.ny... > > Me, I like to have an OFFSET OUT AFTER constraint that gives a Tco value > slightly larger than the guaranteed clock-to-out time for my I/O > standards. If I don't have a register packed in the IOB, there's a failure > in the timing constraint. Neat!Article: 102254
Does anyone know of any good papers describing methods and or algorithms for implementing a Synchronous Scrambler (LFSR) in parallel? Thanks.Article: 102255
<gaurav.vaidya2000@gmail.com> wrote in message news:1147381389.917103.41120@j33g2000cwa.googlegroups.com... > If you are targetting programmable hardware (which you most possible > are), you can get IP cores to work for you. Check out opencores.org or > Xilinx or Altera websites to find cores that provide functions you need. > The Square root function is available as a free megafunction in Altera Quartus. I have just used it as part of my new 32 bit embedded processor design in a Stratix part. A 32 bit square root with a 4 clock pipeline runs in excess of 40MHz in a C7 part. SlurpArticle: 102256
http://www.xilinx.com/bvdocs/appnotes/xapp220.pdf Might be useful? Austin Colin Hankins wrote: > Does anyone know of any good papers describing methods and or algorithms for > implementing a Synchronous Scrambler (LFSR) in parallel? > > Thanks. > >Article: 102257
I've been running into a similar problem recently. For me, ISE would freeze after the prompt that asked if I wanted to unlocked the project file, or would just never load (and eat up 99% of the CPU). It seems to work if I replace the .ise file with a backed-up .ise file, then actually delete the .lock file before starting up ISE. From browsing Xilinx support it looks like there may be issues with ISE corrupting the .ise file on a crash. I'd recommend keeping your own backup (NOT the automatic backup) of the .ise file. Wonder why could they didn't just keep the project file a simple ASCII file like the old .npl? I agree that ISE stability has gone downhill. Altera had a lot of customers defect after their first buggy Quartus tools--Xilinx should take note. Brian WalkingtonArticle: 102258
Yeah, I looked into using that. It actually gets pretty expensive, seems to have an exponential cost related to the number of write ports for the XOR scheme. It is a very interesting solution though. I have a multiple-port reorder buffer that uses partitioning to implement multiple ports, which is very efficient. The reorder buffer writes up to four entries at a time into the register file. So I'll just use time-multiplexing for the register file and hide the extra cycle of latency it takes to update the register file by keeping the data in the reorder buffer an extra cycle.Article: 102259
Hi all, I'm trying to synthesize a design using ISE 7.1 and am getting segmentation faults. The .srp file only gives me the foll message: make: *** [leon3mp.ngc] Segmentation fault How do I debug this? Has anybody encountered segmentation faults before? There isn't anything else in the warnings etc that could indicate a seg fault being imminent. Thanks!Article: 102260
Thanks! Ok, I fixed a few instances of the numbers. <MikeShepherd564@btinternet.com> wrote in message news:eud862pue2p4m6u274up9jj7qhp8si0ena@4ax.com... > >I created a small tutorial about JTAG... > http://www.fpga4fun.com/JTAG.html >> >>...happy to hear about mistakes/suggestions... > > I haven't read it in detail, so I won't comment on the content, but I > like the style. It's well-paced. It's concise. It doesn't have > unnecessary and confusing repetition. It's laid out clearly with good > diagrams. Most articles fail on all these points. > > I'd only say that it's best to avoid writing small numbers (1-10) and > non-exact numbers as digits. E.g. it's easier to read "a few > thousand...three inputs and one output" than "a few 1000...3 inputs, > and 1 output". > > MikeArticle: 102261
Correct. I actually know only one flash that can be programmed through JTAG (Platform flash, made by ST, sold by Xilinx). So I'm a little optimistic in my webpage. Anyone knows if we can get these flash from ST directly? or another source? "Ad" <adam.taylor@eads.com> wrote in message news:1147441764.754114.86100@d71g2000cwd.googlegroups.com... > Eli > > most flash devices do not have a JTAG port but can still be programmed > via JTAG by ensuring all the pins of the flash chip which are required > address, data, and control signals are connected to a device which does > have a boundary scan port. Unused fpag pins are good for this. The JTAG > software can then control the FPGA pins connected to the flash to write > data into the flash device. If you are going to do it this way it is > often necessary to take the WE pin to a spare pin on the JTAG header to > enable the speed of the programming to be quicker. > > hope this helps > > Ad >Article: 102262
> I'm trying to synthesize a design using ISE 7.1 and am getting segmentation > faults. The .srp file only gives me the foll message: > > make: *** [leon3mp.ngc] Segmentation fault > > How do I debug this? Has anybody encountered segmentation faults before? > There isn't anything else in the warnings etc that could indicate a seg > fault being imminent. Windows? Unix? Linux? What service packs installed? Any reason you can't move up to 8.1? Did you search the Xilinx website for this error? DavidArticle: 102263
Ashish wrote: > >You can use a DLL or DCM for that; You could also search for Peter > >Alfkes paper 'six easy pieces', chapter 4 > > Yes thats simple trick. Thanks for your input. Ashish, If you decide to use the DLL (there is no DCM in Spartan 2) you should be aware that the "lock" output of the DLL will not de-assert after the initial lock, so you need a secondary means of detecting that lock was lost. When the DLL is not locked, the 2x clock output actually runs at 1x the input clock. The six easy pieces approach will not generate a 50% duty cycle like the DCM. There's always a trade-off... Cheers, GaborArticle: 102264
The 6-easy-pieces XOR design works reliably, but it just generates one pulse on each input transition, irrespective of that transition's direction. Therefore the doubled clock does not have a defined duty cycle, and two adjacent output clocks (or pulses) may have different spacing, as a result of a non-50% input duty cycle. If these limitations are acceptable, it's a nice and simple/cheap way to double the clock frequency, and it works down to as low a frequency as you possibly might want. Peter Alfke, XilinxArticle: 102265
Sounds like an interview question. There are a lot more differences, which go basically down to the concepts of VHDL. You can write pages about this. This is one of the best and most difficult to answer questions about VHDL IMHO. YiQi wrote: > What's the different between variable and signal? > > variable > signal > assignment operator: := > <= > share between process: key word"shared" > yes > > what else? >Article: 102266
On 9 May 2006 01:36:09 -0700, "ALuPin@web.de" <ALuPin@web.de> wrote: >Hi newsgroup, > >I have observed a strange behaviour in our VHDL design: > >One signal goes low and stays low (133MHz clock domain)(No Reset case). >That flag >is synchronised with one FF into a 125MHz clock domain where >a FSM is running. The flag (flag='0') is checked in one of the states >of the FSM. > >When using one FF for synchronization the circuit shows strange >behaviour, when >using two FFs it works fine. > >I mean the flag does not show much activity, it becomes high or low and >remains stable. So why should one FF not be sufficient for >synchronization ? > >Any ideas ? > >Rgds >André The problem you are describing sounds a lot like metastability. You can read about it here: http://www.fpga-faq.org/FAQ_Pages/0017_Tell_me_about_metastables.htm In terms of timing analysis, the path for the flag signal (in the 133 MHz domain) to the input of your first synchronizing flipflop (in the 125 MHz domain) does not matter much, as the signal is crossing the clock domains. The synchronizing FF can go metastable. You have to look VERY CAREFULLY at what happens to this synchronized version of your flag. First you need to look at the timing for this signal. At 125 MHz, you only have 8 ns. Meeting this timing requirement is not enough! That is because you need some additional time to resolve metastability. Your goal should be that the routing delay (+ clock to output + setup time to FSM FF) is less than 5 ns. This would give you 3 ns of resolving time. Second, you should make sure that when this flag changes, the change in the state machine's state encoding only changes 1 FF. The reason that 2 FFs works so much better, is that you get to do the resolving between the two FFs, which if they are close together, may leave as much as 5 ns resolving time. Philip Freidin Philip Freidin FliptronicsArticle: 102267
Hi fpga, I woudl like to tell two stories about the reverse engineering. One story is about how auto thef in L.A. steal latest version of Toyota Lexus car. The car has a wireless key mechanism. Without the key, i.e., without wireless signal the car cannot be started. L.A. Times reports how smart the auto thef act. Very simple, and all procedure would be done within one minute. 1. Broke the window (not necessarily broke the glass) and open car door as usually they do; 2. Open hood cover; 3. Detach the wireless key module; 4. Install their own wireless key module matched with their key; 5. Close the hood; 6. Drive the car away. 2. Xilinx has applied all patents for its key encoding mechanisms: PAT. NO. Title 1 6,965,675 Structure and method for loading encryption keys through a test access port 2 6,957,340 Encryption key for multi-key encryption in programmable logic device 3 6,415,032 Encryption technique using stream cipher and block cipher 4 6,212,639 Encryption of configuration stream 5 6,118,869 System and method for PLD bitstream encryption 6 5,970,142 Configuration stream encryption With their circuits and their principle in hand and appropriate ASIC/FPGA schematics knowledge, experiences and tools, it is certain that you will be successful.to decode any code imbeded in the chip. For any ASIC/FPGA design and manufacture companies it is a small thing to do: decode their embedded code. After careful reading their patents, one will know what the weakest point is and how to do it. WengArticle: 102268
I don't have such an extensive experience of reverse engineering like fpga, but here is what I once did. While the Coolrunner was Philips, I liked it and asked if I would be given the programming data. I got two files which were most of it (at that point I thought I had it all). I designed the device in and when I started to write my logic compiler tool for it I discovered I missed the data on how the multiplexing area (ZIA, they call it) worked. By that time the switch to Xilinx was on, I knew neither Peter nor Austin nor this newsgroup (long story why). So I took the Philips software, wrote a number (65, just looked) of files which did various routings and wrote a software to look at the Jedec files and build the map based on that. Every new file eliminated possibilities and as they got to 65, I had them all (actually I think I had 2-3 unknown combinations which I just left unused). Well, it took me 2 or 3 weeks to do it (working pretty hard, that is). In general, I tend to design new things and am not interested in reverse engineering. In this case, though, I had to do it - I still have no wintel or whatever alien software involved in my design process, from schematic drawing through PCB design through JTAG testing & programming to software development and I intend to keep that as long as I can (having complete control over all tools and stuff makes a great difference). I have a wintel based laptop here which I use as a browser and .pdf reader - since about a year. Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ P.S. Here is the JEDEC part of interest (one example): NOTE ZIA Decoder Array * L40600 0000101101111111000110100100000001000010* L40640 1111010111111110001011011100011101001011* L40680 1111000001100010000000010100001101001011* L40720 1111111110011101111111101010010000100100* And here is the table which I generated: http://tgi-sci.com/tgi/scm/ziarev.txt (too wide to be posted here)Article: 102269
Weng Tianxiang wrote: > 2. Xilinx has applied all patents for its key encoding mechanisms: [...] > With their circuits and their principle in hand and appropriate > ASIC/FPGA schematics knowledge, experiences and tools, it is certain > that you will be successful.to decode any code imbeded in the chip. Assuming that you have an arbitrarily large amount of time, money, and units of the device to be reverse engineered. The latter is necessary because failed attempts will generally cause the key to be lost. > After careful reading their patents, one will know what the weakest > point is and how to do it. Certainly. The weakest point is that the decryption key is stored in RAM cells in the part. All you have to do is extract the bits from the RAM cells. Piece of cake. (Not!)Article: 102270
thx, Jim, Sorry, the examples are miss leading. My main concern is the different during design flow. Let me restate my question, During HDL synthesis, that's the difference between them? Will that make any different after synthesis(place & route)?Article: 102271
"srini" <g.shrinivasan@gmail.com> wrote: >Can you tell me how to do Physical synthesis and bring in the routing >delays for synthesis. I am using Xilinx ISE 7.1 for PAR. Can physical >synthesis be done with it. How to bring in the routing delays from >Xilinx PAR and use it for synthesis in Synplify Pro? You may be able to vastly improve results by adding syn_keep or syn_preserve or -routing to key signals, to prevent retiming where it isn't helping. Or by doing some manual retiming, and turning off the automatic retiming. Or floorplanning, often placing just a few items is all that is needed. Start with block rams, multipliers, or registers at the ends of the failing path(s). Or updating ISE to 8.1 and try "map -timing". Try several things, see what works and doesn't for your design. I'd suggest trying these before spending more money on a tool. Otherwise, talk to Synplicity about "Synplify Premier". Also, there are other tools by Mentor (and others?), and I have no recent experience to allow me to give good suggestions as to which to look at. However, the same warning applies: Not all problems can be solved by any tool. You probably want to see if you can get an evaluation version first. -- Phil HaysArticle: 102272
Ray Andraka <ray@andraka.com> wrote: >Jim Wu wrote: > >> Another way to verify this is to open the ncd file in FPGA_EDITOR and >> see what are put in the IOBs. >> >> HTH, >> Jim >> http://home.comcast.net/~jimwu88/tools/ >> >Or look at the pad report, there is a column there indicating whether >the signal is registered or not for each pad. Or set static timing constratints on all pins that can only be reached with IOB FFs... -- Phil HaysArticle: 102273
wpiman@aol.com wrote: > We have a Xilinx Flash (XCF series I believe) that we would like to > program in circuit from a microcontroller in order to support field > reconfigurability. This flash has a JTAG backend. We were thinking > about using the GPIO ports on a microcontroller to wiggle the JTAG > lines and load the new files that way. Problem is we don't know much > about the upper protocol involved in JTAG and the documentation seems > hazy. Has anyone done something similar? Does software exist that > will do this for us? > Why bother about a Configurator. If you connect a std flash or SPI dataflash (AT45) to a fast enough controller (AT91:-) you will be cheaper off.. > Thanks, > WP -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This message is intended to be my own personal view and it may or may not be shared by my employer Atmel Nordic ABArticle: 102274
Hi Eric, 10 years ago when I was in China, there was a Chinese electronics company in Beijing boasting every kind of FPGA chips in the world could be decrypted and I really believed it, because they had many products copied from other manufactures' products without designing: just copy, including copies of PCB, FPGA and software driver. I estimate that their FPGA copy business would be going on without any hurdle with latest Xilinx encryption algorithm and circuits. They don't have an arbitrarily large amount of money, but they have smart engineers, enough time and experiences for more than 20 years. For us as outside observer, it may need an arbitrarily large amount of time, money to start fresh, but for them, it is their business and really a piece of cake! And how they do their copy of FPGA is really another secret! For Xilinx decryption circuit, there is a data input port and a data ouptput port. Data input port has input plain bit stream and output port has output encrypted code. One even doesn't have to read the key data and just put a probe on the input port and another on clock, he will get all data stream that is what I thought in theory when I was reading Xilinx encryption circuit. Xilinx encryption circuit is not an equavalence to P ?= NP in computer complexity theory. The latter is an open problem pending for more than 30 years without any solution. Xilinx encryption circuit is only an engineering circuit and it cannot be as reliable in encryption as the algorithm they used. Weng
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