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Hi Mark, Any advise ? Thanks, SandeepArticle: 102351
I like the price of the eval boards!! 0.00 USD published price on Xilinx web!! but well not available, guess the S3, S3E SAD STORY is repeating again or can we hope for better availability ?? hm the 0.00 USD price is eval without the Virtex-5 you have pictures of the boards, and still not available, what could be the reason for not selling eval boards that are made without the silicon? must be some reason. at least there is an v5 LX on the eval board picture :) AnttiArticle: 102352
does LXT is include rocket IO? ok, I am not fair - you specified LX not LXT AnttiArticle: 102353
Un bel giorno shawnn@gmail.com digiṭ: > Are there any alternatives to getting the parts I need without paying > 400% markup? Consider yourself very lucky. The main issue, especially with bigger FPGA, is that you have to buy at least 100 pieces (and wait two months for them to ship anyway). Neither Xilinx nor Altera give a crap on small enterprises that can't afford to blindly spend 10-20 k$ just to make one prototype, maybe for nothing. I'm going to give up using FPGA for bigger projects. When I need a model that is available on digikey it's ok, but when more gates are needed, I have to look for more affordable technologies. -- asdArticle: 102354
I am trying to be fair now, only asking LX questions :) 1) Xilinx website says to the general public that 'start designing' NOW to my understanding it means that software support is available NOW, or is there is any other way to see it? 2) the sysmonitor and ADC block that is present in V4 silicon but disabled by the design software, it is ripped out from V5 ? hm, I am afraid all my others questions are related to FX so it would be fair to ask those. grrrr Antti Lukats PS ROTFL ROTFL ROTFL - this is was gooood laugh !!!! I had to re-register again to gain access to the support archive for the V5 user guide. The download size was indicated as 9MB, made me interested what the heck is inside, NOW I know: the 9MB archive holds a single file, with famous name: readme.txt --------------- This is a placeholder file for the Virtex-5 SSO calculator. The calculator is due to be available with ISE8.2i software. --------------- Hm at least it's now clear that V5 support must be included in ISE 8.2i and not 9.x ? Or will 8.2i only include that SSO Calculator?? But then what and when will actual V5 support be included in ISE/EDK? Anayway it was good ROTFL ! ! ! The office is empty so I had no fear anyone calling the 911Article: 102355
Hi Austin, This gives me the impression that V4-FX will be skipped - or at least customers will be pushed to V5-FX. This scares me quite a lot, actually. OK, now some questions for the LX: How does the performance compares with V4-LX for simple things like Counter/Mux/Booth Multiplier. Any trade-offs for the I/O? Full 3.3V tolerant/compatible? What's the core voltage? That's it for now. I look forward to get hands on the (prelim.) datasheet. Regards and thanks for you response, Luc On Mon, 15 May 2006 10:19:20 -0700, Austin Lesea <austin@xilinx.com> wrote: >Josh, > >Always ask for what we didn't release? OK, that is fair. I wasn't very >specific. > >Details on FX in June. > >For now, questions on LX. > >Austin > >Josh Rosen wrote: > >> On Mon, 15 May 2006 09:49:53 -0700, Austin Lesea wrote: >> >> >>>ryanrs, >>> >>>Yup. Now Peter and I are able to talk about Virtex 5. >>> >>>Any questions? >>> >>>65nm lives....both fabs! >>> >>>Of course, it is early, but we are in ES sampling, and accepting folks for >>>early adoption. >>> >>>The release of the documention should be pretty good. I'd like to hear >>>back on how good folks think it is. >>> >>>Austin >>> >>> >> >> >> I don't see any mention of a V5FX on your website. Can you tell us >> anything about the RocketIO on the Virtex5-FX yet? >> >>Article: 102356
Antti, LXT is the LX with transceivers, yes. We have not finished with the characterization of the transceivers. Stay tuned for their announcement. Austin Antti wrote: > does LXT is include rocket IO? > > ok, I am not fair - you specified LX not LXT > > Antti >Article: 102357
Antti, > 1) Xilinx website says to the general public that 'start designing' NOW > to my understanding it means that software support is available NOW, or > is there is any other way to see it? Software is available now. > 2) the sysmonitor and ADC block that is present in V4 silicon but > disabled by the design software, it is ripped out from V5 ? It will be back, but not right away (in the software, it is definitely there in V5). Some things require a lot of characterization, and yield analysis, and we do not want to put customrs through what we did last time, for which we are very sorry, and promised not to do again. We did get the sysmon working in V4, but too late to introduce it. It did allow us to debug the process of testing, yielding, etc. a complex analog block. What we learned was applied to V5. > hm, I am afraid all my others questions are related to FX so it would > be fair to ask those. grrrr Sorry. FX comes later. Transceivers come later, LXT. But the LXT will be here sooner than the FX or FXT parts. > readme.txt > --------------- > This is a placeholder file for the Virtex-5 SSO calculator. The > calculator is due to be available with ISE8.2i software. > --------------- The SSO calculator just missed by hours for this deadline. Try the link tomorrow. It was just one of those things where the key person who we needed to get us the numbers was out on vacation until last Monday, so we didn't have all the time we thought we had to get it ready. > Hm at least it's now clear that V5 support must be included in ISE 8.2i > and not 9.x ? Yes. > Or will 8.2i only include that SSO Calculator?? But then what and when > will actual V5 support be included in ISE/EDK? No, SSO will be there very shortly. ISE/EDK is another matter. I don't know the schedule on that. For Microblaze, that should be now (or very soon). For PPC, that waits for the FX. Maybe someone who knows will email me. AustinArticle: 102358
scary eh? the V5 performance data/comparison is given in currently available documentation, I just completed full fetch of the V5 docs and managed to get a quick peek. core is 1.0 but thats no surprise. the 3.3V standards are all there of course AnttiArticle: 102359
Antti schrieb: > 1) Xilinx website says to the general public that 'start designing' NOW > to my understanding it means that software support is available NOW, or > is there is any other way to see it? You can either download a text editor from the Xilinx Website or select the "pencil and paper package" (5 weeks lead time) from the webshop to start your HDL capture now. Kolja SulimmaArticle: 102360
LOL LOL I may borrow a paper and pencil Virtex5 HDL Design kit from my son I also (he had 4th birthday yesterday) I think - leadtime, hm when do I get home?. jokes beside, he did like to play with the S3e sample pack (the dice game) too bad all my 3 sample pack PCBs are dead:( no wasnt faul play, they all died in my hands when inserting power plug (LTC power supply burned in). Antti PS I hope there will be some tech news info also regarding V5, ok ok I can already say that folks trash V4 and plans to use V4 if you can wait for V5. similarly to S3e, V5 also has some nifty things added, small things that matter.Article: 102361
lb, V4 FX is not skipped. It is most definitely being shipped right now. In fact the backlog was just cleared. > OK, now some questions for the LX: > How does the performance compares with V4-LX for simple things like > Counter/Mux/Booth Multiplier. The basic fabric is a bit faster, but not a whole lot (perhaps only ~10%). The 6-LUT provides the most improvement by reducing the levels of logic. Anywhere from 58% speedup, with an average of 30% speedup over many hundreds of real customer designs from V4. The carry logic is faster, and that is in the data sheet already. > Any trade-offs for the I/O? Full 3.3V tolerant/compatible? What's the > core voltage? 1.0 Volt Vccint. 3.3V is the Vcco for the IO (or 2.5, or 1.8 or 1.5...). > That's it for now. I look forward to get hands on the (prelim.) > datasheet. http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Data+Sheets/FPGA+Device+Families/Virtex-5 AustinArticle: 102362
Kolja, Software is immediately available for the early access folks. The general release of Virtex-5 LX (minus the LX330) will be in the initial release of 8.2i which is about a month away. Austin Kolja Sulimma wrote: > Antti schrieb: > > >>1) Xilinx website says to the general public that 'start designing' NOW >>to my understanding it means that software support is available NOW, or >>is there is any other way to see it? > > > You can either download a text editor from the Xilinx Website or select > the "pencil and paper package" (5 weeks lead time) from the webshop to > start your HDL capture now. > > Kolja SulimmaArticle: 102363
There is a guaranteed glitch-free clock multiplexer design in "six easy pieces", #6 Find it under TechXclusives on the Xilinx website, or click on: http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1211408&iLanguageID=1&multPartNum=1 &sTechX_ID=pa_six_easy&languageID=1 Sorry for the ridiculously long URL. Peter Alfke, Xilinx =============== Morten Leikvoll wrote: > I have a CPU register block where I use the outputs (wich are supposed to be > static) to control other clock domains. > > The question rises; will these signals coming out of a flip-flop be > guaranteed free for glitches? > > For a synchronous design, there is a setup&hold condition in the cpu clock > domain where this signal will be stable, but how about the rest of the time > window? Is there any tricks to make this guaranteed glitch free? > > The reason I ask is that I want to use this signal to mux (using 2 input > muxcy to avoid lookup table glitches) a clock signal and I want the outgoing > clk to be glitch-free. Maybe I have to route the switching signal thru a > bidir pin and put a capacitor on it. > > Note:I WILL treat this new clk as a new clock domain, and the domain WILL be > reset properly after switching clock.Article: 102364
Hi Austin, I hope my smilies do get some others smile, well its a good day today (LOL + ROTFL) no I mean it, its good for change - really. you are joking too :) please please can I email the ISE/EDK 9.1 to you? FX vs FXT ?? in the website info roadmap there are LX LXT SXT FXT but no FX ? can we hope FX earlier than FXT ? can we hope ethernet MAC earlier than _T parts? or are those questions "FX only" ? AnttiArticle: 102365
One last thought, There are some that suspected we were close to an announcement, and decided to wind up the presses to spread forth much blather. Too bad. They are now left looking a bit foolish. 30% speedup today. More density today. Lower cost today. Lower dynamic power, and equivalent static power, today. Triple oxide (again) today. I don't think people really appreciate the triple oxide, and what it does for us: it allows us a third type of transistor which is optomized for stability (think about SEUs) for the config memory, and extremely low leakage, as well as for a optimized pass gates. This means we still have the lowest static leakage of anyone at both 90nm AND now at 65nm. Oh, there is NO 65nm FPGA, except ours. The triple oxide process is something we pioneered with our fab partners. Read: both of them. Something that we can do, because our customers have chosen Xilinx, and made us large enough (read successful enough) to specify our own process to our fabrication partners! Think of that: what vendor has enough solid proven business to specify a process to more than one fab? Imitation is the sincerest form of flattery, as STM now also has a triple oxide 90nm process. I am sure they will also offer it at 65nm, as they also realized how useful it was to their customers. http://www.tsmc.com/english/technology/t0113.htm is a little late to the game. They are just now advertising 90nm triple oxide (by next calender quarter). Too bad. Too little, too late. That is not even 'fast follower'. That is a really late entrance onto the world stage by the leading player! Now, for the second time, we have brought out this fantastic new technology, again on two fabs at once. No tricks, and no area hungry or goofy circuits for "maybe saving power." Just good old straight-forward simple engineering: use the right transistors for the right job. No risk to the customer, as the triple oxide technology worked great in V4, and is working great again in V5. AustinArticle: 102366
the basic LUT delay cant be much faster, it was pretty damn fast in V4 already ! however the 6 input LUT is not true 6 input LUT but two 5 input LUTs and a mux so if the mux delay is significant then 6 input function will we way slower than 5 input function, sure there is still performance gain over plain 4 LUT architecture. AnttiArticle: 102367
Hi, When can we expect Spartan 4? Six input LUTs seem to be a long over due change. DaveArticle: 102368
Antti, Even my crystal ball is too foggy to see than far. Austin Antti wrote: > Hi Austin, > > I hope my smilies do get some others smile, well its a good day today > (LOL + ROTFL) > no I mean it, its good for change - really. > > you are joking too :) please please can I email the ISE/EDK 9.1 to you? > > FX vs FXT ?? > in the website info roadmap there are > > LX > LXT > SXT > FXT > > but no FX ? > > can we hope FX earlier than FXT ? > can we hope ethernet MAC earlier than _T parts? > > or are those questions "FX only" ? > > Antti >Article: 102369
Thanks for the replies Antti and Mr. lamah. I have read some posts about "gray market" sources for chips. What / where are these sources? I already know about eBay of course.Article: 102370
Antti wrote: > the basic LUT delay cant be much faster, it was pretty damn fast in V4 > already ! > however the 6 input LUT is not true 6 input LUT but two 5 input LUTs > and a mux > so if the mux delay is significant then 6 input function will we way > slower than > 5 input function, sure there is still performance gain over plain 4 LUT > architecture. > How does it compare to the Stratix II 6-input LUT?Article: 102371
Antti wrote: > I like the price of the eval boards!! > > 0.00 USD published price on Xilinx web!! > > but well not available, guess the S3, S3E SAD STORY is repeating again > or can we hope for better availability ?? > > hm the 0.00 USD price is eval without the Virtex-5 you have pictures of > the boards, and still not available, what could be the reason for not > selling eval boards that are made without the silicon? > > must be some reason. > > at least there is an v5 LX on the eval board picture :) > The $0.00 price was a TBD placeholder until the final price is set. The selling price for both of the boards will be in $1000-$1500 range. As with all of the Prototyping Platforms, these boards do not ship with a specific part. I know that this may seem unusual and undesirable, but these are meant to be used across any of the devices that come in a specific package type for prototyping purposes and the user supplies the device that they want to use. They should be shipping in early July. Ed McGettigan -- Xilinx Inc.Article: 102372
Kudos on the new release! But I started to glaze over as you turned on your marketing engines. I sincerely prefer the technical Austin. Way to go, Xilinx. - John_H "Austin Lesea" <austin@xilinx.com> wrote in message news:e4ai8h$avv8@xco-news.xilinx.com... > One last thought, > > There are some that suspected we were close to an announcement, and > decided to wind up the presses to spread forth much blather. > > Too bad. > > They are now left looking a bit foolish. <snip> yada yadaArticle: 102373
Antti schrieb: > however the 6 input LUT is not true 6 input LUT but two 5 input LUTs > and a mux > so if the mux delay is significant then 6 input function will we way > slower than > 5 input function, sure there is still performance gain over plain 4 LUT > architecture. Hmm. There really is no difference between a MUX and a LUT. Same schematic symbol, same choice of implementations, same thing. > the basic LUT delay cant be much faster, it was pretty damn fast in V4 > already ! You can not really read the circuit speed from the datasheet or FPGA editor, as they use abstracted timing models. You can push delay around almost at will in a timing model. At any node of the timing model you can subtract a delay from all outgoing edges and add them to all incoming edges without changing the model. If you reduce the delay of some edges to zero you can merge nodes. You can even have negative delay edges in timing models. You can use this to simplify the model for your software or for the user. Or you can try to look better than your competitor this way because people tend to compare certain delays and ignore others. As a note: The value for the carry chain is pretty reliable beacuse each element is immediately preceeded and succeeded by an identical element. Not much pushing possible there. Kolja SulimmaArticle: 102374
Antti wrote: > the basic LUT delay cant be much faster, it was pretty damn fast in V4 already ! > however the 6 input LUT is not true 6 input LUT but two 5 input LUTs and a mux > so if the mux delay is significant then 6 input function will we way slower than > 5 input function, sure there is still performance gain over plain 4 LUT > architecture. The Virtex-5 6-input LUT is a true 64-bit look-up-table. Any 6 input function can be implemented in the LUT. You can of course think of any LUT as being generated a 128-to-1 MUX, but that would be inefficient in actual hardware to build. As for the timing, the Virtex-5 data sheet is online with timing delays for all three speed grades so you can verify the performance differences. Ed McGettigan -- Xilinx Inc.
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