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The INIT pin becomes user I/O after configuration. INIT going low indicates a CRC only if it goes low before the startup sequence of the device. If it goes low after the DONE pin has gone high then this does not indicate a CRC error but is rather attributable to the fact that INIT has probably become a user I/O now that the image is loaded and the FPGA has gone through the startup process. StephanArticle: 88351
You can use the SOPC builder with AHDL, but you have to write a wrapper in VHDL or BDF. My experience is that although not happy about the extra file to write, it works. HavardArticle: 88352
"Marc Randolph" <mrand@my-deja.com> schrieb im Newsbeitrag news:1124046200.879611.318300@z14g2000cwz.googlegroups.com... > > dalai lamah wrote: > > Which is the preferred way to generate the output clock for a deserializer > > made with a shift register? For example, let's say I feed a 4-bit shift > > register with a 500 MHz signal, so that I have to store four bits at 125 > > MHz into a BRAM (or just latch them). How do I generate this 125 MHz clock? > > I can't use a DCM because the input frequency is out of range, but if I > > generate the clock with common logic (e.g. a binary counter or a shift > > register), how can I be sure that it won't violate the hold/setup times in > > respect to the four output bits? > > Howdy, > > Two ways to solve this: > > 1. If the 125 MHz "clock" isn't needed for a considerable amount of > logic, strongly consider generating and using a clock enable that is > actually in the 500 MHz domain. > > 2. If you have a bunch of logic that needs to run at 125 MHz, the DCM > has a CLKIN_DIVIDE_BY_2 mode to handle higher frequencies: > > http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0064_25.html > > Have fun, > > Marc > Marc, I guess you did pay attention to the part selection of OP, Spartan-3 there is no way Spartan-3 DCM handles 500MHz, well there is one undocumented config bit of the DCM (aka ultra high freq mode) but I really dont know what it does... in all normal modes S3 DCM will not handle 500MHz in our actual measurements with S3 -4 speedgrade the DCM actually worked OK til 275MHz above that it failed. now to the 500MHz clock in S3, I think this may just barely be useable, but to be hones I am little bit interested by what means this clock is entering the S3 logic fabric. The highest clock I have measured in S3 fabric is around 420MHz (speed grade -4), the 420MHz is useable, but only in very limited routing area, basically all the 420MHz needs to be locked down into primitives or be implemented as hard macro. I think that a VERY careful design may just work at 500MHz, but it really needs to be optimized and 'hard locked'. Xilinx max toggle speed for S3 is some 750MHz, 500 is very close to it. Well if the 500MHz was not the clock freq but bitrate and dual data rate (2 clock edges) is being used then we get down to 250MHz what is more useable in Spartan-3 to the OP if 500MHz deserializer is used then the design should run out of 250MHz the clock doubling should happen at OBUF DDR primitives. The DCM can accept input freq as low as 1MHz is your input clock lower than that? if the input clock is highere than DCM range try using the clkindiv2 attribute anttiArticle: 88353
Jim Granville schrieb: > Subroto Datta wrote: >> Quartus allows mising > that should be mixing ? No, missing. The OP was missing a language ;-) Kolja SulimmaArticle: 88354
Peter Alfke <peter@xilinx.com> wrote: > Jim, what do you suggest: > Whenever somebody in Xilinx suggests an application, all software is > put onhold until the new idea has passed all software? > Or: Whenever somebody in Xilinx suggests an application, it may not be > published until it has passed all software implementations? > The specific idea in this thread is over 30 years old, and had been > proven in many TTL designs, but had not been synthesized, because > synthesis did not exist at its birth. > Nevertheless, I have gone back and made some circuit ideas more > synthesis-friendly... > Peter Alfke With the thread " ISE 7.1 'improvements' plus meandering.... " Jim probably suggested to put more entries in a regression suite that is hopefully run before each ISE release/service pack... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 88355
"Hubble" <reiner@huober.de> wrote in message news:1124136042.619204.91920@g44g2000cwa.googlegroups.com... >I suppose you are describing your design in VHDL. > > Disconnect statements are used for bus signals which are controlled by > an implicit GUARD signal inside of blocks. Probably not what you want. > > Drivers of signals can be disconnected by assigning the null waveform > element. > > sig<=null; > > also not what you want. If you want to synthesize, it's best to > describe in terms of standard register and latches. Your description is > a bit puzzling, but it sounds to me as slv_reg0 is a normal latch, > which is enabled when the external signal is valid and latching when it > is invalid. You can describe this in VHDL without using disconnect or > null waveform elements. > > > Hubble. > I have done as you told. It works well. Many and many thanks! MarcoArticle: 88356
Hello, I had the same problem when the RAM controller was inside a module. The way I solved the problem was very easy, I converted the bidir port into two and added a port with the control signal of the bidir port. I put the bidir just in the top level, adding also the logic that controls the port something like: assign data=control?data_i:data_o; It works perfect with the modular flow. Javier Castillo On 14 Aug 2005 00:44:38 -0700, "Fpga_Designer" <FPGA05@gmail.com> wrote: >Hello all, > >I am currently using xilinx modular design flow to develop a simple >design. The top level design has an inout port for communicating data >between an external memory and fpga. I have implemented the necessary >control logic for this port in one of the modules and port mapped the >port of the module to the top level inout port. After having done this >when I run (ngdbuild -modular initial top.edd) with all the modules >instantiated (black boxes only) I receive the following error >"ERROR:NgdBuild:456 - logical net '***' has both active and tristate >drivers". > >Can anyone suggest what needs to be done in this regard. > >ThanksArticle: 88357
Un bel giorno Antti Lukats digiṭ: > there is no way Spartan-3 DCM handles 500MHz, But the CLKIN_DIVIDE_BY_2 attribute seems to be supported also by Spartan3! > now to the 500MHz clock in S3, I think this may just barely be useable, but > to be hones I am little bit interested > by what means this clock is entering the S3 logic fabric. I need to use the 500 MHz clock just for the shift registers that deserialize the data, i.e. four flip-flops for each bit (and sixteen bit in total). I've tried to add this clock constraint to my design and it compiled correctly, even without manual floorplanning. In theory, if we give credit to the S3 datasheet, they should go at least 100 MHz faster than that! I'm very interested on this topic, I was believing that the datasheet specifications (and ISE map/par results) were realistic. If they aren't, I'd like to know it before I make the prototypes. :) > Well if the 500MHz was not the clock freq but bitrate and dual data rate (2 > clock edges) is being used then > we get down to 250MHz what is more useable in Spartan-3 No, it's SDR. Actually it's the output of a MAX104, high-speed ADC (another problem will be interface its LVPECL 3V interface with S3 LVPECL_25, but one problem at a time :-)). > that? if the input clock is > highere than DCM range try using the clkindiv2 attribute Uhm, I'm not sure what's your point; this is exactly the same advice that Marc gave me, but apparently in the first part of your message you didn't agree with that. :) -- asdArticle: 88358
Un bel giorno Marc Randolph digiṭ: > 2. If you have a bunch of logic that needs to run at 125 MHz, the DCM > has a CLKIN_DIVIDE_BY_2 mode to handle higher frequencies: > > http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0064_25.html Thank you, I didn't notice this feature! -- asdArticle: 88359
Un bel giorno dalai lamah digiṭ: > No, it's SDR. Actually it's the output of a MAX104, high-speed ADC (another > problem will be interface its LVPECL 3V interface with S3 LVPECL_25, but > one problem at a time :-)). This problem seems to be already solved: :-) http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=18095&iLanguageID=1 I am always amazed on the quality of Xilinx answers database. -- asdArticle: 88360
"Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag news:4300f5c3$0$18648$14726298@news.sunsite.dk... > Hi Vladimir, > The circuit's being optimised away because the 'tool' doesn't understand > that there's stuff outside the chip. It can't understand the output is > current limited, so it thinks your circuit can be optimised away. If you > make the outputs tri-state-able, and drive the tri-state line to turn them > on from something the 'tool' doesn't optimise away, you'll have more > success. Maybe. > Have fun! > Syms. > not maybe. for sure. I use special wires called 'always1' those are driven to 1 always but in the way that XST doesnt guess that. Those wire are useful to keep stuff from being optimized aways. another option would be create a hard macro, there things are more persistant AnttiArticle: 88361
Hi does anybody have a design example of an image sensor connected to programmable logic with HDL code? I want to try this. I have not committed any hardware yet so a working example would be a great starting point. Mostly concerned with the physical connections and image sensor low level interface code.Article: 88362
Hi, Enviroment Board : Nios development kit(cyclone edition)version 3.1 Quartus : version 4.2 NIOSII IDE : version 1.1.0(build 137) Host OS : Windows XP(German version) I have used a standard project from the NIOS examples and downloaded the sof file through JTAG(ByteBlasterII) from quartus programmer. When I try to download my software from the NIOSII IDE it gives me the following error The instruction in "0x00709536" refers to memory in "0x00c8=E3d0".The procedure "READ" could not be executed on the memory"(translated from german to english). I couldnt run my C software on the development kit because of this problem.I have even reinstalled both quartus and nios dev. kit.But the same response. Is it a bug in NIOS software or on windows XP? I will be obliged if anybody can help me to solve my problem. Please let me know if more information needs to be provided. Thanks in advance. Monica, GermanyArticle: 88363
I'm using that same configuration except WINXP is english. I don't have any problems like you've described. I have seen WinXP issues come up with drivers. But those problems were automatically reported through the OS and updates sent all in less that a week. So be sure you've got automatic updates turned on. georgeArticle: 88364
> I will be obliged if anybody can help me to solve my problem. > Please let me know if more information needs to be provided. > Thanks in advance. > Monica, Monica, The best place for NIOS problems is.... http://www.niosforum.com/index.htm The forums are read by NIOS developers and experienced users. You can also search to see if others have had the same problems. Nial. ------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 88365
Paul Urbanus wrote: > I am assisting in the debug of a board with XC5202 parts. The design is > done using Aldec schematics in the M1.4 environment. I have M1.5 set up > on Win2K in a VMWare virtual machine. > > Q: Does anyone know the latest version of the Xilinx implemenation tools > which support the XC5200? > I'm using version 4.1i which I believe is the end of the line for Aldec tools available through Xilinx. However Xilinx no longer has a working relationship with Aldec, so you're on your own for finding this version. I don't have the XC5200 devices installed on my machine, but the libraries guide in this revision still lists them, so I think they're supported. > Q: Latest version of Foundation Express which supports XC5200? > Foundation Express 3.6.1 works with 4.1i There may be a later release that supports XC5200. > Q: Can either of these older versions be installed/run from Windows 2000? Yes. 4.1i also runs on XP service pack 1. > Q: How can I get the latest patches/service packs for tools with XC5200 > support? > You may be out of luck there, since Xilinx no longer has a working arangement with Aldec. > I have a valid license for Foundation Express version which supports > XC5200. Following is from my license.dat > > PACKAGE FND-EXP-PC xilinxd 1.000 30A0C0B1948681FADED8 \ > COMPONENTS="system-PC bit-PC \ > xc3000D-PC xc4000X-PC xc5200X-PC \ > ngd2vhdl-PC verilog-PC \ > Foundation-PC X-VHDL-PC \ > FPGA-Express:1997.110 \ > FPGA-Express-VHDL-Base:1997.110 \ > FPGA-Express-VLOG-Base:1997.110 \ > FPGA-Express-XC3k-Optimizer:1997.110 \ > FPGA-Express-XC4k-Optimizer:1997.110 \ > FPGA-Express-XC5k-Optimizer:1997.110 \ > FPGA-Express-XC9k-Optimizer:1997.110 \ > FPGA-Express-Constraint-Mgr:1997.110 " > > Does anyone know what version of Foundation Express this license applies to? > I think you'll have to go by release dates. (1997 week 110?) Mine (for 3.6.1) has lines: COMPONENTS="FPGA-Express:2002.12 \ FPGA-Express-VHDL-Base:2002.12 \ FPGA-Express-VLOG-Base:2002.12 \ FPGA-Express-XC3k-Optimizer:2002.12 \ FPGA-Express-XC4k-Optimizer:2002.12 \ FPGA-Express-XC5k-Optimizer:2002.12 \ FPGA-Express-VIRTEX-Optimizer:2002.12 \ FPGA-Express-XC9k-Optimizer:2002.12 \ FPGA-Express-Constraint-Mgr:2002.12 \ FPGA-Express-GAT:2002.12 " > To Xilinx: How can I get this license renewed? How can I get a copy of > the install CD and patches for this version of Foundation Express? > > > TIA > Urb > > > _______________________________________________________________________________ > Posted Via Uncensored-News.Com - Accounts Starting At $6.95 - http://www.uncensored-news.com > <><><><><><><> The Worlds Uncensored News Source <><><><><><><><>Article: 88366
Bob wrote: > Hi does anybody have a design example of an image sensor connected to > programmable logic with HDL code? > > I want to try this. I have not committed any hardware yet so a working > example would be a great starting point. > > Mostly concerned with the physical connections and image sensor low > level interface code. Have you already picked out a sensor? There are as many interface models as there are sensors (almost).Article: 88367
Paul, Fastest way to get an answer to this is to open a webcase. We do provide support for old software and devices. Austin Paul Urbanus wrote: > I am assisting in the debug of a board with XC5202 parts. The design is > done using Aldec schematics in the M1.4 environment. I have M1.5 set up > on Win2K in a VMWare virtual machine. > > Q: Does anyone know the latest version of the Xilinx implemenation tools > which support the XC5200? > > Q: Latest version of Foundation Express which supports XC5200? > > Q: Can either of these older versions be installed/run from Windows 2000? > > Q: How can I get the latest patches/service packs for tools with XC5200 > support? > > I have a valid license for Foundation Express version which supports > XC5200. Following is from my license.dat > > PACKAGE FND-EXP-PC xilinxd 1.000 30A0C0B1948681FADED8 \ > COMPONENTS="system-PC bit-PC \ > xc3000D-PC xc4000X-PC xc5200X-PC \ > ngd2vhdl-PC verilog-PC \ > Foundation-PC X-VHDL-PC \ > FPGA-Express:1997.110 \ > FPGA-Express-VHDL-Base:1997.110 \ > FPGA-Express-VLOG-Base:1997.110 \ > FPGA-Express-XC3k-Optimizer:1997.110 \ > FPGA-Express-XC4k-Optimizer:1997.110 \ > FPGA-Express-XC5k-Optimizer:1997.110 \ > FPGA-Express-XC9k-Optimizer:1997.110 \ > FPGA-Express-Constraint-Mgr:1997.110 " > > Does anyone know what version of Foundation Express this license applies > to? > > To Xilinx: How can I get this license renewed? How can I get a copy of > the install CD and patches for this version of Foundation Express? > > > TIA > Urb > > > _______________________________________________________________________________ > > Posted Via Uncensored-News.Com - Accounts Starting At $6.95 - > http://www.uncensored-news.com > <><><><><><><> The Worlds Uncensored News Source > <><><><><><><><> >Article: 88368
Uwe Bonnes wrote: Uwe, I understand. Most regression test suites are huge designs intended to cover as much ground as possible. Adding in a debounce ciruit as a separate test isn't productive. Now having one "goofy" suite with ALL of the strange and wonderful test cases that are three lines or less would be useful.... Something to work towards. Austin > Peter Alfke <peter@xilinx.com> wrote: > >>Jim, what do you suggest: >>Whenever somebody in Xilinx suggests an application, all software is >>put onhold until the new idea has passed all software? >>Or: Whenever somebody in Xilinx suggests an application, it may not be >>published until it has passed all software implementations? > > >>The specific idea in this thread is over 30 years old, and had been >>proven in many TTL designs, but had not been synthesized, because >>synthesis did not exist at its birth. > > >>Nevertheless, I have gone back and made some circuit ideas more >>synthesis-friendly... >>Peter Alfke > > > With the thread " ISE 7.1 'improvements' plus meandering.... " Jim probably > suggested to put more entries in a regression suite that is hopefully run > before each ISE release/service pack... >Article: 88369
Jeremy Stringer wrote: > > Sven, approximately the sequence of steps that you go through is this - > > You take your VHDL (and constraints file - ucf for a xilinx native > flow), and run it through a synthesiser (AFAIK, this is XST for ISE). > This gives you a file with a set of primitives relevant to the FPGA you > are working with (EDIF for me)). > Sven's problem is that he is using ISE 4.2, which I am fairly sure did not come with a synthesis tool. I don't really see an easy solution for him. Presumably he is trying to use a very old part, or else I don't understand why he would be using ISE 4.2. A very old part would probably require a very old synthesis tool.Article: 88370
On Tue, 16 Aug 2005 09:06:10 -0400, Bob <bob@notrealmail.com> wrote: >+<Hi does anybody have a design example of an image sensor connected to >+<programmable logic with HDL code? >+< >+<I want to try this. I have not committed any hardware yet so a working >+<example would be a great starting point. >+< >+<Mostly concerned with the physical connections and image sensor low >+<level interface code. ****** FIrst off you are ging to have to decide on type. Frame Transfer, progressive scan or CMOS imager. Each one has their advantages and disadvantages. External clock generation will differ with each. FOr the most part the Frame Tranfer Imagers, mostly TI, have large gate capacitances and the clock source for these chips are not drivable from a FPGA. Peak currents to the SAG and IAG of the TI chips can be in the range of 1 amp. All imagers will clock each pixel out serially, that analog output is then fed to an ADC. You can bin adjacent pixels to form larger pixels and even bin rows to increase pixel size. SOme imagers allow this to be done internal to the chip. Then you need to determine what application this camera is used for. Still pictures using fast integration times, slow integration times, or video and how many FPS you want. Each type of imager requires it own unique interface. So decide from which type depending on apllication needs and then start thinking of what circuits are needed around the imager. jamesArticle: 88371
Paul Urbanus wrote: > I am assisting in the debug of a board with XC5202 parts. The design is > done using Aldec schematics in the M1.4 environment. I have M1.5 set up > on Win2K in a VMWare virtual machine. > > Q: Does anyone know the latest version of the Xilinx implemenation tools > which support the XC5200? The very latest versions of Xilinx implementation tools that support XC5200 are Founation 4.1i and Founation 4.2i series. Please note that is the latest "implementation" tool. You can use latest version of synthesis tool from Synplicity or Synopsys. You can use latest version of simulator from Aldec or any other vendor as well. Also, Foudation design can be imported into Aldec's Active-HDL software so you can maintain and resuse your Fouantion design. Active-HDL can also help you to covert the design targetting newer devices. > > Q: Latest version of Foundation Express which supports XC5200? Foundation Express is basically Xilinx Founation bundled with Synopsys's FPGA Express. FPGA Express 3.6 is bundled with Founation 4.1/4.2 series. > > Q: Can either of these older versions be installed/run from Windows 2000? Foundation (Express) 4.x should be able to run on Windows 2000 and Windows XP SP1. > > Q: How can I get the latest patches/service packs for tools with XC5200 > support? If you are talking about patches for Xilinx implementation tool, it is discontinued so there is no future patched or service packs. Xilinx released at least two service packs for 4.1i. > > I have a valid license for Foundation Express version which supports > XC5200. Following is from my license.dat > > PACKAGE FND-EXP-PC xilinxd 1.000 30A0C0B1948681FADED8 \ > COMPONENTS="system-PC bit-PC \ > xc3000D-PC xc4000X-PC xc5200X-PC \ > ngd2vhdl-PC verilog-PC \ > Foundation-PC X-VHDL-PC \ > FPGA-Express:1997.110 \ > FPGA-Express-VHDL-Base:1997.110 \ > FPGA-Express-VLOG-Base:1997.110 \ > FPGA-Express-XC3k-Optimizer:1997.110 \ > FPGA-Express-XC4k-Optimizer:1997.110 \ > FPGA-Express-XC5k-Optimizer:1997.110 \ > FPGA-Express-XC9k-Optimizer:1997.110 \ > FPGA-Express-Constraint-Mgr:1997.110 " > > Does anyone know what version of Foundation Express this license applies to? It looks like an older Founation Express software, probably with Express Version 2.0, which is actually Foundation 1.4. Check the following link on Xilinx site: http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=3480&iLanguageID=1 Again, this design can be open/imported in latest Active-HDL software from Aldec. > > To Xilinx: How can I get this license renewed? How can I get a copy of > the install CD and patches for this version of Foundation Express? > > > TIA > Urb > > > _______________________________________________________________________________ > Posted Via Uncensored-News.Com - Accounts Starting At $6.95 - http://www.uncensored-news.com > <><><><><><><> The Worlds Uncensored News Source <><><><><><><><>Article: 88372
Antti Lukats <antti@openchip.org> wrote: > "Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag > news:4300f5c3$0$18648$14726298@news.sunsite.dk... > > Hi Vladimir, > > The circuit's being optimised away because the 'tool' doesn't understand > > that there's stuff outside the chip. It can't understand the output is > > current limited, so it thinks your circuit can be optimised away. If you > > make the outputs tri-state-able, and drive the tri-state line to turn > > them on from something the 'tool' doesn't optimise away, you'll have > > more success. Maybe. > > Have fun! > > Syms. > > > not maybe. for sure. > I use special wires called 'always1' those are driven to 1 always but in > the way that XST doesnt guess that. Those wire are useful to keep stuff > from being optimized aways. > another option would be create a hard macro, there things are more > persistant Can you show us your way to define 'always1'? Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 88373
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im Newsbeitrag news:ddt4t2$809$1@lnx107.hrz.tu-darmstadt.de... > Antti Lukats <antti@openchip.org> wrote: >> "Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag >> news:4300f5c3$0$18648$14726298@news.sunsite.dk... >> > Hi Vladimir, >> > The circuit's being optimised away because the 'tool' doesn't >> > understand >> > that there's stuff outside the chip. It can't understand the output is >> > current limited, so it thinks your circuit can be optimised away. If >> > you >> > make the outputs tri-state-able, and drive the tri-state line to turn >> > them on from something the 'tool' doesn't optimise away, you'll have >> > more success. Maybe. >> > Have fun! >> > Syms. >> > > >> not maybe. for sure. >> I use special wires called 'always1' those are driven to 1 always but in >> the way that XST doesnt guess that. Those wire are useful to keep stuff >> from being optimized aways. > >> another option would be create a hard macro, there things are more >> persistant > > Can you show us your way to define 'always1'? > > Thanks > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Hi Uwe, there are many ways. 1 use fixed value IO pin as input 2 a 0 pin, 0 lut variant is to use alwaays1 <= not(SEL1 and SEL2) where SEL1 are SEL2 are outputs from BSCAN primitive 3 just use inverse of the pattern compare result to some 'known' never true signal set, this is application dependant Antti PS I just tried to implement the SPDT switch as proper hard and also as 'locked/constrained' soft macro, and failed in both cases because of Xilinx tools bugs. So the 'always1' approuch is possible the only useable at the moment, unless 8.1 update fixes the issues, I do not belive the issues could be fixed in 7.1 service packs.Article: 88374
Hi all I am regret to inform you all that this the last time I either post or reply to comp.arch.fpga newsgroup. This decision was triggered by an reply from an Xilinx employee to one of my postings. If someone wants to look up that posting then its around the sentence: "This may have been a mistake" - I do understand that I may have understand the original intentions of that posting and that sentence and the context wrong, but that doesnt make any difference to my decision which is final. I will not discuss this matter in public or make any comments on it. A small explanation about the reasoning and background of my decision is available but not for free and not for quoting or republishing by any media. http://shop.openchip.org/shop/product_info.php?cPath=28_29&products_id=36 Antti Lukats, posted to comp.arch.fpga at 1900PM on 16 August 2005 my final smile :) to all of you.
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