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Hi all, I have got two high frequency clocks , i need to select one of them, but while muxing the output clock(one of the two high will be gated). Is there any way to avoid this. Regards, PravArticle: 88226
Hi Antti, I agree with you that Xilinx availability-announcements are always more or less over-optimistic. However, I think you are bit unfair, you should not mix "availability" with "on-stock-delivery". Many well established products have delivery-times of several weeks, but you would not say that all these products are not available. I can remember times, just some years ago, when I ordered 1k-0603-resistors at Farnell and got a delivery-time of allmost a year... (OK, you can call THAT not available... ;-) Also I think that it would be a good idea to contact a distributor if you want to use a brand new product. They can contact Xilinx and discuss your need. This process will not happen when you simply look on a web-site, of course. Also, a delivery time of 5 weeks is normally no problem for new designs, as long as it is guaranteed. You will need this 5 weeks anyway for design and PCB-production. Thomas "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:ddhvh5$60d$01$1@news.t-online.com... > "Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> > schrieb im Newsbeitrag > news:1123808503.796652.203850@o13g2000cwo.googlegroups.com... >> Thanks. Yes, I'm back although via Google (which has it's own >> advantages). >> >> XC3S100E and XC3S500E samples are generally available today. If you >> are having a problem obtaining them after placing an order, please let >> me know. >> >> Samples of the rest of the family are through September and October. >> >> --------------------------------- >> Steven K. Knapp >> Applications Manager, Xilinx Inc. >> General Products Division >> Spartan-3/-3E FPGAs >> http://www.xilinx.com/spartan3e >> --------------------------------- >> The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. >> > > Hi Steven > > I just checked Xilinx web store, Spartan-3e is not there. > When it is to be expected to be available ?? > > What disties say I do know, they will quote standard leadtimes, > and that means that even though you can place order today the > actual parts will not arrive until september. > And september was what I have forecasted all the time for availability. > > Nuhorizons, S3-100e, lead time 5 weeks, end of september! > Digikey: no S3 at all > Xilinx Online: no S3E > Avnet: s3-100e, ENGINEERING SAMPLE ONLY , no stock or call, that means NO > AVAIL, no leadtime known > s3-500e, ENGINEERING SAMPLE ONLY , no stock, that means NO > AVAIL, no leadtime known > Memec has been purchased by Avnet so no sense to check. > > So where is the general availabiluty ?? > > > Antti > > > > > > >Article: 88227
> CMOS wrote: >> hi all, >> Im in the need of capturing images at about 500 Frames per second and >> sending all raw data to PC through some port. The sensor i'll be using >> will be one from Kodak ( KAC-9630, KAC-9638 ) and the communication >> channel im thinking of is USB 2. I need to do this with minimal effort, >> as the real work is writing some processing algorithems to this raw >> image data. >> > > Hmm, 500 frames over USB 2.0 ?! USB 2.0 can do a peek of > 56MBytes/sec, which would mean 56*1024/500 = 114 bytes per > image ?! > > Regards, > rudi 114 Kbytes. Maybe that sensors supports partial read-out and he wants to transfer only part of the picture, then it will be possible. However, he will need a lot of light with such short exposure times and that sensors ;-) Thomas www.entner-electronics.comArticle: 88228
On 12 Aug 2005 03:38:40 -0700, "CMOS" <manusha@millenniumit.com> wrote: >hi all, >Im in the need of capturing images at about 500 Frames per second and >sending all raw data to PC through some port. The sensor i'll be using >will be one from Kodak ( KAC-9630, KAC-9638 ) and the communication >channel im thinking of is USB 2. I need to do this with minimal effort, >as the real work is writing some processing algorithems to this raw >image data. > >The ideal solution for me is to buy a development board which support >this Image sensor and USB2 interface. The ones i checked, which are >from >http://www.framos.de are too expensive. ( about $ 5500 ). So if some >one knows a kit with those features for low cost, please let me know. > >The next alternative is to buy a FPGA development kit with USB2 >support. i know some details about spartan 3 starter kit, which >supports digilent Inc's Accessory module for USB2. Can some one explain >the steps involved in using these two modules to communicate with the >PC? > >Third alternative is to implement the logic for USB2 high speed >communication in the FPGA it self. Is this possible? And how complicate >will this be? I'm in the process of doing something similar, to interface an old Kodak Ektapro high-speed camera system (details www.electricstuff.co.uk/ektapro.html) I've not yet looked into the USB2 aspect but like you am interested in getting the data to the PC at a reasonable speed with a minimum of effort. You probably don't want to send all the data to the PC, and even if you do, doing it in real time is going to be a major challenge. A better approach is probably going to be to use a FPGA to capture and store it in SDRAM, and then download what you need to the PC , e.g. after cutting out the frames before/after the event of interest, cropping the image etc. It also means the PC interface does not need to acheive a particular speed to keep up, which will remove a lot of constraints. This assumes that you are capturing relatively short events - if you need continuous processing at that rate you will need a BIG FPGA and do it all in hardware! Some of the higer-end Xilinx eval kits include SDRAM SIMM sockets Another thing that may be worth a look is a PCI FPGA board, which will give you plenty of bandwidth into the PC. Incidantally, Micron also do a high-speed sensor that may be worth a look.Article: 88229
praveen.kantharajap...@gmail.com wrote: > Hi all, > > I have got two high frequency clocks , i need to select one of them, > but while muxing the output clock(one of the two high will be gated). > > Is there any way to avoid this. > > Regards, > Prav I'm not sure what you're asking here. Are you talking about avoiding "runt" clock pulses (switching glitches)? Newer Xilinx components (since Virtex II) have BUFGMUX components which handle this properly. Without the built-in BUFGMUX, you would need to create a synchronous gating circuit for each input clock that guarantees only one clock is enabled at any time and that each clock gates on or off synchronously. This produces an output clock that has a stretched low (or high depending on active state of gating) period during the switch but never a short low or high period. All this gating will however cause some delay, so the phase relationship to the input clocks may not be good enough for "high speed" clocks.Article: 88230
"Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag news:42fc93ed$0$2279$91cee783@newsreader02.highway.telekom.at... > Hi Antti, > > I agree with you that Xilinx availability-announcements are always more or > less over-optimistic. However, I think you are bit unfair, you should not > mix "availability" with "on-stock-delivery". Many well established products > have delivery-times of several weeks, but you would not say that all these > products are not available. I can remember times, just some years ago, when > I ordered 1k-0603-resistors at Farnell and got a delivery-time of allmost a > year... (OK, you can call THAT not available... ;-) > > Also I think that it would be a good idea to contact a distributor if you > want to use a brand new product. They can contact Xilinx and discuss your > need. This process will not happen when you simply look on a web-site, of > course. Also, a delivery time of 5 weeks is normally no problem for new > designs, as long as it is guaranteed. You will need this 5 weeks anyway for > design and PCB-production. > > Thomas > partially agree, but I would call general availability the date when first 'normal' customer who placed small volume order to some disti actually receives the parts. Not the day hes order was accepted. And to my understanding from that point of view there is no S3e general availabiliy before septemer (or maybe late late August). If some customer did manage to get the parts earlier it doesnt change anything. General means just anyone who placed regulart order will get the parts without the need to specially escalate the order processing. BTW, if General Availability is now, that means there was there some availability earlier, but in that case there S3e evaluation boards should be shipping already, but they are not. Ok, I am unfair maybe. here some advice to Xilinx: with any new products send a first batch of silicon to the disties and announce general availability after confirmation that the parcel is arrived at disti stock. or make the device available (even for samples only) at Xilinx webshop. Thats not a hard thing todo, but avoid PITA comments as those of mine in the future. AnttiArticle: 88231
Mike Harrison wrote: > On 12 Aug 2005 03:38:40 -0700, "CMOS" <manusha@millenniumit.com> wrote: > > >hi all, > >Im in the need of capturing images at about 500 Frames per second and > >sending all raw data to PC through some port. The sensor i'll be using > >will be one from Kodak ( KAC-9630, KAC-9638 ) and the communication > >channel im thinking of is USB 2. I need to do this with minimal effort, > >as the real work is writing some processing algorithems to this raw > >image data. > > > >The ideal solution for me is to buy a development board which support > >this Image sensor and USB2 interface. The ones i checked, which are > >from > >http://www.framos.de are too expensive. ( about $ 5500 ). So if some > >one knows a kit with those features for low cost, please let me know. > > > >The next alternative is to buy a FPGA development kit with USB2 > >support. i know some details about spartan 3 starter kit, which > >supports digilent Inc's Accessory module for USB2. Can some one explain > >the steps involved in using these two modules to communicate with the > >PC? > > > >Third alternative is to implement the logic for USB2 high speed > >communication in the FPGA it self. Is this possible? And how complicate > >will this be? > > I'm in the process of doing something similar, to interface an old Kodak Ektapro high-speed camera > system (details www.electricstuff.co.uk/ektapro.html) > I've not yet looked into the USB2 aspect but like you am interested in getting the data to the PC at > a reasonable speed with a minimum of effort. > > You probably don't want to send all the data to the PC, and even if you do, doing it in real time is > going to be a major challenge. > > A better approach is probably going to be to use a FPGA to capture and store it in SDRAM, and then > download what you need to the PC , e.g. after cutting out the frames before/after the event of > interest, cropping the image etc. > It also means the PC interface does not need to acheive a particular speed to keep up, which will > remove a lot of constraints. > This assumes that you are capturing relatively short events - if you need continuous processing at > that rate you will need a BIG FPGA and do it all in hardware! > > Some of the higer-end Xilinx eval kits include SDRAM SIMM sockets > > Another thing that may be worth a look is a PCI FPGA board, which will give you plenty of bandwidth > into the PC. > > Incidantally, Micron also do a high-speed sensor that may be worth a look. If you want a ready-made system (camera with frame storage and USB2.0) using the Micron sensor (500 fps @ 1280 x 1024), look at: http://www.fast-vision.com/cameras/camera13.HTM This camera has Virtex-II internally with up to 1GB of DDR SDRAM for frame storage and flexible triggering options. By the way, throughput on high-speed USB 2.0 can only be sustained at about 48 MB/s so if you really want raw data to the PC you're limited to about 96K byte frames.Article: 88232
Very cool program. Evolutionary codes are pretty cool.... Just think you solved a problem by using random numbers. Congrats!Article: 88233
Dear all, I'm having some problems installing Xilinx ISE on a Gentoo system. It's the same problem that has plagued many other Linux ISE users: /mnt/cdrom/xilsetup: relocation error: /mnt/cdrom/bin/lin/libwinsock44.so: symbol h_errno, version GLIBC_2.0 not defined in file libc.so.6 with link time reference I've tried setting LD_ASSUME_KERNEL to 2.4.7, but it makes no difference (In fact it seems the xilinx setup script does this automatically anyway). If anyone else has managed to get ISE running on Gentoo I'd love to know how. I'm running a 2.6.12 kernel. Glibc is 2.3.5 Many Thanks AndyArticle: 88234
Summary
This document describes the correlation between publicly documented
logic, I/O, and routing resources within the Atmel AT40k/94k family
of chips and bits in the bitstreams needed to program them.
Our goal is to make this information available to the public without
restriction on its use, for the purpose of creating automated tools
which generate bitstreams.
Statement of Public Knowledge
The Knowledge encapsulated in this document was derived by formal
scientific experimentation, using only information generally
available to the public. Extreme care which has been taken to
ensure that the process did not violate any copyright, trademark,
trade secret, or patent statutes. No licensing contracts or
non-disclosure agreements were entered into by the parties involved
in this endeavor, nor did they have access to any confidential
information.
This document is part of the Public Domain; its authors surrender
claim to copyright on it.
Corrections
If you find errors in this document, please correct them and add the
date and a short description of the correction to the table below.
This will assist in merging changes made in disjoint derivitaves.
2005.08.12 [gosset] Initial revision
Background
The Atmel AT40k Datasheet describes in great detail the resources
available in the AT40k as well as the FPGA portion of the AT94k
(which is functionally identical and uses the same binary
configuration format).
The configuration space used to control these resources consists of
a collection of independent octets arranged in a sparse 24-bit
address space. This document correlates those bits with the
resources described in the Datasheet.
The process of configuring the device consists of writing these
octets into the configuration memory. Once the desired
configuration octets are known, the procedures for loading them into
configuration memory are well documented in Atmel Documents 1009 and
2313.
Each data octet "D" has a 24-bit address, divided into three address
octets "X", "Y", and "Z". In general, the X and Y address octets
are related to the physical position of the resource, while the Z
octet is related to the type of resource being addressed.
Notation
We will use the notation A->B to indicate that setting the
corresponding configuration bit high causes source A to drive wire
B, and the notation A<>B to indicate that a pass gate between A and
B is enabled. The notation ~A or ~A->B indicates a configuration
bit controlling A or causing A to drive B is *active low*
(inverted).
We will use the following terms to describe routing resources.
They vary slightly from Atmel's documentation, but are less
ambiguous.
X, Y, W, Z The cell's inputs
XO, YO The X and Y outputs from the cell (to its neighbors)
N, S, E, W Orthogonal lines: connections to neighboring cells
NE,SE,NW,SW Diagonal lines: connections to neighboring cells
S0..S4 Quad lines: four-cell long routing lines
H0..H4 Horizontal quad lines
V0..V4 Vertical quad lines
L0..L4 Switchbox ports: the wires joining FB,H0..H4,V0..V4,X,Y,Z,W
G0a..G4b Global lines: eight-cell long routing lines, in two sets (a+b)
FB The cell's internal feedback line
R The cell's internal register
C The cell's "center" output; can drive the X or Y outputs
ZM The "Z-mux"; the mux which drives the cell's register input
WM The "W-mux"; the mux which drives the third input to the LUTs
XL, YL The output of the X,Y-LUTs
IA The "internal and" gate (W & Z)
Cartesian Resources
Although the exact interpretation of the X and Y octets depends on
the resource type (Z octet), in most cases the X and Y octets are
the cartesian coordinates of the logic cell nearest to the desired
resource (0,0 is the lower-left hand logic cell). This section
describes the significance of the Z and D octets for such resources.
Notes:
- The most significant four bits of the Z octet are 0000 for these bits
- If WZ->WM and FB->WM are both low, then W->WM.
- If ZM->R and YL->R are both low, then the XL->R
- The ZM->C and ZM->FB bits are used to bypass the register (when high).
- ~SET bit controls the set/reset behavior of the register; 0=set, 1=reset
+----+--------+--------+--------+--------+--------+--------+--------+--------+
|Z3:0| D octet |
+----+--------+--------+--------+--------+--------+--------+--------+--------+
|0000| V4->L4 | H4->L4 | FB->L2 | FB->L3 | FB->L1 | FB->L0 | FB->L4 | 0 |
+----+--------+--------+--------+--------+--------+--------+--------+--------+
|0001| ZM->R | YL->R | WZ->WM | FB->WM | ZM->C | ZM->FB | C->XO | C->YO |
+----+--------+--------+--------+--------+--------+--------+--------+--------+
|0010| L4->Z | L4->Y | L3->Z | L2->Z | L1->Z | L0->Z | V4->OE | H4->OE |
+----+--------+--------+--------+--------+--------+--------+--------+--------+
|0011| L2->W | L3->W | L4->W | L4->X | L1->W | L0->W |H2a<>V2a|H3b<>V3b|
+----+--------+--------+--------+--------+--------+--------+--------+--------+
|0100| N->Y | S->Y | W->Y | E->Y | L3->Y | L2->Y | L1->Y | L0->Y |
+----+--------+--------+--------+--------+--------+--------+--------+--------+
|0101| SW->X | NE->X | SE->X | NW->X | L3->X | L2->X | L1->X | L0->X |
+----+--------+--------+--------+--------+--------+--------+--------+--------+
|0110| X-LUT truth table, inverted |
+----+--------+--------+--------+--------+--------+--------+--------+--------+
|0111| Y-LUT truth table, inverted |
+----+--------+--------+--------+--------+--------+--------+--------+--------+
|1000| V3->L3 | H3->L3 | H2->L2 | V2->L2 | V1->L1 | H1->L1 | V0->L0 | H0->L0 |
+----+--------+--------+--------+--------+--------+--------+--------+--------+
|1001|H1a<>V1a|H0a<>V0a|H0b<>V0b|H4a<>V4a|H4b<>V4b|H1b<>V1b|H3a<>V3a|H2b<>V2b|
+----+--------+--------+--------+--------+--------+--------+--------+--------+
...
+----+--------+--------+--------+--------+--------+--------+--------+--------+
|0001| 1 | 1 | 1 | 1 | ~SET | 1 | 1 | 1 |
+----+--------+--------+--------+--------+--------+--------+--------+--------+
Sector Resources
Clocking, reset, and inter-sector repeaters are resources which are
not specific to a particular cell. As such, their X,Y addressing is
slightly different. These resources are addressed by the cartesian
coordinates of the cell above or to the right of the resource, with
an additional twist: for resources in vertical channels, the
X-coordinate is shifted right by two bits (divided by four); for
resources in horizontal channels, the Y-coordinate is shifted right
by two bits (divided by four).
The most significant three bits of the Z-octet for a sector resource
are set to 001; the next bit (fourth most significant) is set to 0
for horizontal channels and 1 for vertical channels.
One sector wire and one global wire enter each side of each
repeater, for a total of four connections. Each connection has an
associated four-bit code which indicates if that connection is
driven by the repeater, and if so, which connection to the repeater
is used to drive it:
000 - driver disabled
100 - source is global wire on the other side of the repeater
010 - source is sector wire on the other side of the repeater
001 - source is other connection on the same side of the repeater
Example: a code of 001 for the left-hand side sector wire driver
means that the source of the driver should be the left hand side
global wire. A code of 010 for the top sector wire driver means that
the source of the driver should be the bottom sector wire.
CC = column clock
CR = column reset
SC = sector clock
CC+ = sector clock of the sector below this one
InvSC = invert the clock source (CC or S4) before driving SC
+----------+--------+--------+-----+-----+------+-----+-----+------+
| Z octet | D octet |
+----------+--------+--------+-----+-----+------+-----+-----+------+
| 001_0000 | 1 | 0 | Left/Top G4 | Left/Top S4 |
+----------+--------+--------+-----+-----+------+-----+-----+------+
| 001_0001 | 0 | S4->CR | Right/Bottom G4 | Right/Bottom S4 |
+----------+--------+--------+-----+-----+------+-----+-----+------+
| 001_0010 | 1 | 0 | Left/Top G3 | Left/Top S3 |
+----------+--------+--------+-----+-----+------+-----+-----+------+
| 001_0011 | 1 | 1 | Right/Bottom G3 | Right/Bottom S3 |
+----------+--------+--------+-----+-----+------+-----+-----+------+
| 001_0100 | 1 | 0 | Left/Top G2 | Left/Top S2 |
+----------+--------+--------+-----+-----+------+-----+-----+------+
| 001_0101 | SC->CC+| S3->SC | Right/Bottom G2 | Right/Bottom S2 |
+----------+--------+--------+-----+-----+------+-----+-----+------+
| 001_0110 | 1 | 0 | Left/Top G1 | Left/Top S1 |
+----------+--------+--------+-----+-----+------+-----+-----+------+
| 001_0111 | 1 | 1 | Right/Bottom G1 | Right/Bottom S1 |
+----------+--------+--------+-----+-----+------+-----+-----+------+
| 001_1000 | 1 | 0 | Left/Top G0 | Left/Top S0 |
+----------+--------+--------+-----+-----+------+-----+-----+------+
| 001_1001 | InvSC |~SC->CC+| Right/Bottom G0 | Right/Bottom S0 |
+----------+--------+--------+----+--------+----+-----+--------+---+
Block Memories
Although block memories are shown in the lower right hand corner of
each sector in the Atmel Datasheets, they are conceptually addressed
by the cartesian coordinate of the cell in the lower *left* hand
corner of the sector. Furthermore, both coordinates are shifted
right two bits (divided by four).
The significance of the "D" octet for a given block memory depends
on its position; if it falls in an odd sector-column (4-7, 12-15,
etc), use the first chart; otherwise, use the second chart.
USECLK = the memory is synchronous
ENABLE = the memory is enabled
DUAL = enable both ports on a dual-ported memory
Odd Sector-Columns
+--------+------+------+------+------+--------+--------+--------+---------+
|Z octet | D octet |
+--------+------+------+------+------+--------+---------+--------+--------+
|01000000| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+--------+------+------+------+------+--------+---------+--------+--------+
|01000001| 1 | 1 | 1 | 1 | USECLK | ~ENABLE | ENABLE | ENABLE |
+--------+------+------+------+------+--------+---------+--------+--------+
Even Sector-Columns
+--------+------+------+------+------+--------+--------+--------+--------+
|Z octet | D octet |
+--------+------+------+------+------+--------+--------+--------+--------+
|01000000| 1 | 1 | 1 | 1 | USECLK | DUAL | ~DUAL | ENABLE |
+--------+------+------+------+------+--------+--------+--------+--------+
|01000001| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+--------+------+------+------+------+--------+--------+--------+--------+
I/O Blocks
The Z octet for I/O resources always its most significant three bits
set to 011. The next two bits are either 01 for a primary IOB or 10
for a secondary.
S = Sector wires of this cell
S+ = Sector wires of next cell
S- = Sector wires of previous cell
G = Global wires of this cell
G+ = Global wires of next cell
Output = Allow output from this IOB
OE = when low, output is always enabled
OEM = 7 bits, one-hot encoded, chooses input to output-enable mux
USEOEM = when low, ignore the output enable mux
Delay = amount of delay to add; can be 0, 1, 3, or 5
Slew = slew time: 11=fast, 10=med, 01=slow
Pull = 00=pullup, 11=pulldown, 01=none
+--------+--------+--------+------+-------+-------+--------+--------+--------+
|Z octet | D octet |
+--------+--------+--------+------+-------+-------+--------+--------+--------+
|011__000| Schmit | Slew |~G2->CR| | Pull | |
+--------+--------+--------+------+-------+-------+--------+--------+--------+
|011__001|REG->OUT| | OE | Output Mux |
+--------+--------+--------+------+-------+-------+--------+--------+--------+
|011_0010| Added Delay (primary) |PRI->S-| PRI->G+| PRI->G | PRI->S |
+--------+--------+--------+------+-------+-------+--------+--------+--------+
|011_1010| Added Delay (secondary) |SND->S | SND->S+|PRI->REG|SND->REG|
+--------+--------+--------+------+-------+-------+--------+--------+--------+
|011__011| OEM | USEOEM | OEM |
+--------+--------+--------+------+-------+-------+--------+--------+--------+
Global Clock/Reset Networks
To drive a column clock from one of the eight global clock/reset
networks, set the corresponding bit in the desired column:
+--------+--------+--------+
|Z octet |X octet |Y octet |
+--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
|10100000| column |00000000| CK1 | CK2 | CK3 | CK4 | CK5 | CK6 | CK7 | CK8 |
+--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
Unknown
The following configuration resources are not fully understood, but
the values below appear to work.
+--------+--------+--------+
|Z octet |X octet |Y octet |
+--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
| |00000000|00000000| 1 | 1 | 1 | 1 | 1 | 1 | GCK SRC |
|10100001|00010111|00000000| 1 | 1 | 1 | 1 | 1 | 1 | GCK SRC |
| |00101111|00000000| 1 | 1 | 1 | 1 | 1 | 1 | GCK SRC |
+--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
|11010000|00000000|00000000| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
+--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
|11010011|00000000|00000000| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
+--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
Article: 88235On Fri, 12 Aug 2005 15:54:54 +0100, Andrew Greensted wrote: > Dear all, > > I'm having some problems installing Xilinx ISE on a Gentoo system. > > It's the same problem that has plagued many other Linux ISE users: > > /mnt/cdrom/xilsetup: relocation error: > /mnt/cdrom/bin/lin/libwinsock44.so: symbol h_errno, version GLIBC_2.0 > not defined in file libc.so.6 with link time reference > > I've tried setting LD_ASSUME_KERNEL to 2.4.7, but it makes no difference > (In fact it seems the xilinx setup script does this automatically anyway). > > If anyone else has managed to get ISE running on Gentoo I'd love to know > how. > > I'm running a 2.6.12 kernel. Glibc is 2.3.5 > > Many Thanks > Andy Don't know anything about Gentoo, I use Fedora, but you need to make sure that you have a set of legacy libraries installed. The Xilinx tools are targeted at an obsolete version of RHEL, RHEL 3. The installer in particular is very distribution sensitive although the tools themselves seem to work fine on modern distributions. I keep a copy of the Whitebox version of RHEL 3 on one of my machines. I do the installs there and then rsync the xilinx directory to my other machines that are running FC3.Article: 88236
Antti, All I will say is that we are working on all of your issues, and we take everyone of them seriously. Clearly, if you will not use the phone, that will make things harder, as sometimes it is best to just talk to the customer. Every hotline person is trained, and yes, the ones serving the basic service grade are newer than those who serve the premium service grade, but they are allowed to immediately escalate any issue directly to the next level. They do not have to go to the FAE for permission. It is encouraged to use the local FAE's just so that the customer has the best experience, and the local FAE stays in the loop, and is always aware of what his customer is doing. As for the original Macro issue, if I new something about software, I'd say something, but I do not. The hotline is absolutely the best source for information on the software. Unfortunately, it is postings like yours (that disparrage the webcase support) that encourage folks to email me directly with their problems, rather than open a webcase. That is terrible, as I can in no way compete with databases of tens of thousands of answers, 400 FAE's, and 200+ CAE's, and what they do very well. If you look at my performance in answering webcases, I would be absolutely horrible! So, do not email me with a specific case. Email me (or Peter) if a specific case is not being resolved to your satisfaction, or if you have been unable to get a question answered by the normal means. If anything, emailing me first will delay the response to your problem. AustinArticle: 88237
Praveen, BUFGMUX in xilinx devices is built in such way that it ensures synchronous clock muxing. Vladislav <praveen.kantharajapura@gmail.com> wrote in message news:1123849083.672840.141540@z14g2000cwz.googlegroups.com... > Hi all, > > I have got two high frequency clocks , i need to select one of them, > but while muxing the output clock(one of the two high will be gated). > > Is there any way to avoid this. > > Regards, > Prav >Article: 88238
"William Sealey Gosset" <wgosset@guiness.com> schrieb im Newsbeitrag news:20050812150910.29614.qmail@nym.alias.net... > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Summary > > This document describes the correlation between publicly documented > logic, I/O, and routing resources within the Atmel AT40k/94k family > of chips and bits in the bitstreams needed to program them. Way to go! Atmels FPGA tools JUST SUCK I still do have the FPSLIC starterkit download cable and even dongle laying aroung but never had much time. Well I started Atmel JBits library once, but that wasnt much finished, I may dig it out now. I can verify your public document as I do happen to have the original document, what I have actually obtained without signing NDA :), sure to the bottom end that doesnt change anything. I wonder if the soon to be announced FPSLIC-II has some new features as well or is just technology schrink and new package? Antti PS http://wiki.openchip.org/index.php/AT94K:Bitstream I like wiki to edit online documents :) PPS if you like I have one AT94K laying around (and conf memory for it too), I can send to you free or charge (the chip is older die revision without JTAG interface).Article: 88239
Stefan, My knowledge of SSC is pretty scarce, but from what I do remember, the problem you are facing is not trivially solvable (I hope I am wrong here) unless can obtain a direct or indirect information about the clock, which you are using as a sampling clock, correct? (and this is the problem!) Because if this is not a sampling clock... Again, I hope I am wrong. Vladislav "Stefan" <holzi_stefan@hotmaildotcom.nospam> wrote in message news:ddfq6e$hvn$1@wsc10.lrz-muenchen.de... > Hello Vladislav, > > the problem is that I cannot transfer data via my RF link. (in the end > this > is the aim...) I just transmit bursts of a 200 Mbit signal with a interval > of 3 us. These bursts contain data for a spread spectrum calculation, and > are only used with a analog correlator. To transmit data, I invert the > bits > from this burst and after that on the correlator the output is -1 (instead > of 1 before). > And for this purpose, I have to synchronize these 2 bursts. I just tried > to > use a DCM for clock generation, with no effect. > Really annoying... I got so far in this project and now this problem... > > Any suggestions? > > Regards, Stefan > > > > > > "Vladislav Muravin" <muravinv@advantech.ca> schrieb im Newsbeitrag > news:8wJKe.8472$yH2.405404@news20.bellglobal.com... >> Stefan, >> >> DLL with clock mirroring would eliminate a skew between the clocks, but >> if > I >> understand you correctly, you are facing not a simple issue, especially >> because you have 100 MHz and you want to use RF connection as a link. >> That >> is, you have to embed certain information in the outgoing data, such as > the >> information about your local clock. >> >> The common way to do this is to run, for example, 50-bit wide counter >> with >> 100 MHz clock in one end and transfer the value of the counter through >> the >> data to another end. In the another end, there is the same counter and > this >> value is compared with the one embedded in the data traffic. The > difference >> between the two gives you an estimation about the difference between the > two >> clocks. >> >> The rest depends on the device that you are using for clock generation >> and >> its crystal pullability or frequency range that you can use. >> If your clock would have been much slower, there is a way to do this >> using >> very high-speed clock & phase shift technique. >> >> If you could give a few more details.......... >> >> Hope this helps. >> Vladislav >> >> >> "Stefan" <holzi_stefan@hotmaildotcom.nospam> wrote in message >> news:ddfm7g$fuf$1@wsc10.lrz-muenchen.de... >> > Hello, >> > >> > does anybody know about clock accuracy - I need a very stable clock to >> > synchronize 2 devices via a RF connection. They must exactly have the > same >> > clock, at this time I'm using a 100 MHz clock generator and a Spartan-3 >> > fpga. But for my intended purpose it's not accurate enough. That means, > on >> > a >> > scope my generated data bursts of each device with a interval of 3 us > are >> > "running away" (that ones those aren't triggered). The 3 us intervals >> > differ >> > perhaps in half a ns or something. >> > Is there a practicable solution for such a problem? Does a DLL with > clock >> > mirroring eliminate the problem? >> > >> > Thanks in advance, >> > >> > Stefan >> > >> > >> >> > >Article: 88240
"austin" <austin@xilinx.com> schrieb im Newsbeitrag news:1123860161.490496.181160@g14g2000cwa.googlegroups.com... > Antti, > > All I will say is that we are working on all of your issues, and we > take everyone of them seriously. > > Clearly, if you will not use the phone, that will make things harder, > as sometimes it is best to just talk to the customer. > > Every hotline person is trained, and yes, the ones serving the basic > service grade are newer than those who serve the premium service grade, > but they are allowed to immediately escalate any issue directly to the > next level. They do not have to go to the FAE for permission. It is > encouraged to use the local FAE's just so that the customer has the > best experience, and the local FAE stays in the loop, and is always > aware of what his customer is doing. > > As for the original Macro issue, if I new something about software, I'd > say something, but I do not. The hotline is absolutely the best source > for information on the software. > > Unfortunately, it is postings like yours (that disparrage the webcase > support) that encourage folks to email me directly with their problems, > rather than open a webcase. That is terrible, as I can in no way > compete with databases of tens of thousands of answers, 400 FAE's, and > 200+ CAE's, and what they do very well. > > If you look at my performance in answering webcases, I would be > absolutely horrible! > > So, do not email me with a specific case. Email me (or Peter) if a > specific case is not being resolved to your satisfaction, or if you > have been unable to get a question answered by the normal means. > > If anything, emailing me first will delay the response to your problem. > > Austin > LOL, gosh I need a break. I do use and I am able to use phone, just my contact preferences is always set to email. And my mobile hasnt been switched off for some weeks, but I wasnt expecting any phone calls. Shit, I did not mean to piss off anyone or discourage the WebCase use, for vast majority of case I belive the WebCase support is just proper and superior also in timely responses. But I do not fall into the 'vast majority' category and in most/all cases where I encounter an issue its not trivial, so the WebCase response is not as immediate for me. I do belive that Xilinx does take the WebCases (every each of them) seriously, its the best way to get feadback and found out problems. As I have stated before the only BIG issue for me is the XCFxxP programming algorithm issue, I guess there is some weird silicon erratic behaviour that is compensated somehow in the impact internal programming algorithm, but that again makes the XCFxxP non programmable by any 3rd party tools. All other webcases are mostly of interest to Xilinx as fixing the issues means fixing bugs and making the SW better. AnttiArticle: 88241
>>It's the same problem that has plagued many other Linux ISE users: >> >>/mnt/cdrom/xilsetup: relocation error: >>/mnt/cdrom/bin/lin/libwinsock44.so: symbol h_errno, version GLIBC_2.0 >>not defined in file libc.so.6 with link time reference > Don't know anything about Gentoo, I use Fedora, but you need to make sure > that you have a set of legacy libraries installed. The Xilinx tools are > targeted at an obsolete version of RHEL, RHEL 3. The installer in > particular is very distribution sensitive although the tools themselves > seem to work fine on modern distributions. I keep a copy of the Whitebox > version of RHEL 3 on one of my machines. I do the installs there and then > rsync the xilinx directory to my other machines that are running FC3. Ahh... That's interesting. I'm just going through the motions of setting up an older glibc environment. But, if it's just the installer that requires this, then your solution sounds like a much easier alternative. I'll give it a try. ThanksArticle: 88242
Click on http://www.xilinx.com/xcell/xl24/xl24_20.pdf for a simple circuit that lets you switch asynchronously between two clocks. Never any glitches or runt pulses, even when the Select signal is totally asynchronous. Note that both incoming clocks must run continuously, since the circuit cannot switch away from a dead clock. Peter Alfke, XilinxArticle: 88243
Is there a freeware (or reasonable cost... i.e no annual renewal fee involved and a cost a hobbiest could afford) C compiler for the PicoBlaze available? I'd like to experiment with an embedded processor on a Spartan 3 (with the Xilinx development board) but prefer not to spend an arm-and-a-leg to get there :) Thanks DaveArticle: 88244
This issue is covered by Answer Record 21615. A patch is available. It will also be fixed in SP4. http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21615 Bret Wade Xilinx Product ApplicationsArticle: 88245
PeterC wrote:
>Thanks Peter, I appreciate your insight.
>
>The divider sounds most promising - 50 ppm frequency error is about as
>good as my 98.304 MHz source as you said. The next question I suppose
>is how best to do a divider by 2229?
>
>The obvious design would be a counter with the limit set to 2229 as
>this number is obviously not DCM friendly. This amounts to a 13 bit
>counter which would indeed be quite small. If you can suggest an even
>simpler way (or any other possible alternatives as to me the counter
>seems like to only way) I'd like to hear it (judging by your 6 easy
>pieces tech-xclusive you know a trick or two!).
>
>PeterC.
>
>
>
Rather than doing a limit compare, use a 13 bit loadable down-counter.
Load it with 2229-2 when the left bit='1' (which happens when the count
reaches -1). The sign bit is a one clock wide pulse. If you need a
wider pulse, you can use the next bit down (bit 11) which will be '0'
for 1024 clocks of the 2229 clock cycle. This way, there is no decoding
which uses up resources and slows the counter down.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 88246Dave wrote: > Is there a freeware (or reasonable cost... i.e no annual renewal fee > involved and a cost a hobbiest could afford) C compiler for the PicoBlaze > available? > > I'd like to experiment with an embedded processor on a Spartan 3 (with the > Xilinx development board) but prefer not to spend an arm-and-a-leg to get > there :) http://www.poderico.co.uk/PCCOMP.htmArticle: 88247
Andrew, THanks a lot for the link to the paper.I am trying to implement an error decoder in asynchronous logic.The fpga implementation is a proof of concept and the final translation would be custom design asic.I was also trying to recreate the new async methodology by the greek sync team(http://www.ics.forth.gr/about.html) THanks Vish Andrew FPGA wrote: > Hi Vish, > If you are wanting to detect the location of the most significant bit > then you may want to use a "propagate kill" circuit that maps very well > to the FPGA carry chain (at least in Xilinx anyway). I won't attempt to > describe it here, have a read of the following paper - page 6 in > particular. > > www.ece.byu.edu/faculty/nelson/research/pubs/fpl2002.pdf > google fpga propagate kill also returns this as top result. > > I think floating point arithmatic often needs to find the MSBit in the > normalise process so maybe a google on FPGA floating point designs may > find something. > > Out of interest, why are you trying to create an "asynchronous system"? > Research topic? I believe synchronous design techniques are more > appropriate if you are targetting an FPGA implementation.... > > > > backhus wrote: > > Hi Vish, > > In VHDL you can use the IF-ELSIF Statement. > > > > IF A = B THEN > > --do something > > ELSIF B = C THEN > > -- do something else, but only if a=b didnt match before > > ... > > ELSE > > -- do some default stuff if nothing else fits > > END IF; > > > > Depending on the deepth of this structure your design will become quite > > big and slow though. But the structure creates the priority dependance > > and if your compares are kept simple (only = and /=) and need only a > > small ammount of bits it may fit to your needs. > > > > have a nice synthesis > > eilert > > > > llabakdas@gmail.com schrieb: > > > +HI, > > > Is it possible to create a comparator structure that has a priority > > > structure eg My system has more than 65% cases where the winner is > > > determined by the msb(matlab simulations).I am trying to create an > > > asynchronous system, so early completion would be beneficial for my > > > system. > > > > > > > > > Essenatially i need a completion detection comparator. > > > > > > > > > THanks > > > Vish > > >Article: 88248
Thanks for all the replies. This is for very high volume production where cost and low-power are nearly everything. Which rules out (I think) pretty much all FPGA and CPLD solutions and may even marginalize structured ASIC solutions (not sure about this). Actually the more I think about it, the more I'm considering just buying die for the microcontroller and encapsulating all of our specialized glue logic in a small ASIC (we're looking at a few thousand gates tops). The plusses are that we won't be reinventing the wheel (as far as the micro goes, at least not in initial production we could always cost-reduce later). The micro may need to change for several different applications. Does anyone have any good ASIC fabs to suggest? Dave.Article: 88249
Dave, Don't rule out CoolRunner II. We are used in cell phones (to fix the ASIC bugs on a regular basis). Can not think of any tougher low power application than that. By the way, if you go to the cell phone ASIC vendor's websites, they detail all the errata, and all the little logic circuits needed to work around their bugs. Seems like we can get Coolrunner II designed into every first run of every cell phone pcb.... Not a bad business, fixing other people's ASIC goofs. Austin dave94024 wrote: > Thanks for all the replies. > > This is for very high volume production where cost and low-power are > nearly everything. Which rules out (I think) pretty much all FPGA and > CPLD solutions and may even marginalize structured ASIC solutions (not > sure about this). > > Actually the more I think about it, the more I'm considering just > buying die for the microcontroller and encapsulating all of our > specialized glue logic in a small ASIC (we're looking at a few thousand > gates tops). > > The plusses are that we won't be reinventing the wheel (as far as the > micro goes, at least not in initial production we could always > cost-reduce later). The micro may need to change for several different > applications. > > Does anyone have any good ASIC fabs to suggest? > > Dave. >
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