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I dont think real num format is supported. how do you suppose the WTIME of 43.03us will be represented as ? and what unit will it make of your "accum <= accum + '1' " ?Article: 88526
In verilog there is no concept of component declaration so no need to declare the module but the instantiation goes like this:- clk1440: CLK_1440_I ( async_reset.(BUS2IP_Reset), ----- ----- ); where the clk1440 is your actual module name and CLK_1440_I is an instance of it.Article: 88527
Sorry about the lack of details :) I need to compute an adress in a RAM given the following parameter : page group, page number and offset (so typically it's PG*page_size*number_pages + page_number*page_size + offset) The size of the page is 833 850. A group of page contains 16 pages, and there are up to 1024 pages. This computation does not work simply using Quartus (the output is too large) Then I split this adress in two, take the most significants bits to adress the RAM (in 8*64 bits) and the 9 less significants bits to adress in the data block (take one bit from the 8*64) The speed is not really an issue. The design works at 50 MHz, but I could use several clocks ticks to do this (actually I already use 4 for smaller size), but I could go to up to 20 without drawback. The design is supposed to work on a Cyclone EP1C20, speed grade 7 The solution I identified would be use megafunctions allowing more than 32 bits for the operands so I could do my computation and split without problem. But then I concerned with portability of the design A later solution would be to compress the data so the size of the page is smaller (at least 2 times) but it wouldn't be enough to come under the 32 bits limit. Thanks Nick On 21 Aug 2005 05:30:53 -0700, "Marc Randolph" <mrand@my-deja.com> wrote: >Nick wrote: >> Hello, >> >> I need to use large number (up to 12 774 182 400) in my design, bigger >> than a typical long. >> The question is : how can I do it ? And efficiently ? >> >> I could split the number in two parts, do the computations and the >> carry-bits, but i'm afraid it would be to much of a pain and I bet >> somebody already did it... > >Howdy Nick (although this reply would help mikelinyoho/frankgerlach22 >as well), > > The quality of the answers you get in comp.arch.fpga are usually >proportional to the amount of detailed information included in the >question. > >In your case, you have provided only two (mostly insignificant) pieces >of info: you have a single largish number and you want to do something >to it that might or might not involve some carry bits. > >To get a good answer, you'll need to explain what you are trying to do, >and if possible, why you are trying to do it. There are lots of very >sharp people in this newsgroup, and for open-ended questions like >these, they often identify solutions that the OP never even considered. > >In short, when asking a question in this newsgroup, you need to include >as much detail as possible: > >1. What's the 10,000 foot (high-level) view of what you're trying to >do? >2. What are the details (low-level view) of what you're trying to do? >3. What solution(s) have you already identified? > >4. What function(s) surround this one? >5. What's the interface to the surrounding functions >(speed/width/protocol)? > >6. Which vendor/part number/speed grade are you trying to use? >7. What clock speed(s) are being fed to the FPGA pins? >8. Is there a limit to the amount of time it can take to perform the >function? > >Have fun, > > MarcArticle: 88528
Hi Folks, in my ALTERA based cpld design (no on-chip pll) i need to low-jitter phase lock a frequency of 6.144 Mhz to a second frequency of 10 MHz. The greatest common divisor of these two numbers is 16000, so i use LPM_COUNTER with modulus 625 to divide the 10 MHz down to 16000 Hz and a modulus 384 LPM_COUNTER to divide the 6.144 MHz to 16000 Hz, everything ok up to this point. For low-jitter phase comparison usually a xor phase comparator is used. For a xor phase comparator i need the input signals to have an exact 1:1 duty cycle. Since the modulus counters generate only a short (1 clock) impulse when the modulus condition is given, i put a divide-by-two flip-flop behind each counter to produce a 8000 Hz 1:1 duty cycle signal. While this may work in reality, i get a QUARTUS warning saying that i drive clock inputs with gate outputs. This is clearly true because the modulus output decodes the counter states, but then: What is the "official" way to generate a 1:1 duty cycle signal out of a modulus counter that obeyes the rule that only clocks should feed clock inputs? TIA for your help Ulrich BangertArticle: 88529
I suppose you mean the FPGA's difference. Xilinx's FPGA is main-stream. It based on SRAM tech while Lattice's FPGA based on Flash tech. Which means Xilinx's FPGA have to be initilized before use and requires more dynamic current. But Flash-based FPGA have must have some short-coming. Something like not easy to write, etc. So it may requires higher cost. Anyone know more? All the best, DavyArticle: 88530
>While this may work in reality, i get a QUARTUS warning saying that i drive >clock inputs with gate outputs. This is clearly true because the modulus >output decodes the counter states, but then: What is the "official" way to >generate a 1:1 duty cycle signal out of a modulus counter that obeyes the >rule that only clocks should feed clock inputs? Use the one cycle wide pulse as a clock enable. Note that you have serious problem if you are using the output of a state decoder as a clock. It will be full of glitches. You can use it as a clock if you run it through a register. (Costs a cycle of pipeline delay.) It should work (without the extra register) as a clock enable as long as you can meet setup time. PS: Be sure to thank the software guys at Altera for saving you from debuging this in the lab. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 88531
you may change to another general IO and test it. maybe some IO were destroyed.. or the IO didn't have enouth ablity to driven the clk~!Article: 88532
Hi Jo! The Openwince tools support at least all non-USB versions of the cable: http://openwince.sourceforge.net/jtag/ If the API for the USB-cable is not available it would be very difficult to add support for that cable to openwince. But it should be possible to program the altera parts with any cable supported by openwince. BSDL for openwince has been added by Hein Röhrig: http://hein.roehrig.name/jtag/ Kolja Sulimma Jo Schambach schrieb: > Does anybody know how to program access to the Altera USB Blaster? I am > trying to port Altera's SRunner software, which currently only supports > a ByteBlaster II on a Windows environment to support the USB Blaster > (since this is the only download cable I have) on either Windows or Linux. > Any help would be appreciated, Altera does not seem to release the API. > > -- > Dr Joachim Schambach > The University of Texas at Austin > Department of Physics > 1 University Station C1600 > Austin, Texas 78712-0264, USA > Phone: (512) 471-1303; FAX: (814) 295-5111 > e-mail: jschamba@physics.utexas.eduArticle: 88533
Hello Hal, thank you for your advice. > Note that you have serious problem if you are using the output of > a state decoder as a clock. It will be full of glitches This is definitely not the case with the modulus output. I am well aware of glitches due to decoding counter states from the times when we used 7490s. The modulus output does not show this behavior, it is clean. That is why i thing that ALTERA did perhaps do a trick or two to avoid the glitches, perhaps enabling the decoded output on a negative clock edge or something like that. If this were the case (one cycle output from negative to negative edge) this were ok for use as a clock enable signal as you suggest. I will check it. Best regards Ulrich Bangert "Hal Murray" <hmurray@suespammers.org> schrieb im Newsbeitrag news:qpmdnZ2dnZ09rOGCnZ2dnYvulN6dnZ2dRVn-yJ2dnZ0@megapath.net... > >While this may work in reality, i get a QUARTUS warning saying that i drive > >clock inputs with gate outputs. This is clearly true because the modulus > >output decodes the counter states, but then: What is the "official" way to > >generate a 1:1 duty cycle signal out of a modulus counter that obeyes the > >rule that only clocks should feed clock inputs? > > Use the one cycle wide pulse as a clock enable. > > Note that you have serious problem if you are using the output of > a state decoder as a clock. It will be full of glitches. You > can use it as a clock if you run it through a register. (Costs > a cycle of pipeline delay.) > > It should work (without the extra register) as a clock enable > as long as you can meet setup time. > > PS: Be sure to thank the software guys at Altera for saving you > from debuging this in the lab. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 88534
"Neo" <zingafriend@yahoo.com> wrote in message news:1124689868.744720.73830@g43g2000cwa.googlegroups.com... > In verilog there is no concept of component declaration so no need to > declare the module but the instantiation goes like this:- > > clk1440: CLK_1440_I ( > async_reset.(BUS2IP_Reset), > ----- > ----- > ); > where the clk1440 is your actual module name and CLK_1440_I is an > instance of it. > Many Thanks MarcoArticle: 88535
Maybe someone can point me in the right direction: I need a Spartan development board (with about an XC3S1500) that supports slave parallel configuration. Futher features should include flash/PROM, SRAM and 2 UARTS. Can anyone suggest a board that satisfies some of the requirements? Thank youArticle: 88536
Hi, I am using ISE7.1i + SP3 target on a Virtex-4 FX12 fpga. The dual port block ram core generated by Coregen does not contain the initialization data defined in a .ceo file. The simulation using Modelsim is OK after I modified .v file to specify the correct .mif file. Anyone has same problem and how to solve? ThanksArticle: 88537
Davy wrote: > I suppose you mean the FPGA's difference. Xilinx's FPGA is main-stream. > It based on SRAM tech while Lattice's FPGA based on Flash tech. Which > means Xilinx's FPGA have to be initilized before use and requires more > dynamic current. But Flash-based FPGA have must have some short-coming. > Something like not easy to write, etc. So it may requires higher cost. > Anyone know more? > > All the best, > Davy I think the OP needs to say which of the many series of both vendors he is comparing. For example Lattice EC/ECP series vs Spartan 3, between which there are many fewer differences than with the flash-based parts you mentioned...Article: 88538
I expected it to truncate the 43.03 * 50 = 2151.5 to 2151. I expected for there to be a way to convert it to an integer constant so that it could be synthesized. I don't want floating point. I simply want to use the real constants so that when the clock speed is changed, the module can be simply updated to be the most accurate representation of that amount of `WTIME. I don't understand you question about accum <= accum + 1. That is simply a counter. This circuit will count until accum (an integer) >= `WTIME (a real constant I would like to be converted to an integer) and it will latch finished high and it will stop (until reset is triggered). I tried to use the $realtobits() system function to convert the constant to constant bits, but synthesizers don't recognize it. I should also add that by adding a wire and assigning the constant to it I got quartus do do proper synthesis: wire [11:0] wtime = `WTIME; then changing if(accum >= `WTIME) to if(accum >= wtime) The problem is, I need to do this with XST not Quartus and the technique I used in Quartus does not work in XST. Is this an XST bug? Thanks, ArlenArticle: 88539
Hi all,
The following piece of code works in functional simulation
--*************************************************************************
--This process is used to detect the start condition(I2C).
-- SDA is used as the clock for this purpose
--*************************************************************************
process(sda,sys_reset,current_i2c_state,scl)
begin
if(sys_reset='0' or current_i2c_state= I2C_HEADER)then
detect_start <= '0';
elsif(sda='0' and sda'event)then
if(scl/= '0')then
detect_start <= '1';
else
detect_start <= '0';
end if;
end if;
end process;
--**********************************************************--
In functional sim it works fine but when i do the timing simulation
even when the condition is satisfied the detct_start dosen't go high.
Note: This is the start detction logic for I2C .Since SCL and SDA are
externally pulled up '1' is converted to a 'Z'(not shown here).
But same is the case for funstional simulation.
the sda will aways be either '0' or 'Z' never a '1'.
I am using modelsim simuator to perform timing simulation .
and industry standard SDO file generated by altera.
Any suggestions appreciated.
Thanks in advance,
Praveen
Article: 88540
I checked all the warnings and none of them seem significant.
Ok, I'm trying to synthesize a design for an N-tap complex MAC FIR. The
design serially loads the complex coefficients (currently 64-taps) via
a 64 long, 16-bit word size shift register. Here is the synthesis blurb
of that unit:
Synthesizing Unit <srsipo>.
Related source file is
"/../../../Modeltech_6.0c/projects/espfep/work/srsipo.vhd".
Found 1024-bit register for signal <d_r>.
INFO:Xst:738 - HDL ADVISOR - 1024 flip-flops were inferred for signal
<d_r>. You may be trying to describe a RAM in a way that is
incompatible with block and distributed RAM resources available on
Xilinx devices, or with a specific template that is not supported.
Please review the Xilinx resources documentation and the XST user
manual for coding guidelines. Taking advantage of RAM resources will
lead to improved device usage and reduced synthesis time.
Summary:
inferred 1024 D-type flip-flop(s).
Unit <srsipo> synthesized.
Since I was worried about the size of this unit, I synthesized it alone
and noticed that it consumed very few slices/FFs (2%,4%), so I don't
think that this is the problem. This HDL ADVISOR message is just an FYI
correct? I do no believe I'd have any benefit from using the on-chip
RAM resources?
Anyway, here is the final report for the design.. if it helps.
=========================================================================
* Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name : mac_fircplx_wrapper.ngr
Top Level Output File Name : mac_fircplx_wrapper
Output Format : NGC
Optimization Goal : Area
Keep Hierarchy : NO
Design Statistics
# IOs : 102
Macro Statistics :
# Registers : 3651
# 1-bit register : 2817
# 16-bit register : 258
# 32-bit register : 256
# 33-bit register : 128
# 38-bit register : 128
# 6-bit register : 64
# Counters : 2
# 6-bit up counter : 2
# Multiplexers : 130
# 16-bit 64-to-1 multiplexer : 130
# Adders/Subtractors : 320
# 33-bit adder carry in : 128
# 38-bit adder : 128
# 6-bit subtractor : 64
# Multipliers : 256
# 16x16-bit multiplier : 256
# Xors : 128
# 1-bit xor3 : 128
Cell Usage :
# BELS : 159480
# BUF : 4
# GND : 1
# INV : 367
# LUT1 : 64
# LUT2 : 4304
# LUT3 : 73793
# LUT4 : 217
# MUXCY : 9164
# MUXF5 : 33281
# MUXF6 : 16640
# MUXF7 : 8320
# MUXF8 : 4160
# VCC : 1
# XORCY : 9164
# FlipFlops/Latches : 22611
# FDC : 130
# FDCE : 22114
# FDCPE : 15
# FDP : 64
# FDPE : 288
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 101
# IBUF : 67
# OBUF : 34
# MULTs : 256
# MULT18X18 : 256
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 2vp50ff1152-5
Number of Slices: 45523 out of 23616 192% (*)
Number of Slice Flip Flops: 22611 out of 47232 47%
Number of 4 input LUTs: 78378 out of 47232 165% (*)
Number of bonded IOBs: 102 out of 692 14%
Number of MULT18X18s: 256 out of 232 110% (*)
Number of GCLKs: 1 out of 16 6%
WARNING:Xst:1336 - (*) More than 100% of Device resources are used
=========================================================================
I'm not worried about the multiplier over-utilization. I'll probably
just reduce the number of taps once I get the other numbers down...
I've yet to find any info on the Xilinx cell primitives,i.e. what's the
difference between FDC, FDCE, FDP, etc.? Does anyone have any technical
documentation on these? If anyone is interested, I could provide a
design schematic...
Much thanks,
-Brandon
Article: 88541but i have have this problem and think that a small change somewhere will fix it. i have been using xilinx system generator to design a neural network for FPGA. it seems to synthesize and download properly. i have added a chipscope cores to check if it runs as expected on the FPGA however it complains when run that it has a slow or stopped clock. i interpret this to mean that system generator has not correctly generated the VHDL file or i have missed a step somewhere. please any pointers you have for this problem are appreciated. I am using xilinx system generator, Ise and chipscope Pro version 6.3i with updated ip. the device i am developing for is the virtex 2 pro XCV2p50.Article: 88542
Brandon wrote: > I checked all the warnings and none of them seem significant. > > Ok, I'm trying to synthesize a design for an N-tap complex MAC FIR. The > design serially loads the complex coefficients (currently 64-taps) via > a 64 long, 16-bit word size shift register. Here is the synthesis blurb > of that unit: > > Synthesizing Unit <srsipo>. > Related source file is > "/../../../Modeltech_6.0c/projects/espfep/work/srsipo.vhd". > Found 1024-bit register for signal <d_r>. > INFO:Xst:738 - HDL ADVISOR - 1024 flip-flops were inferred for signal > <d_r>. You may be trying to describe a RAM in a way that is > incompatible with block and distributed RAM resources available on > Xilinx devices, or with a specific template that is not supported. > Please review the Xilinx resources documentation and the XST user > manual for coding guidelines. Taking advantage of RAM resources will > lead to improved device usage and reduced synthesis time. > Summary: > inferred 1024 D-type flip-flop(s). > Unit <srsipo> synthesized. > > Since I was worried about the size of this unit, I synthesized it alone > and noticed that it consumed very few slices/FFs (2%,4%), so I don't > think that this is the problem. This HDL ADVISOR message is just an FYI > correct? I do no believe I'd have any benefit from using the on-chip > RAM resources? > > Anyway, here is the final report for the design.. if it helps. > > ========================================================================= > * Final Report > * > ========================================================================= > Final Results > RTL Top Level Output File Name : mac_fircplx_wrapper.ngr > Top Level Output File Name : mac_fircplx_wrapper > Output Format : NGC > Optimization Goal : Area > Keep Hierarchy : NO > > Design Statistics > # IOs : 102 > > Macro Statistics : > # Registers : 3651 > # 1-bit register : 2817 > # 16-bit register : 258 > # 32-bit register : 256 > # 33-bit register : 128 > # 38-bit register : 128 > # 6-bit register : 64 > # Counters : 2 > # 6-bit up counter : 2 > # Multiplexers : 130 > # 16-bit 64-to-1 multiplexer : 130 > # Adders/Subtractors : 320 > # 33-bit adder carry in : 128 > # 38-bit adder : 128 > # 6-bit subtractor : 64 > # Multipliers : 256 > # 16x16-bit multiplier : 256 > # Xors : 128 > # 1-bit xor3 : 128 > > Cell Usage : > # BELS : 159480 > # BUF : 4 > # GND : 1 > # INV : 367 > # LUT1 : 64 > # LUT2 : 4304 > # LUT3 : 73793 > # LUT4 : 217 > # MUXCY : 9164 > # MUXF5 : 33281 > # MUXF6 : 16640 > # MUXF7 : 8320 > # MUXF8 : 4160 > # VCC : 1 > # XORCY : 9164 > # FlipFlops/Latches : 22611 > # FDC : 130 > # FDCE : 22114 > # FDCPE : 15 > # FDP : 64 > # FDPE : 288 > # Clock Buffers : 1 > # BUFGP : 1 > # IO Buffers : 101 > # IBUF : 67 > # OBUF : 34 > # MULTs : 256 > # MULT18X18 : 256 > ========================================================================= > > Device utilization summary: > --------------------------- > > Selected Device : 2vp50ff1152-5 > > Number of Slices: 45523 out of 23616 192% (*) > Number of Slice Flip Flops: 22611 out of 47232 47% > Number of 4 input LUTs: 78378 out of 47232 165% (*) > Number of bonded IOBs: 102 out of 692 14% > Number of MULT18X18s: 256 out of 232 110% (*) > Number of GCLKs: 1 out of 16 6% > > WARNING:Xst:1336 - (*) More than 100% of Device resources are used > > > ========================================================================= > > I'm not worried about the multiplier over-utilization. I'll probably > just reduce the number of taps once I get the other numbers down... > I've yet to find any info on the Xilinx cell primitives,i.e. what's the > difference between FDC, FDCE, FDP, etc.? Does anyone have any technical > documentation on these? If anyone is interested, I could provide a > design schematic... > > Much thanks, > -Brandon There are 130 16 bit wide, 64-to-1 multiplexers in your design. That is where your excess logic utilization is comming from. What are they for? Each 64-to-1 mux is going to be 32 luts plus some MUXFXs per bit. 32*16*130 = 66560 Luts. Regards, John McCaskillArticle: 88543
praveen.kantharajapura@gmail.com wrote:
> -- process(sda,sys_reset,current_i2c_state,scl)
process(sda,sys_reset)
> begin
> -- if(sys_reset='0' or current_i2c_state= I2C_HEADER)then
if sys_reset='0' then
> detect_start <= '0';
> elsif(sda='0' and sda'event)then
> -- if(scl/= '0')then
if(scl/= '0'
and current_i2c_state /= I2C_HEADER) then
> detect_start <= '1';
> else
> detect_start <= '0';
> end if;
> end if;
> end process;
-- Mike Treseler
Article: 88544Austin Lesea schrieb: > I understand. Most regression test suites are huge designs intended to > cover as much ground as possible. Adding in a debounce ciruit as a > separate test isn't productive. Now having one "goofy" suite with ALL > of the strange and wonderful test cases that are three lines or less > would be useful.... > > Something to work towards. Especially as synthesis software tends to break with some parameter being unusually small. - ISE over a couple of versions could not handle designs that had no inputs. (The error message suggested that the design were to large) - The ISE schematic flow had a problem with vectors of length 1. - Magma Design Automations VHDL parser could not handle empty records in one version. - I saw a - non commercial - partition based placer fail on all single gate circuits because do-while was used instead of while-do And so on. These cases are not likely to show up in manual designs, but are actually very likely when working with circuit generators. I am doing synthesis research at an university and I always test extremely small cases first because the test cases are easy to come up with and show problems with programming that can hide in larger examples. Kolja SulimmaArticle: 88545
Kolja, Good points. Austin > Austin Lesea schrieb: > > >>I understand. Most regression test suites are huge designs intended to >>cover as much ground as possible. Adding in a debounce ciruit as a >>separate test isn't productive. Now having one "goofy" suite with ALL >>of the strange and wonderful test cases that are three lines or less >>would be useful.... >> >>Something to work towards. > > > Especially as synthesis software tends to break with some parameter > being unusually small. > > - ISE over a couple of versions could not handle designs that had no > inputs. (The error message suggested that the design were to large) > - The ISE schematic flow had a problem with vectors of length 1. > - Magma Design Automations VHDL parser could not handle empty records in > one version. > - I saw a - non commercial - partition based placer fail on all single > gate circuits because do-while was used instead of while-do > > And so on. > > These cases are not likely to show up in manual designs, but are > actually very likely when working with circuit generators. > > I am doing synthesis research at an university and I always test > extremely small cases first because the test cases are easy to come up > with and show problems with programming that can hide in larger examples. > > Kolja Sulimma > >Article: 88546
Regards: I use "Icarus Verilog" as a synthesis and simulation tool.But How can I see the waveform of my verilog codes? thank you may goodness be with you allArticle: 88547
See if you can use simple concatenation instead of most of your computations... /Mikhail "Nick" <nick@no-domain> wrote in message news:luoig1d0a1qrlj95qflg0tvqnck7g5nidr@4ax.com... > Sorry about the lack of details :) > > I need to compute an adress in a RAM given the following parameter : > page group, page number and offset (so typically it's > PG*page_size*number_pages + page_number*page_size + offset) > The size of the page is 833 850. > A group of page contains 16 pages, and there are up to 1024 pages. > > This computation does not work simply using Quartus (the output is too > large) > > Then I split this adress in two, take the most significants bits to > adress the RAM (in 8*64 bits) and the 9 less significants bits to > adress in the data block (take one bit from the 8*64) > > The speed is not really an issue. The design works at 50 MHz, but I > could use several clocks ticks to do this (actually I already use 4 > for smaller size), but I could go to up to 20 without drawback. > > The design is supposed to work on a Cyclone EP1C20, speed grade 7 > > The solution I identified would be use megafunctions allowing more > than 32 bits for the operands so I could do my computation and split > without problem. But then I concerned with portability of the design > > A later solution would be to compress the data so the size of the page > is smaller (at least 2 times) but it wouldn't be enough to come under > the 32 bits limit. > > Thanks > Nick > > On 21 Aug 2005 05:30:53 -0700, "Marc Randolph" <mrand@my-deja.com> > wrote: > > >Nick wrote: > >> Hello, > >> > >> I need to use large number (up to 12 774 182 400) in my design, bigger > >> than a typical long. > >> The question is : how can I do it ? And efficiently ? > >> > >> I could split the number in two parts, do the computations and the > >> carry-bits, but i'm afraid it would be to much of a pain and I bet > >> somebody already did it... > > > >Howdy Nick (although this reply would help mikelinyoho/frankgerlach22 > >as well), > > > > The quality of the answers you get in comp.arch.fpga are usually > >proportional to the amount of detailed information included in the > >question. > > > >In your case, you have provided only two (mostly insignificant) pieces > >of info: you have a single largish number and you want to do something > >to it that might or might not involve some carry bits. > > > >To get a good answer, you'll need to explain what you are trying to do, > >and if possible, why you are trying to do it. There are lots of very > >sharp people in this newsgroup, and for open-ended questions like > >these, they often identify solutions that the OP never even considered. > > > >In short, when asking a question in this newsgroup, you need to include > >as much detail as possible: > > > >1. What's the 10,000 foot (high-level) view of what you're trying to > >do? > >2. What are the details (low-level view) of what you're trying to do? > >3. What solution(s) have you already identified? > > > >4. What function(s) surround this one? > >5. What's the interface to the surrounding functions > >(speed/width/protocol)? > > > >6. Which vendor/part number/speed grade are you trying to use? > >7. What clock speed(s) are being fed to the FPGA pins? > >8. Is there a limit to the amount of time it can take to perform the > >function? > > > >Have fun, > > > > Marc >Article: 88548
I believe it is the xilinx "libraries guide" you are after for FDC, FDCE etc documentation. Look in the ISE install directory and you should find it under xilinx\doc\usenglish\books\docs\lib\lib.pf. Or in ISE 7.x go to Help->online documentation, then in left hand pane you will see "libraries guide". What is the sample rate and number of bits in your input data? You may have already considered it but a "distributed arithmetic" filter uses much less FPGA resources than a fully parallel filter. The cost is in sample rate. A distributed arithmetic approach to the FIR filter allows you to trade off sample rate and FPGA resource usage. Regards AndrewArticle: 88549
mikelinyoho wrote: > Regards: > > I use "Icarus Verilog" as a synthesis and simulation tool.But How can I > see the waveform of my verilog codes? I suppose you didn't read the Icarus Verilog FAQ: http://www.icarus.com/eda/verilog/FAQ.html Scroll down to the part where it says: "I want pretty pictures (wave forms) of my simulation run." I further suppose that you could have asked this question in comp.lang.verilog. -a
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