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Hallo, I'm simulating a peripheral into modelsim. I have watched some differences between: behavioral, post-translate, post-map, post-place simulations. Using post-place simulation, the peripheral works well into modelsim. Instead, if I use post-map, modelsim shows some warnings like this: # Time: 299133929 ps Iteration: 7 Instance: /wave/uut/adc_ram_addr_write_0_1_399 # ** Warning: /X_LATCHE HOLD Low VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.381 ns; Observed := 0 ns; At : 299133.929 ns Then into behavioral simulation some signal are not initialized, even if I do it in vhdl file. Why my system works well into a more real simulation? I think it should be the opposite. It should works well into behavioral, and less well into post-place... Many Thanks MarcoArticle: 89001
? Anyone bothered to do a simulation? IBIS, or hspice? Flying or driving blind is not recommended. Back of envelope calculations are worthless. Austin huangjie wrote: > Thanks for John_H 's replay ! > I will continue use spartan3 since your boards can run well. > Any one know how Xilinx calclate the SSO number ? > Use the following formula ? > Vgnd = L * 1.52* deltaV *C / (( T(10%-90%))^2) ? > I found this in book <<High Speed Digital Design>> (Section 2.4.1.4 ). > Xilinx may be use it because this formula is linear for L and C that > mentioned in xapp689 by xilinx. > When I read xapp689, I thought Xilinx maybe make some mistake in > calclating SSO number for PCI > because PCI has no capacitance load while they use capacitance. > There perhaps some other mistake in calculate the SSO number . Because > the higher package inductance > the slower ouput. So package inductance is not the most significant > factor . > Though I write these and post it , I am not know if it is right . > > Thanks to anyone for any words! >Article: 89002
My understanding is "no." Consider System Verilog if you "have" to use multi-dimensional input/output ports. The method Verilog designers often use is to make a multi-dimensional port into a simple vector, pass tha vector, then change the vector back to the multi-dimensional port. "vssumesh" <vssumesh_asic@yahoo.com> wrote in message news:1125654950.934300.218330@f14g2000cwb.googlegroups.com... > Hello all > Is it possible to instantiate multi dimensional input/output port in > verilog2001. > I tried the following code. > > module A(in,out); > input [7:0]in[7:0]; > output [7:0]out[7:0]; > > but it did gave an error in the Xilinx ISE 6.2.... > > Sumesh >Article: 89003
Isn't there a limited warranty printed on the CD jacket pushing responsibility of a bad CD back onto the publisher? The book distributor doesn't have that responsibility. And you *have* tried reading the CD on another machine, right? "Gra" <spamless-news@wildpossum.com> wrote in message news:df8t6b$4ui$1@nnrp.waia.asn.au... > Hi All. > > First off - Apologies if anyone considers this not the place to post such > information - but I am getting desperate. > > I am self-studying the book "Advance Digital Design with the Verilog HDL" by > Michael D. Ciletti. Unfortunately the original CD supplied with the book > was blank. So I went back to the local book distributor and after waiting > some weeks got a replacement. The replacement CD has several sector errors > and refuses to load at about half way through installation. The local > distributor now doesn't want to know me or about my problem, Even after I > paid ~15% of my weekly wage on his product. > > I would like to ask anyone who has the same CD, if they would kindly supply > me with a copy PLEASE (either they can ftp it to my home server or cut the > CD and mail it to me via snail mail) whatever means of getting it to me > would let me get further into my studies without more holdups. > > I have checked with the s/w originator - www.simucad.com unfortunately they > no longer distribute this s/w for free so I have hit the "wall". > > So, is their anyone out in web-world willing & able to assist me. > I'd be most appreciative of a working replacement CD. > > Much thanks. > -- > Cheers Grahame. at wildpossum dot comArticle: 89004
It depends on the mode as to whether the CCLK is an input or an output, hence this dedicated pin is not a dedicated input. "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:hcafh1pvcg7he15pq9rfetdhj6e5ie4kvl@4ax.com... > On Thu, 01 Sep 2005 18:09:55 GMT, "John_H" <johnhandwork@mail.com> > wrote: > > >The current through pullup resistors for dedicated pins at Vcco of 3.3V is > >up to 2.35 mA per device according to the Spartan-3 FPGA Family: DC and > >Switching Characteristics (v1.6) datasheet, Table 6. > > > >These signals are probably only pulled high when the HSWAP_EN pin indicates > >pullups should be used in the unconfigured state. > > > >The Spartan-3 is - as far as I know - the only family with these strong > >pullups; the Spartan-3E devices are back to the weaker pullups typical of > >other Xilinx devices. > > > > > > OK, thanks a lot. I never would have suspected a dedicated CMOS clock > input of having/needing a pullup! At least nothing's broke. > > John > > > >Article: 89005
I just installed and updated both the EDK and ISE 7.1 I'm using the XUP Virtex-II Pro, and downloaded the accompanying BSB package. When I generate a design using BSB (selecting the XUP as a design platform of course) I notice two things: A second DDR memory is added to the peripheral list, altough I have no idea where it comes from and what it does (it's called DDR-DRAM<something>). However, the biggest problem is that I cannot start the bitstream generation, it quits immediatly with: ERROR:MDT - Invalid target architecture 'xc2vp30ff896-7' ERROR:MDT - Invalid target architecture '' ERROR:MDT - platgen failed with errors! make: *** [implementation/system.bmm] Error 2 Done. How can I fix this? Any help would be appreciated.Article: 89006
Thanks john for your replay... i will follow that way. I am not familier with system verilog. What is the difference with normal verilog. Can i use it on the tool chain (model sim xilinx etc) and get the same output.Article: 89007
Hello all Is there any algortihm by which i can combine 8 bit multipliers using adders and shifters to get 16 or 32 bit multipliers. In unsigned i think the solution is direct but what in the signed mode how can i achive this. Sumesh V SArticle: 89008
Sorry about that last message. It deleted it on me for some reason. Anyway. I have the same book. I tried my CD in a couple of drives. Mine doesn't work either. But the CD is provided as-is. I would consider the CD quite unnecessary. I would suggest you try one of two things: 1. Download Modelsim XE starter from Xilinx and use that. It's much better than Silos and much less limited. 2. Download/build gpl cver and gtkwave. I consider this easier to get started with, but it's definitely less nice and slower than Modelsim. If the design is sufficiently large (> 10000 lines), this will be faster than Modelsim starter, but odds are if you're just now learning digital design/verilog, your designs won't pass that limit unless you're doing post P & R sims. Good luck, Arlen John_H wrote: > Isn't there a limited warranty printed on the CD jacket pushing > responsibility of a bad CD back onto the publisher? The book distributor > doesn't have that responsibility. > > And you *have* tried reading the CD on another machine, right? > > > > "Gra" <spamless-news@wildpossum.com> wrote in message > news:df8t6b$4ui$1@nnrp.waia.asn.au... > > Hi All. > > > > First off - Apologies if anyone considers this not the place to post such > > information - but I am getting desperate. > > > > I am self-studying the book "Advance Digital Design with the Verilog HDL" > by > > Michael D. Ciletti. Unfortunately the original CD supplied with the book > > was blank. So I went back to the local book distributor and after waiting > > some weeks got a replacement. The replacement CD has several sector errors > > and refuses to load at about half way through installation. The local > > distributor now doesn't want to know me or about my problem, Even after I > > paid ~15% of my weekly wage on his product. > > > > I would like to ask anyone who has the same CD, if they would kindly > supply > > me with a copy PLEASE (either they can ftp it to my home server or cut the > > CD and mail it to me via snail mail) whatever means of getting it to me > > would let me get further into my studies without more holdups. > > > > I have checked with the s/w originator - www.simucad.com unfortunately > they > > no longer distribute this s/w for free so I have hit the "wall". > > > > So, is their anyone out in web-world willing & able to assist me. > > I'd be most appreciative of a working replacement CD. > > > > Much thanks. > > -- > > Cheers Grahame. at wildpossum dot comArticle: 89009
The Xilinx application notes that IBIS files and IBIS derived results UNDER NO CIRCUMSTANCES will produce SSO information because there is no modeling of the chip's power and ground distribution. Do we have spice models available to us that *do* provide power/ground modeling? We were only flying blind for the first year or so before Xilinx started publishing numbers for the package and for the I/O standard that were absent in several early generations of the datasheet. We worked closely with our Xilinx FAE to develop a reasonable pinout for the PQ208 package. There were no warnings along the way that the PCI SSO limits would be 2 pins per bank for a 50 pin interface. I believe our first PCI/PQ208 design was shipping before the information first appeared in a datasheet. Mine is the 4th internal PCI design in this package that I know of and the Spartan3 is becoming "mature" for the typical design issues associated with a part. My case # is 597160 if you'd like to track down the active case to see what's going on. We're working with about 20 SSOs possible per bank rather than the 2 that are given by the guideline. Is this 10:1 difference expected in the SSO guidelines? "Austin Lesea" <austin@xilinx.com> wrote in message news:df9pt3$2181@cliff.xsj.xilinx.com... > ? > > Anyone bothered to do a simulation? > > IBIS, or hspice? > > Flying or driving blind is not recommended. > > Back of envelope calculations are worthless. > > Austin > > huangjie wrote: > > > Thanks for John_H 's replay ! > > I will continue use spartan3 since your boards can run well. > > Any one know how Xilinx calclate the SSO number ? > > Use the following formula ? > > Vgnd = L * 1.52* deltaV *C / (( T(10%-90%))^2) ? > > I found this in book <<High Speed Digital Design>> (Section 2.4.1.4 ). > > Xilinx may be use it because this formula is linear for L and C that > > mentioned in xapp689 by xilinx. > > When I read xapp689, I thought Xilinx maybe make some mistake in > > calclating SSO number for PCI > > because PCI has no capacitance load while they use capacitance. > > There perhaps some other mistake in calculate the SSO number . Because > > the higher package inductance > > the slower ouput. So package inductance is not the most significant > > factor . > > Though I write these and post it , I am not know if it is right . > > > > Thanks to anyone for any words! > >Article: 89010
What do you mean by the peripheral list? That's what the target architecture should be. Never run across either of these--can you post the *.mhs and *.xmp files? Paul "zoinks@mytrashmail.com" wrote: > > I just installed and updated both the EDK and ISE 7.1 > I'm using the XUP Virtex-II Pro, and downloaded the accompanying BSB > package. > > When I generate a design using BSB (selecting the XUP as a design > platform of course) I notice two things: > > A second DDR memory is added to the peripheral list, altough I have no > idea where it comes from and what it does (it's called > DDR-DRAM<something>). However, the biggest problem is that I cannot > start the bitstream generation, it quits immediatly with: > > ERROR:MDT - Invalid target architecture 'xc2vp30ff896-7' > ERROR:MDT - Invalid target architecture '' > ERROR:MDT - platgen failed with errors! > make: *** [implementation/system.bmm] Error 2 > Done. > > How can I fix this? Any help would be appreciated.Article: 89011
vssumesh wrote: > Thanks john for your replay... i will follow that way. > I am not familier with system verilog. What is the difference with > normal verilog. Can i use it on the tool chain (model sim xilinx etc) > and get the same output. The difference Verilog and System Verilog is that your toolset (XST) doesn't support System Verilog :( You could try VHDL; multidimensional arrays have been supported on ports for synthesis for a long time. Only kidding. John's suggestion of a 1 dimensional port is probably the best for you. Regards, AllanArticle: 89012
<denizdikmen@gmail.com> schrieb im Newsbeitrag news:1125575027.735673.124800@g44g2000cwa.googlegroups.com... > Hello, > > I want to connect a LED with Uf=1.8V and If=20mA to a CPLD (XC2C512). > But from the datasheet I get that the current is limited to I_OH and > I_OL = 8mA. Is this right? Means this that I couldn't use this LED with > 1.8V? Have I to operate the LED with 8mA and the corresponding voltage > (using a resistor in series)? You can easyly drive a 20mA LED with the Coolrunner-II. The current given in the datasheet is the guarenteed maximum under certain measurement conditions (Rise time, output LOW/HIGH level). For a LED this doesnt matter at all. There is a typical I/O curve in the datasheet, from there you can see that the output resistance is ~25 ohm. So if you draw 20mA, the output voltage will be 0.5V away from GND or VCC (depending if you sink or source the current). Just go ahead, calculate the appropiate current limiting resistor value and drive the LED with 20mA. Only keep in mind that you should not drive a logic inputs with this LED in parallel, since the the output voltages ar not more full specification compliant (but it will work thou) Regards FalkArticle: 89013
<alan@nishioka.com> schrieb im Newsbeitrag news:1125649231.259165.250930@g43g2000cwa.googlegroups.com... > I2C is an open-collector bus with a resistor pullup. > So the falling edge is sharp and the rising edge is exponential. > > I would guess that the rising edge is too slow and is causing problems > for your input buffer at the input threshold. Yes, you should use the schmitt trigger option for the input (if it is a coolrunner-II) I2C is terribly slow for nowadays CPLDs, so a rising edge can (and WILL) have enough noise on it to make the CPLD see double edges. I also suggest to NOT use SCL directly as a clock (for the given reason). Use a "high speed" (lets say 10 MHz) clock to sample SDA/SCL and make your state machine rung on this 10 MHz clock using the samples SDA/SCL. Regards FalkArticle: 89014
"Pierre de Vos" <pierre.devos@webmail.co.za> schrieb im Newsbeitrag news:df2g0c$cji$1@ctb-nnrp2.saix.net... > Hi, > > I've been struggeling with a long standing problem driving a 320x240 graphic > LCD display. I've been using a LCD module with an Epson SED1335 controller > chip. In my application the controller is quite susceptible to noise - it > resets for no reason, exibits distortion of the image. Googling has come up > with some other people also having similar symptoms with this controller. > > I have mostly overcome the problem by adding additional filtering to the > module - extra caps, ferrite on the cable, but the problem sometimes > persists. You have a basic supply and noise problem. Just "adding ferrites and caps" doesnt solve it. You have to place the caps of the right type on the right place. Place 100nF ceramic cap close to VCC/GND of your module. Close means, make the wires shorter than 1/2 inch. Also place a 10uF electrolytic cap close to VCC/GND. Wire lenght can be longer, but keep it shorter than 2 inch. Make a good ground connection beteen the FPGA board and the LCD. A not too thin wire will do. Add 100pF to reset inputs of the LCD. This will catch spikes. Are all input pins of the LCD tied to a fixed voltage (VCC/GND)? Do not leave inputs open, unless is is guarenteed that they have internal pull resistors. Good luck Regards FalkArticle: 89015
John_h Wrote "My case # is 597160 if you'd like to track down the active case to see what's going on". Where to find more information about case # 597160 ?Article: 89016
http://www.xilinx.com/xlnx/xil_entry2.jsp?sMode=login&group=mysupport Login, and find out what the case notes are. Who is handling it, and what they know so far. You can get in there, and EDIT it, and add information to your case! You can be in control and "drive" the support! Go for it! Austin huangjie wrote: > John_h Wrote "My case # is 597160 if you'd like to track down the > active case to see > what's going on". > Where to find more information about case # 597160 ? >Article: 89017
When you go to simulate your code, you can either create a testbench
manually in a text file, but since you are using the WebPack tools,
they have created a gui where you set your inputs to your modules
graphically...there is also a line you drag to determine the length of
the simulation...it is default at t=0. Have you moved that?
learnfpga wrote:
> Hello Everyone,
> I am new to Xilinx and the whole FPGA thing and this might be a very
> stupid problem that I am facing. Anyways Here it goes. I am trying to
> write a simple counter program using ISE Webpack 7.1. I write the code
> using language templates (verilog)then I check the syntax and
> everything is fine till this point.
>
> Then I make a testbench wave form and I can also see the expected
> results dialog box. Next step is I use ModelSim XE starter free version
> to simulate behavioural model. It opens up ModelSim automatically and
> this is where after running for a few seconds it stops. Below are the
> few messages that I am posting.......
>
> Basically in the tfw window in ModelSim it stops at $stop;. Please see
> below.
>
> Is there something that I am missing. Thanks a lot in advance.
> THIS IS TBCounter.tfw WINDOW
>
> module TBCounter_3try;
> reg CLOCK = 1'b0;
> reg DIRECTION = 1'b0;
> wire [3:0] COUNT_OUT;
>
> parameter PERIOD = 40;
> parameter real DUTY_CYCLE = 0.5;
> parameter OFFSET = 200;
>
> initial // Clock process for CLOCK
> begin
> #OFFSET;
> forever
> begin
> CLOCK = 1'b0;
> #(PERIOD-(PERIOD*DUTY_CYCLE)) CLOCK = 1'b1;
> #(PERIOD*DUTY_CYCLE);
> end
> end
>
> counter UUT (
> .CLOCK(CLOCK),
> .DIRECTION(DIRECTION),
> .COUNT_OUT(COUNT_OUT));
>
> integer TX_ERROR = 0;
>
> initial begin // Open the results file...
> #2040 // Final time: 2040 ns
> if (TX_ERROR == 0) begin
> $display("No errors or warnings.");
> end else begin
> $display("%d errors found in simulation.",
> TX_ERROR);
> end
> $stop;
> end
>
> initial begin
> // ------------- Current Time: 290ns
> #290;
> DIRECTION = 1'b1;
>
>
>
>
>
>
>
>
> THIS IS IN THE TRANSCRIPTS WINDOW
> # Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
> # do TBCounter_3try.fdo
> # ** Warning: (vlib-34) Library already exists at "work".
> # Model Technology ModelSim XE III vlog 6.0a Compiler 2004.11 Nov 10
> 2004
> # -- Compiling module counter
> #
> # Top level modules:
> # counter
> # Model Technology ModelSim XE III vlog 6.0a Compiler 2004.11 Nov 10
> 2004
> # -- Compiling module TBCounter_3try
> #
> # Top level modules:
> # TBCounter_3try
> # Model Technology ModelSim XE III vlog 6.0a Compiler 2004.11 Nov 10
> 2004
> # -- Compiling module glbl
> #
> # Top level modules:
> # glbl
> # vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps
> TBCounter_3try glbl
> # Loading work.TBCounter_3try
> # Loading work.counter
> # Loading work.glbl
> # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
> # .main_pane.workspace
> # .main_pane.signals.interior.cs
> # No errors or warnings.
> # Break at TBCounter_3try.tfw line 55
> # Simulation Breakpoint: Break at TBCounter_3try.tfw line 55
> # MACRO ./TBCounter_3try.fdo PAUSED at line 14
Article: 89018Hello, I'm designing a board with DDR and QDR II memories. When I look at the memory design reference of the FPGA manufacturers, all the signals are terminated by resistors. But when I look at the memory manufacturers app notes they say that in the case of single memory chip (point to point) configuration only a source resistor is needed. As modern FPGAs have builtin controlled source impedance there should be not resistor at all. (QDRII memories have controlled drivers too) So who is right here? (And yes, I will have the design simulated before producing the boards anyway ;-) MarcArticle: 89019
Hi
After searching more than 3 hours the web, awincupl.exe was found to
compile some CUPL code.
Personally I find it to bugy, so if there is any better suite to get a
.jed file I would appreciate the information.
The programm for a g16v8 needs to have 1 input to decode 8 outputs,
unfortunatelly the code attached does not give the right output
signals. That is, when 0 give as output 00100000 when 1 give as outs a
01000100;
The code was loaded to 2 GALs and the do exactly the same errors. I
tried diferent programmers with the same results.
Could someone please tell me what I'm doing wrong?
Best Regards and Thank you
Code:
Name IO ;
PartNo 00 ;
Date 9/2/2005 ;
Revision 01 ;
Designer Engineer ;
Company None ;
Assembly None ;
Location ;
Device g16v8 ;
/* *************** INPUT PINS *********************/
/* PIN 1 = CLK; */
PIN 1 = IN;
/* *************** OUTPUT PINS *********************/
PIN 19 = !ADR6 ; /* */
PIN 18 = !ADR5 ; /* */
PIN 17 = !ADR4 ; /* */
PIN 16 = !ADR3 ; /* */
PIN 15 = !ADR2 ; /* */
PIN 14 = !WR ; /* */
PIN 13 = !RD ; /* */
PIN 12 = !SEL ; /* */
/*
* Logic: examples of simple gates expressed in CUPL
*/
FIELD input = [IN];
FIELD output = [!SEL, !RD, !WR, !ADR2, !ADR3, !ADR4, !ADR5, !ADR6];
TABLE input => output{
0 => 'b'00100000;
1 => 'b'01000100;
}
Article: 89020Petter Gustad wrote: > "Eric" <ericjohnholland@hotmail.com> writes: > > >>"...Altera continues to sell Excalibur devices, this product family > > > Excalibur does not have a 3Gbps serdes. > > But what about the NIOS-II in a Stratix GX? > > Petter But, then it wouldn't have an "embedded processor comparable to the PowerPC 405". :-) EdArticle: 89021
Hey Folks,
i have a question about the RAM instantiations for the
Spartan 3(XC3S200) in the Xilinx verilog templates. You can instantiate
different types of SRAM sizes and bit widths, like 16K x 1, 2K x 8,
512K x 32, but what if a user wants use the SRAM in a 256K x 16 format,
or something else not displayed in the templates?. Can this be done ??
Also, the clock parameter (clk) in the instantiations, does this neeed
to be 100 Mhz, same as the SRAM clock frequency?. Do i need to use the
DCM to double the FPGA clock frequency?.
Thanks !!!
Article: 89022
vssumesh wrote:
>Hello all
>Is there any algortihm by which i can combine 8 bit multipliers using
>adders and shifters to get 16 or 32 bit multipliers. In unsigned i
>think the solution is direct but what in the signed mode how can i
>achive this.
>Sumesh V S
>
>
>
first, for unsigned, use the same technique you use for multiplication
by hand. Each 8 bit multiplier represents a digit multiplier where your
digits are each 8 bits (each digit can take on 256 different values).
Every digit needs to multiply every other digit to form partial
products. You add those partial products together after weighting them
with the combined digit weights of the inputs. For a 16x16 multiply
using 8 bit multipliers:
a= a[1]*256+a[0], b= b[1]*256+b[0]
a*b = a[1]*b[1]*256*256 + (a[1]*b[0] + a[0]*b[1])*256 + a[0]*b[0]
For signed multiplication, it is similar, except you use signed
multipliers only for the left-most digit of each multiplicand, and
unsigned for the remaining digits, in that case, you'll need a signed
by unsigned multiply for those mulitplications where only one of the
digits is the left most . You can use a signed multiplier for unsigned
multilplication with a reduced number of bits: tie the most significant
bit '0' and treat the rest as an unsigned value.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 89023Well I certainly agree on the approach. We use DigiKey sourcing as a good reason to choose a part. We would use RS of Farnell, who we do actually use ocassionally, but their respective websites don't work well for searching a new part of a specific type. Their pricing is also well off production numbers pricing whereas DigiKey is pretty much on the ball. The only weakness in Digikey for us is the 2 days it takes to get here in the UK. Still looks pretty good is it is a late evening order or it isn't a desperate rush. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Eric Smith" <eric@brouhaha.com> wrote in message news:qhy86h4mu7.fsf@ruckus.brouhaha.com... > John_H wrote: >> I think it's the Texas Instruments TFP501 and TFP510 (Rx and Tx) that are >> popular TMDS choices. These came up with similar parts using a keyword >> search on DVI on the TI website. > > Sylvain Munaut wrote: >> Would you happen to know where to find theses for experimenting ? > > I'm not sure about the 500 series, which have HDCP, but Digikey and Newark > seem to stock the TFP410PAP transmitter, and the TFP401APZP receiver. > > Others will argue, but my general rule-of-thumb for sourcing parts for > prototypes or low-volume production is that if you can't get it from > Digikey, Mouser, or Newark, it doesn't really exist. > > EricArticle: 89024
Lathe_Biosas wrote:
> Hi
>
> After searching more than 3 hours the web, awincupl.exe was found to
> compile some CUPL code.
> Personally I find it to bugy, so if there is any better suite to get a
> .jed file I would appreciate the information.
>
> The programm for a g16v8 needs to have 1 input to decode 8 outputs,
> unfortunatelly the code attached does not give the right output
> signals. That is, when 0 give as output 00100000 when 1 give as outs a
> 01000100;
>
> The code was loaded to 2 GALs and the do exactly the same errors. I
> tried diferent programmers with the same results.
>
> Could someone please tell me what I'm doing wrong?
> Best Regards and Thank you
CUPL creates a .DOC report file - have a look in that, and check the
final reduced equations ARE what you expected.
CUPL can also create/append test vectors, so you can verify operation
on the device programmer.
-jg
> Code:
>
>
> Name IO ;
> PartNo 00 ;
> Date 9/2/2005 ;
> Revision 01 ;
> Designer Engineer ;
> Company None ;
> Assembly None ;
> Location ;
> Device g16v8 ;
>
>
> /* *************** INPUT PINS *********************/
> /* PIN 1 = CLK; */
> PIN 1 = IN;
>
> /* *************** OUTPUT PINS *********************/
> PIN 19 = !ADR6 ; /* */
> PIN 18 = !ADR5 ; /* */
> PIN 17 = !ADR4 ; /* */
> PIN 16 = !ADR3 ; /* */
> PIN 15 = !ADR2 ; /* */
> PIN 14 = !WR ; /* */
> PIN 13 = !RD ; /* */
> PIN 12 = !SEL ; /* */
> /*
> * Logic: examples of simple gates expressed in CUPL
> */
>
> FIELD input = [IN];
> FIELD output = [!SEL, !RD, !WR, !ADR2, !ADR3, !ADR4, !ADR5, !ADR6];
>
> TABLE input => output{
> 0 => 'b'00100000;
> 1 => 'b'01000100;
> }
>
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