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On Wed, 31 Aug 2005 23:49:24 -0500, Andrew Dyer <amdyer@gmail.com> wrote: >On Wed, 31 Aug 2005 19:04:24 +0000, Mike Harrison wrote: > >> Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes called Panel-link >> I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up to - I saw a mention >> recently about using the DDR registers to reduce the data rate but couldn't immediately see any >> Xilinx appnotes when I had a quick look. >> >> Also, as the IO banks on the lower-end dev boards tend to be tied to +3.3v, but LVDS needs 2.5v, >> what happens if you lie to the software about the supply - will it work to any useful degree >> (interested in lvds output only)? > >Funny you should mention this - I am working on exactly this at >work right now. > >It's not working right now, but the basics are in place. clock >runs and I see data coming out of the fpga, but I think I might >be shifting bits in the wrong place. Panel stuff is annoying in >that the data streams are organized in 7-bit chunks which means >you have to do some trickery to do shifting via the DDR registers. What frequency/display format are you aiming for ? >The DDR trick is nice, otherwise you end up doing a fair bit >of monkeying with RLOC attributes if you want to run an s3 -4 >speed grade part at 200+ Mhz. > >Our board has a selectable 2.5V/3.3V bank for doing either LVTTL >or LVDS panel stuff. > >I assume you know about the TTL to LVDS chips made for this from >National and others? Yes - I bought a couple to play with after messing with a ttl (parallel) style interface, but I was wondering how possible it would be without..Article: 88951
On Thu, 01 Sep 2005 00:32:32 +0200, Sylvain Munaut <com.246tNt@tnt> wrote: >Mike Harrison wrote: >> Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes called Panel-link >> I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up to - I saw a mention >> recently about using the DDR registers to reduce the data rate but couldn't immediately see any >> Xilinx appnotes when I had a quick look. > >Look at >http://www.xilinx.com/bvdocs/appnotes/xapp298.pdf > >It's not for TFT panels but for their TX side, they serialize 10 bits by >using a 5x clock and DDR flips flops with a differential output. > > >> Also, as the IO banks on the lower-end dev boards tend to be tied to +3.3v, but LVDS needs 2.5v, >> what happens if you lie to the software about the supply - will it work to any useful degree >> (interested in lvds output only)? > >Well, on lower end board, the trace might not be routed as differential >anyway. The Avnet spartan 3 board (the PCI one) I have has 4 LVDS pairs >connected on 2.5v rail. > >That's definitly something I'd like to do. I might try it soon with an >old laptop scree if I find the doc for it. TFT panel docs are a bit scarce but from what I've seen, they are all very similar to each other within any given resolution. If you have the whole laptop lid, you will have the cable/flexi which will help identify the connections. Here are some links to tft pinouts and data I found a while ago. Most concern ttl-style panels but even the LVDS ones are based on this, so give a starting point for experimenting with timings etc. Some LVDS panels have an identifiable LVDS-to-TTL converter chip, so the pinouts can be derived by beeping out the pins. http://www.optrex.com/products/groupdetail.asp?g=TFT&s=12.1 http://www.linux-hacker.net/cgi-bin/UltraBoard/UltraBoard.pl?Action=ShowPost&Board=verytech&Post=152&Idle=0&Sort=0&Order=Descend&Page=0&Session= http://support.advantech.com.tw/Cservice/LCD.nsf/f99b88c84af1eeff482565ec000759ea?OpenView&Start=1&Count=30&Expand=17.1#17.1Article: 88952
I'm using Mentor Fpga Advantage 7.0 and really, I read the docs but I can't figure the difference between "through block" and "through components" in the possible invocation of the various design flow (DesignAnalyst, Modelsim Precision Synthesis, Generate... flow (right upper side buttons)) Can someone help?Article: 88953
Dear all, I'd like to understand why my design, which occupies 2500 Slice according to Precision RTL, increases to 3900 Slices after running Xilinx ISE Translate and Map. The synthesized design is passed in EDIF format from Precision to ISE. Any explanation about that ? Thanks in advance.Article: 88954
"Andy Peters" <Bassman59a@yahoo.com> wrote in message news:1125515151.589486.295760@f14g2000cwb.googlegroups.com... > Marco wrote: >> Hallo, >> have connected an external signal to my spartan 3. When the external >> peripheral goes into power down mode, the signal goes into Hi-Z state. >> >> I have made a process sensitive to the external signal. >> >> if (ext_signal = 'Z') then >> ... >> >> Using this syntax the fpga doesn't "see" the high impdance state and >> considerthe signal 0 or 1. >> >> What could I do? > > I'd be very surprised if the synthesis tool (I presume XST?) didn't > complain or error out on that (ext_signal = 'Z') comparison. There's > no way for the FPGA logic to detect that a signal is undriven, which is > what happens when a driver is tristated. > > About all you can do is to figure out some way for your peripheral to > signal that it's powered up. I don't know the details of your > peripheral, so that's something you'll have to figure out. > > -a > I have solved the trouble to manage the Hi-Z state. After chipselect, the a/d conversion takes 5 clock cycles. After it goes low for 1 cycle and then it sends datas through a serial connector. I have added six states into state machine, it's simple, and works well. Many Thanks to everyone!! MarcoArticle: 88955
Hello, I want to connect a LED with Uf=1.8V and If=20mA to a CPLD (XC2C512). But from the datasheet I get that the current is limited to I_OH and I_OL = 8mA. Is this right? Means this that I couldn't use this LED with 1.8V? Have I to operate the LED with 8mA and the corresponding voltage (using a resistor in series)? Regards DenizArticle: 88956
Who sells bare die (non packaged) FPGA, CPLD, controllers ? Thanks. Dix www.testhaus.comArticle: 88957
Hallo, I have made a small microcontroller based on microblaze. I have connected a differential 16 bit adc to my system. The adc takes input from a opamp for testing. The system works well only if I measure voltage between chipselect of adc and gnd. In this way it shows every hex number in range: 0 to 7FFF (it is two complementer). If not, I can see only 4-5 numbers of the acquisition range: FB, 1F1F, 3E3E, 7C7C. Which trouble could produce a so strange behavior? Many Thanks MarcoArticle: 88958
just use leds with 2mA (for a small price premium)
or use a resistor to limit the curent to <=8mA if your leds have enough
intensity.
Aurash
denizdikmen@gmail.com wrote:
>Hello,
>
>I want to connect a LED with Uf=1.8V and If=20mA to a CPLD (XC2C512).
>But from the datasheet I get that the current is limited to I_OH and
>I_OL = 8mA. Is this right? Means this that I couldn't use this LED with
>1.8V? Have I to operate the LED with 8mA and the corresponding voltage
>(using a resistor in series)?
>
>Regards
>Deniz
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 88959Working for a manufacturing company that specialises in FPGA designs and development boards, I can now tell you that our new product RAGGEDSTONE1 is in its final stages of development and finalisation. While developing this board we have considered and listened to many suggestions provided by previous customers and peoples posting to previous news messages, and the result of which is an amazing board that will amaze everyone in its performance to cost profile. JUST WAIT AND SEEN........! However developing this board at a cost has meant that we cant include everything one wishes, so I ask you what you might think would be good for expansion modules that we could develop and consider, for the final pin layout, to allow maximum performance from the Spartan-3 contained within the board core. ------------------------------------------ Ian Muncaster BENG(Hons), Enterpoint Ltd - Opening the doors to cheap (yet powerful) development boards to everyone. web: www.enterpoint.co.ukArticle: 88960
Hello, I am using the Xilinx ISE 7.1 with ModelSim 6.0a and I have a problem when I use the "Perform Timing-Driven Packing and Placement" option for the mapping process. When I turn that option off my design works perfectly: during all simulations I get the outputs that I expect. But when I turn the option on the Post-Map and Post-PAR simulations give different outputs. It is as if the circuit suddenly performs a different computation. My circuit was designed for the Virtex-4 and only uses flip-flops and the DSP48 blocks of the FPGA. All the components are connected to the same clock and I am not running the circuit anywhere near its maximum frequency. So I find it odd that an option which should only influence the timing of the circuit (and leave the functional correctness intact) causes this problem. My guess would be that this is some kind of bug in the mapping process. However, I am quite new to FPGA programming and therefore it is more likely that I made some mistake. In any case, any help to give me some insight in this problem would be appreciated. Thank you, MartinArticle: 88961
Hi Martin,
> I am using the Xilinx ISE 7.1 with ModelSim 6.0a and I have a problem
> when I use the "Perform Timing-Driven Packing and Placement" option for
> the mapping process.
> <snip>
No, it is most likely not your error. There are known problems with the
DSP48 register-balancing feature of the mapper. Set the variable
XIL_MAP_NO_DSP_AUTOREG in your environment and your problem will most likely
disappear.
You may find that upgrading to the latest service pack will also fix it, but
unfortunately this is far from certain I'm afraid. If you can submit your
design (or part of it) to Xilinx for analysis, that would be really great.
The Map team are keen to get to the bottom of these problems.
Sorry for the inconvenience...
Cheers,
-Ben-
Article: 88962The cascading used in my design was generated by XPS, so I guess it wasn't supposed to happen :) It's still a weird bug, imho.Article: 88963
I've just started to use the XUP Virtex-II Pro, but I hit a problem I can't seem to solve or circumvent: I'm using EDK 6.3, and when I generate a system containing DDR in XPS, I get the following errors during compile time: Constructing platform-level signal connectivity ... ERROR:MDT - pgassign1 - assign index is out of VEC range, [0:1] ERROR:MDT - pgassign1 - assign index is out of VEC range, [0:1] ERROR:MDT - pgassign2 - assign index is out of VEC range, [0:1] Completion time: 13.00 seconds ERROR:MDT - platgen failed with errors! make: *** [implementation/system.bmm] Error 2 Done. It seems the system has a problem creating the top-level connections. I have no idea how to "fix" this. I haven't changed any settings after generation. As far as I know, the PGassign signals are "temporaty" signals created by XPS when merging nets (for example, to merge the clock inputs of the DDR memory with padding '0' signals). But I'm not sure about this. Anyone know what to do? Thank you in advance!Article: 88964
Hi group, My design contains 1 MAXII EPM1270, 1 LXT971, 1 LXT971, 1 MAXII EPM1270 in series in a JTAG chain. Of course, I defined an element called LXT971 with an instruction register length of 4 (as stated by the manufacturer). Strangely however, using the "Auto Detect" feature, Quartus sees both EPM1270 all right and two "unknowns" in the middle with an instruction register length Of 16 (!!!). The QUARTUS II software keeps on misbehaving since a few days. I think the misbehaviour is related to the installation of version 5.0 SP1 (Web version) and/or a recent version of the LPT1 driver for the ByteBlasterMV/ByteBlasterII. Before that, I had no problem at all for downloading both EPM1270's (with the MV pod only. I always had problems with the II pod). Now, whatever the programming adapter, if I try to do any operation on the second EPM1270 of the chain (4th device of the chain), I get a curious message like : Error: Can't recognize silicon ID for device 4 Error: Operation failed But, any operation on the first device always completes successfully. So, the problem is probably due to the presence of the two LXT971 in the center of the chain (although everything worked fine and reliably with the MV pod and previous software/LPT driver)? I remember I had an equivalent problem with the Xilinx ISE tool (defining the JTAG instruction register length was not sufficient to make the thing work. I had to provide the full BSDL file to ISE, and from there on it worked). BUT, I see no such thing in the Quartus software, just the instruction register length may be entered. Any idea please.Article: 88965
Because of packing factor, I can put bet that "precision RTL" is taking
total number of FFs and LUTs and is dividing with 4 (assuming V2, V2P,
V4, S3) and is getting the mumber of slices.
Map is responsible of packing this and very likely will not be able to
pack 100% (every single slice should have all the luts and FFs used)
try to see how many FF and LUTs is "precision RTL" reporting and compare
with the number of FF and LUTs reported by map.
Aurash
giachella.g@laben.it wrote:
>Dear all, I'd like to understand why my design, which occupies 2500
>Slice according to Precision RTL, increases to 3900 Slices after
>running Xilinx ISE Translate and Map. The synthesized design is passed
>in EDIF format from Precision to ISE.
>Any explanation about that ?
>
>Thanks in advance.
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 88966According to the XUPV2P website, the latest EDK Base System Builder support files require EDK v7.1 with SP2 and ISE v7.1 with SP3: http://www.xilinx.com/univ/xupv2p.html I've used these versions several times to successfully build XUPV2P systems with DDR. Paul "zoinks@mytrashmail.com" wrote: > > I've just started to use the XUP Virtex-II Pro, but I hit a problem I > can't seem to solve or circumvent: > > I'm using EDK 6.3, and when I generate a system containing DDR in XPS, > I get the following errors during compile time: > > Constructing platform-level signal connectivity ... > ERROR:MDT - pgassign1 - assign index is out of VEC range, [0:1] > ERROR:MDT - pgassign1 - assign index is out of VEC range, [0:1] > ERROR:MDT - pgassign2 - assign index is out of VEC range, [0:1] > Completion time: 13.00 seconds > ERROR:MDT - platgen failed with errors! > make: *** [implementation/system.bmm] Error 2 > Done. > > It seems the system has a problem creating the top-level connections. I > have no idea how to "fix" this. I haven't changed any settings after > generation. > > As far as I know, the PGassign signals are "temporaty" signals created > by XPS when merging nets (for example, to merge the clock inputs of the > DDR memory with padding '0' signals). > But I'm not sure about this. > > Anyone know what to do? > > Thank you in advance!Article: 88967
Hi All! I have a project which will use spartan3 xc3s200-pq208 as an pci bridge chip. And there's the problem: In spartan3 datasheet (ds-099,version:August 19 2005) part 3(DC and Switching Characteristics) section called "Simultaneously Switching Output Guidelines" table 23 page I noticed the SSO number for PCI33_3 package pq208 is "1". Sine PCI use 49 signals , I think I can't use the package. The SSO number for xc2s200-pq208 is "4".But why this is so diffence between xc2s200-pq208 and xc3s200-pq208? I make two ISE projects one target to xc2s200-pq208,another xc3s200, and use ibiswriter generete to ibis file. Below is the result: For 3S : [Component] Spartan-3 [Manufacturer] Xilinx, Inc. | [Package] | For Package Type pq208 | variable typ min max R_pkg 0.2 0.199 0.2 L_pkg 14.5nH 12.8nH 16.2nH C_pkg 1.8pF 1.6pF 2.0pF [Model] PCI33_3 Model_type I/O Polarity Non-Inverting Enable Active-Low Vinl = 0.99V Vinh = 1.65V Vmeas = 2.03V Cref = 0.000F Rref = 25.00 |Vref = 0.00V Vref = 3.30V C_comp 6.38pF 4.60pF 8.23pF [Ramp] dV/dt_r 0.98/0.98n 0.75/1.56n 1.16/0.62n dV/dt_f 0.98/1.87n 0.70/2.33n 1.24/1.28n R_load = 25.00 FOR 2S: [Component] Spartan2 [Manufacturer] Xilinx Inc. [Package] | For Package Type pq208 | variable typ min max R_pkg 182.50m 180.00m 185.00m L_pkg 13.350nH 11.700nH 15.000nH C_pkg 1.5500pF 1.3000pF 1.8000pF [Model] PCI33M5V Model_type I/O Polarity Non-Inverting Enable Active-Low Vinl = 0.800V Vinh = 2.000V Vmeas = 1.500V Cref = 50.00pF Rref = 1.0M Vref = 0.0V C_comp 6.5000pF 5.0000pF 8.0000pF [Ramp] | variable typ min max dV/dt_r 1.4790/1.4894n 1.1430/2.5760n 1.7178/1.0217n dV/dt_f 1.7469/1.1800n 1.4917/2.0700n 1.9432/0.7937n R_load = 50.0000 Since almost all values are almost equal(except the R_load,S3:25,S2:50), Why the SSO numbers are significant differ ? Or this just representation (When they driver same load , the SSO number are same )? Thank you for any words!Article: 88968
Ram, First, I understand your situation and solidate with you. Second, despite that DigiKey list those FPGAs for such high price, which may be a bit old (?), the same devices from Virtex-II family are much cheaper than the ones you have been screwed up with, if you check with the distributor. Check out also the prices for similar devices, so that you would not be screwed up with the offer... best of luck Vladislav "Ram" <r_fpga_dev@yahoo.com> wrote in message news:CMuRe.3100$Z91.788@tornado.socal.rr.com... > Hi. > > I have a sealed, un-opened, 60-pack of XCV1000-4BG560C FPGAs for sale. > They > are in the original Xilinx packaging, seal date of 31-OCT-02. > > Here is a datasheet: > http://direct.xilinx.com/bvdocs/publications/ds031.pdf > > I am *not* a chip broker, but an independent EE trying to recover some > losses on these. These were purchased for a project, but the customer > screwed me on the project and gave me these as part of payment. > > DigiKey lists the XCV1000-4BG560C at $1462/chip, min-order of 12, total > cost > for 12 @ $17,544.00. > > See here: > http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?Ref=355865&Row=532143&Site=US > > Please make me an offer on the entire lot. I DO NOT want to eBay these, so > please do not low-ball me. > > Please e-mail me: > > r_fpga_dev@yahoo.com > > Ram. > > > > > > > > > >Article: 88969
You may use a block buffer (Virtex-II family) with enable, which provides glitch-free operation. If you may use this signal as a clock enable for other clock, this would also be a nice alternative. Vladislav <yijun_lily@yahoo.com> wrote in message news:1125430241.111312.49060@o13g2000cwo.googlegroups.com... > Hello, > > I want to implemented a gated clock signal that is active for only a > certain period. What is the best way? > > I did it like this (I know that is bad) > > wire clock_coding; > assign clock_coding = (counter > 5 && counter < 120)?clock:1'b0; > > Thanks, >Article: 88970
Has anyone seen or developed an IP to interface the Microblaze to the PLX PCI 9056 in mode C? Thanks, JTWArticle: 88971
We have a 3.3 volt uP that's programming two Spartan 3 FPGAs in slave serial mode. A CPU port pin drives a 180 ohm series resistor to the line that CCLKs both FPGAs, with a 330 ohm resistor to ground at the last one, making a nice voltage divider for the 2.5 volt dedicated config logic. It works fine and both chips configure nicely. But if we probe the resistor junction before we configure either chip, which is both chip's CCLK pins, we get about +0.6 volts with the CPU port pin at ground. Clearly one or both of the CCLK pins is sourcing current... about 5 mA total! All FPGA ground pins seem to be properly grounded. Anybody have ideas? JohnArticle: 88972
Hello, I am having ADI board containing xilinx virtex II chip. There are two pins defined as LVDS_33 I/O but I wanted to reprogram them as single ended signals and hence I had removed the 100ohm resistance between the lvds signals. The lvds receiver output signals are ignored by my design. Hence I am sending two single ended signals to the two pins which are defined as lvds. Now the 2 pins take 0-2.4V and the other is open. Does this mean I am exceeding the electrical ratings ? I see this on the LVDS DC specifications. VCCO =3D 3.3V DC PARAMETER CONDITION MIN TYP MAX VIDIFF (Common-mode I/p =3D 1.25) 100 350 N/A mV I/p Common-Mode (Diff I/p V=3D =B1350 mV) 0.2 1.25 VCCO - 0.5 I know I can redefine the pins to accept LVCMOS25 I/O but the way it is, will it cause the device to fail ?Article: 88973
Just curious if anyone else has come across this: I have a design using an asynchronous fifo. It builds without any problems in ISE 6.3. When I upgraded to ISE 7.1, I get the following error when I build the bitstream: ERROR:PhysDesignRules:993 - Dangling pins on block <.../fifo/Mmux__n0082_inst_mux_f7_16/MUX6.IO>:<SLICE_F6MUX>. Must have a VCC signal on the input control path. I originally generated the fifo using the 6.3 core generator. I recreated it with the 7.1 core generator (including the IP updates), and I get the same problem. If I choose to skip the DRC, the design works fine. However, I would prefer not to skip it. If I open the FPGA Editor, and run the DRC, and get the same PhysDesignRules:993, but it's a warning, not an ERROR -- -- Matt +-- |Matthew Plante | University of New Hampshire | InterOperability Lab | Research & Development | SMTP: maplante@iol.unh.edu | Phone: +1-603-862-0203 +-Article: 88974
ciappalastringa wrote:
> I'm using Mentor Fpga Advantage 7.0 and really,
> I read the docs but I can't figure the difference
> between "through block" and "through components"
> in the possible invocation of the various design flow
> (DesignAnalyst, Modelsim Precision Synthesis,
> Generate... flow (right upper side buttons))
Consider learning Modelsim all by itself first.
You can't run synthesis until you have good
code, and the only way to get good code
is to edit/sim/edit/sim.
-- Mike Treseler
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