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>How will the master know that this byte is the last byte
Can you be more specific on what you mean by this? (are you referring to the
SPD controller, or the state machine or microprocessor controlling it?)
>and what
> happens if the master acknowledges the last byte also.
Referring to the I2C spec Page 10, section 7.2, "If a master-receiver is
involved in a transfer, it must signal the end of data to the
slave-transmitter by not generating an acknowledge on the last byte that was
clocked out of the slave. The slave-transmitter must release the data line
to allow the master to generate a STOP or repeated START condition"
I don't really know what will happen with the slave device you are using if
you don't NACK the last byte, it might work just fine, or if the SPD puts
out one additional clock at the end of the ACK bit position to release the
ACK/NACK, the slave device would think the next byte should be read and
would assert the MSB of the next byte on the data line. If the MSB of the
next byte was a 0, then the master would not be able to apply a stop
condition (remember it's open drain or wire AND), and the system would
affectively be unsynchronized. The Master may believe it terminated the the
read sequence correctly, and the slave could still be driving the data line
low with it's MSB waiting to shift out the next bit for the byte.
Following communications to the slave device would fail, until the master
outputs a continuous 1 (0xFF) pattern to the device allowing the device to
eventually get a NACK and terminate the read operation. The master could
then attempt to repeat the sequence for a read operation..
Based on the spec. and the possibilities of what you can look forward to and
the corrective actions, I would recommend following it for compatibility
reasons.
dbrown
<praveen.kantharajapura@gmail.com> wrote in message
news:1118720948.402364.49090@g49g2000cwa.googlegroups.com...
>
>
>
>
> David Brown wrote:
>> One additional note. As mentioned below, the master should ACK each byte
>> that it reads, except for the last byte. The last byte should be nacked
>> prior to the stop condition.
>>
>
> How will the master know that this byte is the last byte, and what
> happens if the master acknowledges the last byte also.
>
>
>
>
>> dbrown
>>
>> "Gabor" <gabor@alacron.com> wrote in message
>> news:1118690295.803563.225360@g43g2000cwa.googlegroups.com...
>> > praveen.kantharajapura@gmail.com wrote:
>> >> Hi Gabor ,
>> >>
>> >> Thanks for the reply. My EEPROM is write protected i will only be
>> >> reading the first 128 bytes, is this flow diagram all right.
>> >>
>> >>
>> >> 1-bit 8-bits
>> >> 1-bit
>> >>
>> >> Start from master --->> EEPROM Slave address("10100001") -->> ACK
>> >> from eeprom --->>
>> >
>> > Actually you need to start with write address "10100000" in order
>> > to write the address register (you don't need to write the EEPROM
>> > array so write protect doesn't matter).
>> >
>> >>
>> >>
>> >> 8-bits 1-bit
>> >> Write register address "00000000" --->> ACk from EEPROM
>> >
>> > Right here you need to switch to read mode. There are two
>> > ways to do this. Either master sends Stop followed by Start
>> > or master sends repeated start. If you intend to reuse this
>> > code for other peripherals besides EEPROM, you'll find the
>> > repeated start is compatible with more chips.
>> >
>> > Then you need to provide slave address "10100001" for read
>> > and get ack from slave then:
>> >
>> >> 8-bits 1-bit
>> >> --->> Data[0]
>> >> from EEPROM --->> ACK from master
>> >>
>> >> 8-bits 1-bit
>> >>
>> >> ................. --->>Data[127] from EEPROM --->> STOP from master
>> >>
>> >> I will generate the STOP condition after receiving 128 bytes.
>> >>
>> >> Any comments on this.
>> >>
>> >>
>> >> Regards,
>> >> Praveen
>> >>
>> >>
>> > Also you talk about "bits" when you send start and stop. These
>> > conditions
>> > do not toggle the SCL line so they are not usually counted as "bits"
>> > as would be data or Ack cycles.
>> >
>> > Regards,
>> > Gabor
>> >
>
Article: 85701Depending on the speed you need you can also slow down the clock by 4 and run it through a 3 stage shift register, where each output stage will be shifed by 90 degrees. Clock = 0 degrees stage 1 = 90 degrees stage 2 = 180 degrees stage 3 = 270 degrees dbrown <zoinks@mytrashmail.com> wrote in message news:1118738196.144036.226920@g49g2000cwa.googlegroups.com... > Hi, I'm still working on creating a DDR interface for an OCM bus. > > The problem I now face is the following: I need "shifted" clk signals. > I'm using a driver originally used for the PLB bus, which has those > shifted clks. Since I do not have enough knowledge or time to create > shifted clk's myself (The deadline is reaaaly close). > So I "borrowed" the clock signals from the PLB bus (Runs on the same > speed as the OCM bus, I thought I could give it a try :p. > > But when I do this, the timing constrains aren't met. So I guess I need > to create my own shifted signals from the OCM clk (Which I'm not even > using right now) > Here is the timing constraint table: > > ---------------------------------------------------------------------- > Constraint | Requested| Actual |LLvls > ---------------------------------------------------------------------- > NET "bufgp_10/IBUFG" PERIOD = 10 nS HI | N/A | N/A | N/A > GH 50.000000 % | | | > ---------------------------------------------------------------------- > PERIOD analysis for net "dcm_0/dcm_0/CLK0 | 10.000ns | 5.476ns| 17 > _BUF" derived from NET "bufgp_10/IBUFG" | | | > PERIOD = 10 nS HIGH 50.000000 % | | | > ---------------------------------------------------------------------- > * TSCLK2CLK90_ocm_ddr_1 = MAXDELAY FROM TIM | 2.250ns | 3.931ns| 5 > EGRP "PLB_Clk_ocm_ddr_1" TO TIMEGRP "Clk | | | > 90_in_ocm_ddr_1" 2.250 nS | | | > ---------------------------------------------------------------------- > PATH "FROM CPUS THRU RST_GRP TO FFS" TIG | N/A | 1.810ns| 0 > ---------------------------------------------------------------------- > PATH "FROM FFS THRU RST_GRP TO FFS" TIG | N/A | 1.445ns| 1 > ---------------------------------------------------------------------- > PATH "FROM FFS THRU RST_GRP TO CPUS" TIG | N/A | 0.656ns| 0 > > The one with the * is the one giving the problem. > > How can I easily make such a clock myself? > Btw, I'm using EDK 6.3 and working on the ML310 board. (Virtex 2pro) > > Thanks in advance, > > Jim Tuilman >Article: 85702
Dear all, I need some help with this one. I am integrating a design of somebody who's been designing using schematic and VHDL code generation. Consequently, a direct VHDL synthesis results in 500+ warnings during XST and another 500+ during NGDBuild and MAP that are inevitable & annoying, yet this block is not simulated in a full system environment, so it makes a lot of sense to integrate it after XST, i.e. use its netlist for NDG Build. So, I have an NGC file. I am running NDGbuild and there are some instances that are missing, therefore I get error messages. the instances that are missing are found in /_ngo_/ folder of the delivery (there is synthesis of this block stand-alone as well). I know that modular design could be a nice solution, but for technical reasons this option of out of consideration. So, the question is how do I merge this NGC and link place and route tool to those NGO files? I feel like this is a simple thing to do, but... Any help is appreciated. Thank you all for your time. VladislavArticle: 85703
add NGO files directory under translation prorperty "macro search path". -JamesArticle: 85704
If you are using Xilinx ISE, I think you can only see entity port signal names after posted P&R timing simulation model. Even if you have "keep hierarchical" switch turn on, most internal signals have been replaced by some ISE generated signals. -JamesArticle: 85705
Hi all, Using HDL to pipelining manually is a hardy task. And I found some tools like Synplify have pipeline tools. But the pipeline they provided is just insert reg between RAM and logic. My question is: Is there a tool to auto pipeline the logic? For example, I want to pipeline the logic by insert N regs. And if there exists such a tool, what does it modify, HDL or netlist level? Best regards, DavyArticle: 85706
I think Xilinx, or maybe it's Mentor Graphics, that has a tool called Precision, that is suppose to "push or pull" registers in order to make timing criteria. I don't know what it costs. b r a d @ a i v i s i o n . c o mArticle: 85707
"David Brown" <david.brown_spamnot@vertronix.com> schrieb im Newsbeitrag news:6bednUMu4YQ7SDPfRVn-oQ@adelphia.com... > You may want to bring your gated clock to an IO pin and back into a GCLK > pin. I dont think so. Fix the design. Do what the tool is telling you. DONT use a gated clock, use a clock enable instead.. Search your (VHDL?) code after if clk'event or if rising_ege(clk) stuff. Only real clocks (tm) should appear there. If there is any signal generated like my_damm_gated_clock <= real_clock AND gate_signal; than this is bad. Regards FalkArticle: 85708
Hi Davy,
> My question is: Is there a tool to auto pipeline the logic? For
> example, I want to pipeline the logic by insert N regs. And if there
> exists such a tool, what does it modify, HDL or netlist level?
Both Synplify Pro and XST (and probably other synthesis tools) can do this
to some extent.
It's also often called Register re-timing. It works like this: you can write
your big block of
combinatorial logic in HDL, then add N registers after it (also in HDL),
then get the tools to
push the registers around to optimize the timing of the circuit.
That's the theory! In practice you'd be somewhat foolish to rely on this
today (Try it!).
However, it's likely to become more and more important in future.
An area in which XST does this fairly well is multipliers. If you use the
right settings and/or
attributes, it's possible to write a combinatorial multiply followed by a
register-based delay
line, and have the registers pushed back into the adder tree automatically.
The original HDL
source is untouched; it's the resulting netlist which is optimized.
Cheers,
-Ben-
Article: 85709If this is your first time with the board & there are many '1's with IDcode, try thinking about signal integrity issue or board problems... Vladislav "damidar" <dejavu99@hotmail-dot-it.no-spam.invalid> wrote in message news:MfidnZJr6fJ5nzLfRVn_vg@giganews.com... > hi....Please help me for a programmer xilinx XC9536XL (parallel LPT) > > When i starter to program, it stopped on: > > "Error:IMPACT 583 :the idcode read from the device does not match the > idcode in the bsdl" > > :( > > Help me thanks a lot..... >Article: 85710
Hello, Could you, please, give any insight on what can cause the following errors (i got many)? I also have the same errors on the internal signals, not only xilinx nets. Thanks Vladislav ------------------------------------------------------------------------------------ ERROR:MapLib:661 - LUT4 symbol "daisy_all_i/rf_i/rf_dbi_i/_n0018[0]" (output signal=daisy_all_i/rf_i/rf_dbi_i/_n0018[0]) has input signal "daisy_all_i/tc_rx_apoc_mode" which will be trimmed. See the trim report for details about why the input signal will become undriven. ------------------------------------------------------------------------------------Article: 85711
john wo wrote: > what about this error? > > --------------------------------- INTERNAL_ERROR:Xst:cmain.c:3022:1.146.4.1 - To resolve this error, please consult the Answers Database and other online resources at <http://support.xilinx.com> ERROR: XST failed Process "Synthesize" did not complete. > > xilinx.support and google gave nothing... what step should I follow to solve this one???? > > thanks for help! Hi John I already came across with this kind of error before (ISE 6.3), which appeared just after entering the "HDL Analysis" task (second step performed by XST after "HDL Compilation"). After spending a fair amount of time trying to isolate what triggers this error, I found out that it was a mismatch between a port declaration in an entity, and the port declaration of the related component in the upper level of the hierarchy (in a VHDL design). Therefore my advice will be to try to compile your design with an other parser/compiler (such as Modelsim, who seems more strict than XST), and make sure that no suspicious warnings remain.Article: 85712
CODE_IS_BAD wrote:
> I am using ModelSim PE 6.0d. I have done functional simulation for
> my design (i could view all internal signals there) and that works
> fine.
Good. Check design rules, run a place and route,
check static timing and you are done.
> When i run Post P&R simulation i get some misfunctionality. To
> correct the same i need to view internal signals in the post P&R
> simulation. But the same does not come if we check the signals listed
> under UUT.
This may be a problem of synchronization.
Such problems can't be debugged easily using simulation.
Check synchronization for all module inputs
and outputs. Check static timing.
-- Mike Treseler
Article: 85713I have installed xilinx ise foundation 7.1i on a slack10.1 XILINX=/opt/xilinx/ise I follow the istruction on the manual and i refer to http://www.zurich.ibm.com/~ged/wisdom/xilinx.html for some tips to do that on a non-Red Hat system. I perform setup as a normal user with all permission on /opt/xilinx/ise directory. With the same procedure I installed EDK7.1 XILINX_EDK=/opt/xilinx/edk I set up all the environment variable and I installed the ultimate service pack and ip update for both ise and edk. (I use ldconfig, /etc/ld.so.conf for LD_LIBRAY_PATH and seems to work) Finally I'm able to run ise/edk interface with success with a few, maybe ignorable (???), error message like [...] Cannot register service: RPC: Unable to receive; errno = Connection refused unable to register (registryProg, registryVers, tcp) Wind/U Error (248): Failed to connect to the registry on server xxxxxx Cannot register service: RPC: Unable to receive; errno = Connection refused OLE API Function OleInitialize is not currently implemented. Further warnings will be suppressed Wind/U Error (248): Failed to connect to the registry on server xxxxxx Cannot register service: RPC: Unable to receive; errno = Connection refused OLE API Function OleInitialize is not currently implemented. Further warnings will be suppressed [...] The Problem: When I try to open a files or add an existing HDL source file or a project from the ISE project navigator all I can reach is a window with the following error: "can't access this folder path is too long" This happens from EDK's platform studio and from ISE ecs too...I stop here and i try to find an answer around. Damn! After all the trick to make it run :'-( I try to find some solution but the only threads I found were: http://www.fpga-faq.org/archives/75450.html http://www.seriousliving.net/new-3812278-1132.html (agree for the comment about those crap windu!!) I try to kill all windu instance and delete ~/.Xilinx ~/.windu* ~/.Wind* but the problem still remain. I check manually the re-created files in my home directory but I didn't find nothing related. Is there someone who can help me?Article: 85714
I think it will depend on how the gated clock is used and how much logic it clocks. I have done hundreds of designs with gated clocks and multiple clock domains in FPGAs and ASICs and there's nothing wrong with it as long as it's a good gated clock design. The main issue with gated clocks in FPGAs is they don't usually go to internal global buffers and there can be clock skew in the clock tree. If a good gated clock aproach is used, and it is fed out of the device and back in to a global clock pin the design will work fine and will reduce the power. To side with Falk, if the design is only a few flip flops, there is nothing unusual about the clock divide by frequency, and power is not an issue, then you can go back and add clock enables to your code and achieve the same result. David Brown "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:3h8de8FftqolU1@individual.net... > > "David Brown" <david.brown_spamnot@vertronix.com> schrieb im Newsbeitrag > news:6bednUMu4YQ7SDPfRVn-oQ@adelphia.com... >> You may want to bring your gated clock to an IO pin and back into a GCLK >> pin. > > I dont think so. Fix the design. Do what the tool is telling you. DONT use > a > gated clock, use a clock enable instead.. > Search your (VHDL?) code after > > if clk'event > > or > > if rising_ege(clk) > > stuff. Only real clocks (tm) should appear there. If there is any signal > generated like > > my_damm_gated_clock <= real_clock AND gate_signal; > > than this is bad. > > Regards > Falk > > >Article: 85715
Depending on which software you are using there was an error in 5.3i related to Error code 583. I would try going to the Xilinx website and searching for "IMPACT 583". dbrown "Vladislav Muravin" <muravinv@advantech.ca> wrote in message news:WvDre.6378$yU.335951@news20.bellglobal.com... > If this is your first time with the board & there are many '1's with > IDcode, > try thinking about signal integrity issue or board problems... > > Vladislav > > "damidar" <dejavu99@hotmail-dot-it.no-spam.invalid> wrote in message > news:MfidnZJr6fJ5nzLfRVn_vg@giganews.com... >> hi....Please help me for a programmer xilinx XC9536XL (parallel LPT) >> >> When i starter to program, it stopped on: >> >> "Error:IMPACT 583 :the idcode read from the device does not match the >> idcode in the bsdl" >> >> :( >> >> Help me thanks a lot..... >> > >Article: 85716
In article <42aebdcf$1_3@spool9-east.superfeed.net>, Dave Garnett <dave.garnett@metapurple.co.uk> wrote: > >"osedax" <osedax_latin@yahoo.com> wrote in message >news:1118747692.631639.100890@g49g2000cwa.googlegroups.com... >> what kind of tv is that? > >It is a Loewe Xelos A26 - basically a high end flat panel unit. Being >German, it comes with a circuit diagram. And a URL to download the fill for the PROM? TomArticle: 85717
> I use Aldec's Active HDL, I find it more ergonomic than modelsim, and it > has a very nice design entry suite as well. The editor is emacs-like, > but also has the ability to copy and paste VHDL declarations and both > VHDL and Verilog instantiations of any of the library components as well > as any of your own components that have been compiled. It also has a > block diagram viewer/editor, matlab co-simulation and combined > verilog/vhdl/edif simulation. I highly recommend this product if you > are looking for an alternative to modelsim. I think you'll be very > happy with what you see if you check it out. Is all this free? for Linux also?Article: 85718
Let's not forget that Virtex-2 and later FPGAs have, hidden in the Global Clock buffer, not only an Enable input, but also a clock multiplexer. That multiplexer in Virtex-2 must use a synchronous select to avoid glitches, but the BUFGMUX_VIRTEX4 is implemented in such a clever way that the S input can be changed at any time, never causing a glitch. There is a detailed description in the Virtex-4 data sheet, under Global Clocking Resources, page 85 of the August 2004 printed data book. Peter Alfke, Xilinx ApplicationsArticle: 85719
Since I didn't get any answer, I'm posting this again, hopefully someone will shed some light..... Thanks, mArticle: 85720
Preben Holm wrote:
>> I use Aldec's Active HDL, I find it more ergonomic than modelsim, and
>> it has a very nice design entry suite as well. The editor is
>> emacs-like, but also has the ability to copy and paste VHDL
>> declarations and both VHDL and Verilog instantiations of any of the
>> library components as well as any of your own components that have
>> been compiled. It also has a block diagram viewer/editor, matlab
>> co-simulation and combined verilog/vhdl/edif simulation. I highly
>> recommend this product if you are looking for an alternative to
>> modelsim. I think you'll be very happy with what you see if you
>> check it out.
>
>
> Is all this free?
> for Linux also?
No, it is not. I thought you were looking for alternatives to modelsim
PE, not for free simulators. Please forgive me.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 85721Hmm...I suspect your problem stems from trying to use a driver for a Parallel Cable with a USB Cable. But maybe I'm crazy... -j. khbutnospam@clubbutnospam.innet.be wrote: > Hi, > > Can anybody help with the situation described below? > > I followed the best information I could find, but it doesn't work and I > would like some tips that could give me information on what goes wrong, > > Thanks > > Kris Heyrman. > > -- > > kernel: kernel-2.6.11-1.27_FC3, compiled from src.rpm > compiler: gcc (GCC) 3.4.3 20050227 (Red Hat 3.4.3-22.fc3) > xps: Xilinx EDK 7.1.1 Build EDK_H.11.3 > used guidelines from: > http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm > but installed windrvr version 7.00 from www.jungo.com (WD700LN.tgz > instead of WD623LN.tgz), in which I believe Tyson Harding's fix from > 3/18/2005 has been applied. > > /etc/rc.local: wdreg windrvr6 yes > WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86 > loaded > > With a Xilinx XUP Virtex-II PRO Development System, > trying to download Xilinx's Base System: > > # lsusb > Bus 004 Device 001: ID 0000:0000 > Bus 003 Device 002: ID 03fd:0009 Xilinx, Inc. > Bus 003 Device 001: ID 0000:0000 > Bus 002 Device 001: ID 0000:0000 > Bus 001 Device 001: ID 0000:0000 > > $ make -f system.make download > > ********************************************* > Downloading Bitstream onto the target board > ********************************************* > impact -batch etc/download.cmd > Release 7.1.02i - iMPACT H.40 > Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > // *** BATCH CMD : setMode -bs > // *** BATCH CMD : setCable -port auto > AutoDetecting cable. Please wait. > Reusing 78020001 key. > Connecting to cable (Parallel Port - parport0). > WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86 > 21:13:49. > parport0: baseAddress=0x378, ecpAddress=0x778 > LPT base address = 0378h. > ECP base address = 0778h. > Cable connection failed. > Reusing 79020001 key. > Connecting to cable (Parallel Port - parport1). > WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86 > 21:13:49. > Cable connection failed. > Reusing 7A020001 key. WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: > Apr 26 2005 X86 21:13:49. > Cable connection failed. > Reusing A0020001 key. > Connecting to cable (Usb Port - USB21). > Checking cable driver. > File version of /home/krish/binaries/Xilinx/bin/lin/xusbdfwu.hex = > 1018(dec), > 03FA. > File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1018(dec), > 03FA. > Cable connection failed. > Reusing B4020001 key. > Connecting to cable (/dev/ttyS0 Port). > Cable connection failed. > Reusing B5020001 key. > Connecting to cable (/dev/ttyS1 Port). > Cable connection failed. > Reusing B6020001 key. > Connecting to cable (/dev/ttyS2 Port). > Cable connection failed. > Reusing B7020001 key. > Connecting to cable (/dev/ttyS3 Port). > Cable connection failed. > Cable autodetection failed. > make: *** [download] Error 1 > > Connecting to cable (Parallel Port - parport2). > WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86 > 21:13:49. > Cable connection failed. > Reusing 7B020001 key. > Connecting to cable (Parallel Port - parport3).Article: 85722
Does anyone know where can I buy a Xilinx XCR3384XL tq144 CPLD? Thanks in advance Best Regards BrunoArticle: 85723
Hello, thanks for your good ideas. The Avnet Board Marko posted looks very interesting. The Problem is I didn't work with Virtex 4 yet. So it's difficult for me to compare it to Virtex 2 or Spartan 3. Can you give me a comparable Virtex 2 or Spartan 3 device with similar logic resources like Virtex-4 FX12, under the condition I use no specialized IP cores like some projects from opencores? I think there is a µC working µC links for Xilinx PPC available? Thanks, MichaelArticle: 85724
Hello, I think I already had a similar problem with a XC9536! The ID Code was wrong! I was using a long LPT cable! I suspected a Signal Integrity problem and put a capacitor to slow down the edges! The ID code was read successfully and the device was also programmed successfully. To do a quick test, use an oscilloscope probe to load the lines. I don't remember in what line was. Try all four. Hope this helps Bruno "damidar" <dejavu99@hotmail-dot-it.no-spam.invalid> escreveu na mensagem news:MfidnZJr6fJ5nzLfRVn_vg@giganews.com... > hi....Please help me for a programmer xilinx XC9536XL (parallel LPT) > > When i starter to program, it stopped on: > > "Error:IMPACT 583 :the idcode read from the device does not match the > idcode in the bsdl" > > :( > > Help me thanks a lot..... >
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