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Antti Lukats wrote: > "Jedi" <me@aol.com> schrieb im Newsbeitrag > news:SnNve.45$v17.23@read3.inet.fi... > >>Rudolf Usselmann wrote: >> >>>Jedi wrote: >>> >>>>Finally... >>>> >>>>The last 4 days working with NIOS2 since I can't upgrade >>>>my subscription... >>>> >>>>...or is there an opensource alternative like the "utnios" before? >>>> >>>>rick >>> >>>Did you look at www.opencores.org ? >>> >> >>Of course (o; >> >> >>>I don't think there is a nios replacement, but there sure are >>>many alternatives ... >> >>Only have this old utnios design which based on nios32 and then >>the distribution was prohibited by Altera... >> >>But speaking of...has anybody ever done a CPU SOPC component? >> >>rick > > > what you mean was prohibitied by Altera? utnios is is still available I just > checked! > > What Altera DID try to prohibit was, well they told me that I can promote a > sell NIOX > - a NIOS-2 compatible core. So I removed the public links to NIOX from my > website. > > there is nothing at opencores that could be used as nios-2 replacement, the > only opensource > environment that i would consider is LEON3/GRLIB, and that is not hosted on > opencores. > > I have tried to make SOPC processors components and also EDK processor > components > with EDK I succeeded, I had a AVR processor that was possible to use in > EDK/XPS > with SOPC it should also be possible, actually it does exist, and is > available from altera > the Avalon microsequences, its a processor component for SOPC, with full > sources, so > you can use it as base to design your SOPC processors... Oki..found it: http://www.altera.com/solutions/refdesigns/sys-sol/indust_mil/ref-avl-micro.html Hmm..Altera login broken? Didn't work for the whole weekend... rickArticle: 86376
I have some problems with constraining logic that is using two clocks.
I have logic that uses two clocks, GLB (48 MHz, 20.83ns) and GLA (96
MHz, 10.416 ns). Also I use rising and falling edges of 96 MHz clock.
What I need is to constraint this logic not only rising 48 to rising
96 but also rising 48 to falling 96.
As I know there is no possibility in Designer software to use rising
and falling edge constraints. Please tell me this is not true!!!
Anyway, what I did is that I used clock to clock constraint in the
.sdc file in the following way:
set_max_delay 5.2085 -from [get_clocks {clock_comp_1/Core:GLB}] -to
[get_clocks {clock_comp_1/Core:GLA}]
because I want to constraint rising 48 MHz to falling 96Mhz to
5.2085ns.
But, this also presumes that rising 48 MHz to rising 96Mhz is also
5.2085 and I dont need this. This has to be 10.416 ns.
Does anyone know how to solve this?
Thx,
Jura
Article: 86377Hi Steven, What prices can we expect in comparison to Spartan3? Let's say a XC3S250E compared to a XC3S200 in the same package. Will the CP132 package be priced next to the TQ144? When XC3E250E components will be available? Thanks, Luiz CarlosArticle: 86378
Davy wrote:
> There is a problem on How to write FSM in
> Verilog(http://www.asic-world.com/tidbits/verilog_fsm.html).
> Most synthesis tools recommend second "Using Two Always Blocks" style.
> But I would like to use third "Single Always" style. It seems more
> compact.
It is. It works fine. Try it and see.
> What's the pros and cons between the two styles? I see that the third
> style may have state transition latency.
A state transition takes one clock tick,
no matter how you do it. Input synchronization
should be handled as a separate issue.
> But does the third style gain
> higher frequency and shorter critical path?
There are no performance differences for
synchronous designs.
The single process controller does not allow
unregistered outputs and makes long-winded
textbooks unnecessary.
-- Mike Treseler.
Article: 86379Hi everyone Having had a course on introductory VHDL and done a small project in the following semester (4.5 ECTS), we are a group of students thinking to do an individual study-activity in the subject of FPGA's to learn more. The question is - where to start and where to stop? Where should we go now and which subject should we start reading about! The individual study activity will be 5 ECTS points large and therefore fill out 17 weeks with approx. 4 hours of study each. This means around 8.5 hours of work in 8 weeks (which is the length of the indiv. study activity). By doing an individual study activity it is possible to make a project also, and "learn by doing"! There will be no lectures, so everything is done "yourself" and you can use some of the time with a supervisor of course. So with introductory VHDL and a basic project implementing a "bad" multiprocessing system using Spartan II and PicoBlaze CPU's, what can we do, and what can't we do for the indiv. study activity? We have done a basics course in the basics of digital electronics, and also worked with basic analog electronics (and the more advanced transducer interfacing which is more or less irrelevant here). We are all studying for becoming computer systems engineers and are this summer all bachelors. What subjects do you think is relevant, what litterature can you recommend and what does the subject contain (a brief description). Any ideas are welcome! Thanks, PrebenArticle: 86380
Hi Davy, This is really a question for the synthesis tools on the matter of how your code is interpreted. If any of the coding styles would produce different results, the corresponding synthesis tool should have fixed this deficiency by now :) However, there is no really benefit in terms of what you will eventually get, but rather what is more convenient. Personally, I always prefer a single "always", especially if the state machine has MANY outputs. Going a bit further than your question, in my group, I am not enforcing any of those ways. The coding style is completely at the designer's choice. Instead, I enforce the designer to very-well document the "bubbles" stuff, so that he knows what this state machine is doing and it is coded only once. Hope this helps. Vladislav "Davy" <zhushenli@gmail.com> wrote in message news:1119850650.957024.310610@o13g2000cwo.googlegroups.com... > Hi all, > > There is a problem on How to write FSM in > Verilog(http://www.asic-world.com/tidbits/verilog_fsm.html). > Most synthesis tools recommend second "Using Two Always Blocks" style. > But I would like to use third "Single Always" style. It seems more > compact. > > What's the pros and cons between the two styles? I see that the third > style may have state transition latency. But does the third style gain > higher frequency and shorter critical path? > Thanks! > > Best regards, > Davy >Article: 86381
No need to use coregen. Just use the corresponding instance name, the synthesis tool automatically recognizes it Vladislav "pasacco" <pasacco@gmail.com> wrote in message news:1119800347.071206.153410@g43g2000cwa.googlegroups.com... > dear > > i am using 'unisim' for Xilinx component for VHDL "simulation" in > Modelim. So, as far we know the name of the component, no VHDL > description (implementation) was required, which was convenient. > > Now I am wondering whether it is possible to > > - synthesize Xilinx component uing unisim only, > > Should I use 'coregenerator' to synthesize? > > Thankyou in advance >Article: 86382
Some more things which are OK, and which help with the single always block
style:
Multiple non-blocking assigns to the same register: the last one wins:
always @(posedge clk)
begin
out <= 0; // Normally low signal
in_reg <= in;
if (in && !in_reg)
out <= 1; // Pulse out high for one cycle
end
Mix blocking and non-blocking assigns:
always @(posedge clk)
begin
tmp = 0;
if (condition)
tmp = 1;
if (other_condition)
tmp = !tmp;
out <= tmp;
end
(if only you could use the blocking assign output as an input to another
clocked always block... but you can't).
I hate the two always block style: it requires too much typing. It would be
cool if there was a tool to convert from one style to the other.
However, for FPGAs, there is one advantage to the two-always block style:
the Mealy outputs are handly to feed into block RAMs. Block RAMs have short
setup requirements (but huge clk->out delays) so you can improve timing by
moving logic from the output side to the input side, if possible.
In article <4tSdnaiJvLdVeCLfRVn-iw@comcast.com>,
Mike Treseler <mike_treseler@comcast.net> wrote:
>Davy wrote:
>
>> There is a problem on How to write FSM in
>> Verilog(http://www.asic-world.com/tidbits/verilog_fsm.html).
>> Most synthesis tools recommend second "Using Two Always Blocks" style.
>> But I would like to use third "Single Always" style. It seems more
>> compact.
>
>It is. It works fine. Try it and see.
>
>> What's the pros and cons between the two styles? I see that the third
>> style may have state transition latency.
>
>A state transition takes one clock tick,
>no matter how you do it. Input synchronization
>should be handled as a separate issue.
>
>> But does the third style gain
>> higher frequency and shorter critical path?
>
>There are no performance differences for
>synchronous designs.
>
>The single process controller does not allow
>unregistered outputs and makes long-winded
>textbooks unnecessary.
>
>
> -- Mike Treseler.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 86383Hello, I am not quite following, I think that there are two separate issues addressed. One, If you have several devices sharing the same data bus but have different CS signals, where exactly is the problem? You need something like 12 samples * 200 Ksps * 3 devices = 7.2 MHz clock, which can run in robin-round fashion and access each 12 clocks a different SPI port be toggling corresponding CS. What the timing diagrams have to say about it??? Two, You do not need to generate SPI clocks if you are not required to by SPI devices, you already have 57.6 MHz clock, and just divide it by 8 and either use it as a clock if you have clock buffer (line) available, or as a "clock enable" for the existing. In the last option, a general I/O pin + FF would be just fine. Vladislav <m_oylulan@hotmail.com> wrote in message news:1119729848.433597.182440@g44g2000cwa.googlegroups.com... > Hi, > > I need to interface 2 ADCs and 1 DAC to a Spartan-II FPGA running at > 57.6MHz. My data (12-bits wide) needs to be sampled at 200kHz and to > save pins I'm going to be using serial ADCs/DACs. > > As I understand it, using the SPI protocol I would need to read/write > 16-bit words at 200kHz needing 3.2Msps converters. From what I've read > about SPI, all slave devices connected to the same master have to share > the same I/O bus and have separate CS pins. > > - What I can't understand is, if I need my 2 ADCs and 1 DAC to > communicate with the FPGA simultaneously, how do I achieve this when > they have to share the same bus? > > - Are there application notes I could refer to for guidance (I haven't > been able to locate any by googling)? > > - Would I need separate serial clocks (SCLK) for each converter and can > I generate the SCLK using counters, so for instance to get a 3.2MHz > SCLK period, count 18 clock cyles in the 57.6MHz domain of the FPGA > system clock? > > -Do I have to feed SCLK into a clock output pin or a will a general I/O > pin do? > > thanks, > Mees >Article: 86384
Hi, I have built a dvi to lvds converter. However the picture still flickers and is off by 1 pixel. I think I am having trouble with the vsync. Is the vsync on the tmds line the same as on the analog port? Does anybody know if the vsync just does one pulse per frame, I think so but I am not sure... In my EDID Data I find this: V Active Lines 1024 <-this is okay V Blank 42 <- what does this mean? V Sync Offset 1 <- offset to what? V Sync Width 3 <- I guess it means that my pulse is 3 lines? V Image Size Thanks, BenjaminArticle: 86385
Hi all ! thank you for reading this post. I'm experiencing some problems to get good data transfer performance using a PCI core in an FPGA directly linked to a PCI connector in a PC (PCI 32bit-33MHz). The PCI core and the FPGA seem to not be the reason of the problem. The FPGA is most of the time acting on the bus as Master, accessing directly in the system SDRAM. Write accesses to SDRAM are very fast, since I can burst as many words as I want (in my case, 48 words), resulting in a 130MB/s bandwith. However, read accesses bursts are limited by the target (SDRAM controller or just the PCI arbiter, I don't know) to eight word transfers, resulting in a very poor 50MB/s bandwidth. The target always asserts the STOP# pin after the 8th word transfer resulting in a "disconnect without data transfer". All my memory accesses (read and writes) are linearly addressed. Does anyone has an idea of how I can setup my system so I can achieve to have 64-word bursts for Read accesses instead of 8-words ? My system is an Intel Pentium III 600MHz running under Linux Best Regards, Uxello lspci gives me this: 00:00.0 Host bridge: Intel Corp. 440BX/ZX - 82443BX/ZX Host bridge (rev 03) 00:01.0 PCI bridge: Intel Corp. 440BX/ZX - 82443BX/ZX AGP bridge (rev 03) 00:07.0 ISA bridge: Intel Corp. 82371AB PIIX4 ISA (rev 02) 00:07.1 IDE interface: Intel Corp. 82371AB PIIX4 IDE (rev 01) 00:07.2 USB Controller: Intel Corp. 82371AB PIIX4 USB (rev 01) 00:07.3 Bridge: Intel Corp. 82371AB PIIX4 ACPI (rev 02) 00:11.0 VGA compatible controller: Silicon Integrated Systems [SiS] 86C326 (rev 0b) 00:14.0 Network and computing encryption device: Xilinx, Inc.: Unknown device cafe (rev 01) I setup the FPGA config regs as follows (lspci -vv): 00:14.0 Network and computing encryption device: Xilinx, Inc.: Unknown device cafe (rev 01) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 128 (32000ns min) Interrupt: pin A routed to IRQ 11 Region 0: Memory at e0070000 (32-bit, non-prefetchable) [size=256] Region 1: Memory at e0071000 (32-bit, non-prefetchable) [size=256] Region 2: Memory at df800000 (32-bit, non-prefetchable) [size=8M]Article: 86386
Geoffrey, There is no really a number, at least I never got an accurate one, for safety of adding the new block to a design., but... If the FIFO you add has nothing to do with the multipliers, and FPGA usage is, say, less than 80%, I would not worry. But if you do.... well, it's always a good idea to maximize the frequency for using less multipliers for DSP filter design, where DCM could be highly useful, but here comes the trade-off... The rest of the logic should be pipelined enough to undertake the timing constraints. Always check out the timing report. 75 MHz is pretty nice & easy frequency nowadays... Hope this helps. Vladislav "geoffrey wall" <wallge@eng.fsu.edu> wrote in message news:d9eo96$31b$1@news.fsu.edu... >I have been wondering about how to use DCMs in a design > lets say im doing some dsp filter design and I want my embedded > multipliers > to run as fast as possible. I synthesize my design using ISE or some other > tool > and my design synthesizes with a clock rate of say 75 mhz. Now lets say I > add > my DCMs and asychronous FIFO's to this design around the embedded > multipliers. > The thing that worries me is that i still have some delays in my clock > signal, as well > as in the data signals in my design. When I use the DCM, how do i know > that the clock > wont switch faster than the device can actually register? When designing > something like > this how do you know what is a safe multiplication factor so that all > signals will behave as expected? > > thanks > -- > Geoffrey Wall > Masters Student in Electrical/Computer Engineering > Florida State University, FAMU/FSU College of Engineering > wallge@eng.fsu.edu > Cell Phone: > 850.339.4157 > > ECE Machine Intelligence Lab > http://www.eng.fsu.edu/mil > MIL Office Phone: > 850.410.6145 > > Center for Applied Vision and Imaging Science > http://cavis.fsu.edu/ > CAVIS Office Phone: > 850.645.2257 >Article: 86387
Hey Jim, UCF file is included. start-up clock selection... hmmmmmmmmmm.... I just used the same file that is generated through GUI, is it good enough? Many thanks Vladislav "Jim George" <send_no_spam_to_jimgeorge@gmail.com> wrote in message news:WMKdnQ582qJwPCbfRVn-pg@comcast.com... > Vladislav Muravin wrote: >> One more thing to add I am using WinXP >> >> Vladislav >> >> >> "Vladislav Muravin" <muravinv@advantech.ca> wrote in message >> news:90zue.74585$Kk4.909792@news20.bellglobal.com... >> >>>Hello all, >>> >>>I am having a strange thing happening. >>>This was not urgent, so i kinda did not post it previously... >>> >>>I have a design synthesized for XC2V2000-FG686-4 or XC2V3000-FG686-4 >>> >>>(one) When running the entire ISE flow, everything is smooth, the PROM >>>files are generated >>>using two devices 1804v, one 100% full and another 65% full. FPGA is >>>fully functional and everything is working. >>> >>>(two) When running the same using command line, i get that PROM files are >>>generated >>>using two devices 1804v, one 100% full and another 62% full. When >>>programming FPGA with this configuration, >>>nothing is working. the LEDs which blink once a second per different >>>clock domains are "dead"... >>> >>>I have noticed this with both ISE 6.3 and 7.1 >>> >>>The question is what the hell is happening here? >>> >>>Thank you all for your time and attention >>> >>>Sincerely, >>>Vladislav >>> >> >> >> > > Startup clock selection? .UCF file not included in command line version? > (happened to me, resulted in a smoked board :( )Article: 86388
Hi there, I am having trouble with Xilinx Webpack 7.1i, trying to program a chain of 2 Spartan II FPGA's in slave serial mode. I am not using any Slave Serial pod, but rather feeding the FPGA's chain with a bit stream pumped from a parallel PROM file, created in .EXO (EXormacs) format. I guess lots of people do that. The PROM is itself created by ISE, following the links "Generate Programming File", "Generate Prom, ACE or JTAG". At the end of the programming, the FPGA's chain has its DONE pin pulled down (programming not successful). Fortunately, I am lucky enough to have kept on another old PC a copy of a program named PROMFMTR, dating of the old times of the Foundation tool, that was dedicated to prom making only I believe. So, I fed that good old program with my two .bit files and TO MY SURPRISE, everything was the same up to the last two lines in the .EXO file. The PROMFMTR program creates one more line than the ISE tool. That line is essentially all 0's in the data field (4 additional bytes). Googling a bit seems to indicate that Spartan II FPGAs (also others ?) require a few more clocks to get out of their internal state machine and start to work. That is probably why the additional 4 bytes (forgotten in Ise ?). If that is true, how comes that no one has ever seen that at Xilinx ? It is such a big flaw if true. NOTE: I am using the same ISE program with Spartan3 FPGAS, but the additional bytes are there, and they load perfect with the same end to end tools. Any idea ? Thanks for your help.Article: 86389
Anyone have experience putting multiple microblaze's in a single FPGA ?? Is it practical to put 2/4/8 processors in a single device and have them share a single DDR DRAM memory subsystem ? -- StuartArticle: 86390
"uxello" <uxello@free.fr> wrote in message news:42c00678$0$31776$636a15ce@news.free.fr... > Write accesses to SDRAM are very fast, since I can burst > as many words as I want (in my case, 48 words), resulting > in a 130MB/s bandwith. Writes are always much faster in PCI since most bridges provide FIFOs and allow posted writes. > > However, read accesses bursts are limited by the target > (SDRAM controller or just the PCI arbiter, I don't know) > to eight word transfers, resulting in a very poor 50MB/s I wouldn't call 50 MByte/second reads into the PC's SDRAM slow! That's about as fast as I'd expect (based on experience) in a 32/33 machine. What kind of speeds were you expecting and, more importantly, what do you need? > bandwidth. The target always asserts the STOP# pin after > the 8th word transfer resulting in a "disconnect without > data transfer". Well, since this is the PC's sdram, they may want to limit the bandwidth you get into it. ---- Ron Huizen BittWareArticle: 86391
Hello Everybody ! I have looking for FPGA PC104 development board for some time. I like to buy PC104 development board with new generation of FPGAs/CPLDs. I think it is not good decision to buy board with old FPGAs or CPLDs (Xilinx: Spartan, Spartan 2, Virtex E.. or Altera: Flex, ACEX or APEX..), because of providing these devices in future. ????? Until now I have found only one vendor which have PC104 card with Virtex 2 (http://www.derivation.com/), but this is big animal for my necessity :) Also I have found some vendors which offer PC104 development board with old FPGAs (Nova Engineering, APS, Mesa Electronics,Arius). Probably the main reason why new FPGAs are not used on PC104 development board is that PC104 bus is 5V and the most new FPGAs/CPLDs are not 5V tolerant?????? Do you know any vendor which manufactured FPGA PC104 card with new generations of FPGAs/CPLDs? I do not need any special peripherals in first development cycle. I need some memory (???), enough(???) I/O pins (3.3V, 5V), oscillator (???), JTAG, UART... And do you know where I can get ISA bus specifications??? thank you, Regards, AmirArticle: 86392
Thank you Ron for your reply: > Writes are always much faster in PCI since most bridges provide FIFOs and > allow posted writes. Probably, but SDRAM can accept bursts larger than 8-words, I do understand the pretty long latency (around 12 clocks), due to the host bridge, but I don't understand the 8-word limitation. Do you think the limitation is downto the chipset or the sdram and in a more recent PC, I would not have such a limitation ? > I wouldn't call 50 MByte/second reads into the PC's SDRAM slow! That's > about as fast as I'd expect (based on experience) in a 32/33 machine. What > kind of speeds were you expecting and, more importantly, what do you need? The thing is that to be efficient, I have to burst out from SDRAM 1024 32-bit words, and burst into SDRAM 768 words, and this results in a bus monopolization of around 121us for reads, and less than 50us for writes. Which is more accepatble. Moreover, writes are devided in 'small' 48-word bursts, giving a monopolization of just 3us per burst. The total PCI bus load in my application is: Acquisition card -> SDRAM : input bitrate=100Mbit SDRAM -> FPGA card : transfer bitrate=125Mbit FPGA card -> SDRAM : transfer bitrate=100Mbit SDRAM -> Ethernet card : output bitrate=100Mbit As you can see, if my 125Mbit (SDRAM->FPGA) takes actually the equivalent of a 250Mbits transfer because of poor latency and short burst for read accesses, the arbiter will have a hard job ! > Well, since this is the PC's sdram, they may want to limit the bandwidth you > get into it. You are probably right, but their might be a meant to disable this bandwidth limitation, your don't think so ? Why can i have a 1Gbit/s in one sens, and only 400Mbit/s in the other sens ? Regards, UxelloArticle: 86393
Hi, I figured out that my VSYNC is negativ polarity, although my EDID says its positiv.... It know also that it's only one pulse per frame. The other questions are still open. regards, BenjaminArticle: 86394
"Joey" <johnsons@kaiserslautern.de> wrote in message news:d9gmke$odj$1@news.uni-kl.de... > Hi > > I have a small question. > > I have a PLB Peripheral with "Software Addressable Registers". Say the > baseaddress of my peripheral is 0x90000000 . I have five 64bit registers in > my logic. So, the addresses of each of the registers would be baseaddress > plus 0x00, 0x08, 0x10, 0x18 and 0x20 respectively. What happens when I try > to read, or what would be the output when I read the memory addresses in > between. It depends on how you implement those registers. Normally, Bus2IP_BE plays role besides Bus2IP_RdCE/WrCE and the IPIF has byte-steering logic to put the byte to the correct lane. So you should be able to do byte read/write. > > I always believed that the "Bus2IP_WrCE"signal will assume only "10000", > "01000", "00100", "00010" and "00001" and the corresponding register values > would be read out from the corresponding registers. Is it possible that I Your assumption is correct, but you'll also need Bus2IP_BE in order to support writing to individual byte. > can read out the values "byte-shifted"? > >Article: 86395
Hi All,
I'm after a piece of FPGA or DSP-based hardware for the purposes of
performing real time video processing on digital high bandwidth video -
typically DVI 1280x1024 @ 60Hz.
Can anybody recommend a board (either PCI/PC or VME based) that would have
the appropriate DVI-like inputs and outputs and which would be likley to
have sufficient bandwidth to handle this resolution?.
Any comments or suggestions are sgratefully receieved.
Ta,
Dave
Article: 86396hello, I use an APEX 20k1000c. I insert nodes for signaltap, re-compile it and now the only things i have is "post-triggering" when it acquires signals but it seems the signals are stucked to '1'. I didn't give a value for "input trigger", is it a problem ? First it displays : Waiting for clock => I reset the device with DEVCLRn and then it displays : "post triggering". Does it means the trigger condition occurs and i can't see the data because i use a circular buffer which overwrite the trigger time (I hope i'm quite understandable) ? Can someone helps me? ThanksArticle: 86397
Not to mention the fact human players don't build (search) trees. My theory is that to beat machines, we have to start to think like them :)Article: 86398
I see two issues here looking for the classical design practices. Consider a solution space scanner feeding a N-stage pipeline calculating the quality of the solution. As soon as the quality appears satisfactory, we stop the pipeline and show the solution to the user. How do you determine which data was entering the pipeline just N steps earlier? [space explorer] || || (solution) \/ [stage 1] || \/ [stage 2] ... || \/ [stage n] || || (quality) \/ [constraint analyzer] One of the opportunities would be to supply a "solution" tag to each pipeline stage. Nevertheless, the solution may take large room (8 bytes in my case x16 stages, could be not too much for an FPGA?). Another option would be to exploit the knowlenge of current solution entering the pipe. As we know there is N stages we can roll N solutions back (topSol = EnteringSol - N) and calculate the one at the top of the pipeline. Another question is related to activating the pipeline-listening logic. As there is N-stage latency, the output will be not valid during that period and the [constraint analyzer] should be sleeping. Please give me the clues, thanks in advance, any references appreciated.Article: 86399
>However, read accesses bursts are limited by the target >(SDRAM controller or just the PCI arbiter, I don't know) >to eight word transfers, resulting in a very poor 50MB/s >bandwidth. The target always asserts the STOP# pin after >the 8th word transfer resulting in a "disconnect without >data transfer". Is it stopping at the end of a cache block? What PCI command are you using? I forget the details, but there is one that tells the host bridge that you want to do a long read, hinting that it should prefetch the next cache block while you read the current one. Of course, the system is free to ignore that hint and probably will if your read crosses a page boundary in the RAMs. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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